Stack Pointer - Atmel ATtiny25 Manual

4.5.1 The X-register, Y-register, and Z-register
4.6

Stack Pointer

ATtiny25/45/85
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The registers R26..R31 have some added functions to their general purpose usage. These reg-
isters are 16-bit address pointers for indirect addressing of the data space. The three indirect
address registers X, Y, and Z are defined as described in
Figure 4-3. The X-, Y-, and Z-registers
15
X-register 7
R27 (0x1B)
15
Y-register 7
R29 (0x1D)
15
Z-register 7
R31 (0x1F)
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always points
to the top of the Stack. Note that the Stack is implemented as growing from higher memory loca-
tions to lower memory locations. This implies that a Stack PUSH command decreases the Stack
Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program before
any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to
point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack
with the PUSH instruction, and it is decremented by two when the return address is pushed onto
the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is
popped from the Stack with the POP instruction, and it is incremented by two when data is
popped from the Stack with return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementa-
tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present.
Bit 15
SP15
SP7
7
Read/Write R/W
R/W
Initial Value 0
1
XH
YH
ZH
0
14 13 12
SP14 SP13 SP12
SP6 SP5 SP4
6 5 4
R/W R/W R/W
R/W R/W R/W
0 0 0
0 0 1
Figure 4-3.
XL
0 7
R26 (0x1A)
YL
0 7
R28 (0x1C)
ZL
7 0
R30 (0x1E)
11 10 9
SP11 SP10 SP9
SP3 SP2 SP1
3 2 1
R/W R/W R/W
R/W R/W R/W
0 0 0
1 1 1
0
0
0
0
0
8
SP8 SPH
SP0 SPL
0
R/W
R/W
0
1
7598H–AVR–07/09