Atmel AT90PWM2 Manual page 250

21.8.4 ADC Result Data Registers – ADCH and ADCL
21.8.4.1 ADLAR = 0
21.8.4.2 ADLAR = 1
21.8.5 Digital Input Disable Register 0 – DIDR0
4317I–AVR–01/08
Table 21-7. ADC Auto Trigger Source Selection for amplified conversions
ADTS3 ADTS2
1 0
1 0
1 1
1 1
1 1
1 1
1. For trigger on any PSC event, if the PSC uses the PLL clock, the core must use PLL/4 clock
source.
When an ADC conversion is complete, the conversion results are stored in these two result data
registers.
When the ADCL register is read, the two ADC result data registers can't be updated until the
ADCH register has also been read.
Consequently, in 10-bit configuration, the ADCL register must be read first before the ADCH.
Nevertheless, to work easily with only 8-bit precision, there is the possibility to left adjust the
result thanks to the ADLAR bit in the ADCSRA register. Like this, it is sufficient to only read
ADCH to have the conversion result.
Bit 7
-
ADC7
Read/Write R
R
Initial Value 0
0
Bit 7
ADC9
ADC1
Read/Write R
R
Initial Value 0
0
Bit 7
ADC7D
Read/Write R/W
Initial Value 0
• Bit 7:0 – ADC7D..ADC0D: ACMP2:1 and ADC7:0 Digital Input Disable
ADTS1 ADTS0
1 0
1 1
0 0
0 1
1 0
1 1
6 5 4
- - -
ADC6 ADC5 ADC4
R R R
R R R
0 0 0
0 0 0
6 5 4
ADC8 ADC7 ADC6
ADC0 - -
R R R
R R R
0 0 0
0 0 0
6 5 4
ADC6D ADC5D ADC4D
R/W R/W R/W
0 0 0
AT90PWM2/3/2B/3B
Description
(1)
PSC2ASY Event
Reserved
Reserved
Reserved
Reserved
Reserved
3 2 1
- - ADC9
ADC3 ADC2 ADC1
R R R
R R R
0 0 0
0 0 0
3 2 1
ADC5 ADC4 ADC3
- - -
R R R
R R R
0 0 0
0 0 0
3 2 1
ADC3D ADC2D ADC1D
ACMPM ACMP2D
R/W R/W R/W
0 0 0
0
ADC8 ADCH
ADC0 ADCL
R
R
0
0
0
ADC2 ADCH
- ADCL
R
R
0
0
0
ADC0D DIDR0
R/W
0
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