Atmel AT90PWM2 Manual
Atmel AT90PWM2 Manual

Atmel AT90PWM2 Manual

8-bit avr microcontroller with 8k bytes in-system programmable flash

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Features
High Performance, Low Power AVR ® 8-bit Microcontroller
Advanced RISC Architecture
– 129 Powerful Instructions - Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 1 MIPS throughput per MHz
– On-chip 2-cycle Multiplier
Data and Non-Volatile Program Memory
– 8K Bytes Flash of In-System Programmable Program Memory
• Endurance: 10,000 Write/Erase Cycles
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– 512 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– 512 Bytes Internal SRAM
– Programming Lock for Flash Program and EEPROM Data Security
On Chip Debug Interface (debugWIRE)
Peripheral Features
– Two or three 12-bit High Speed PSC (Power Stage Controllers) with 4-bit
Resolution Enhancement
• Non Overlapping Inverted PWM Output Pins With Flexible Dead-Time
• Variable PWM duty Cycle and Frequency
• Synchronous Update of all PWM Registers
• Auto Stop Function for Event Driven PFC Implementation
• Less than 25 Hz Step Width at 150 kHz Output Frequency
• PSC2 with four Output Pins and Output Matrix
– One 8-bit General purpose Timer/Counter with Separate Prescaler and Capture
Mode
– One 16-bit General purpose Timer/Counter with Separate Prescaler, Compare
Mode and Capture Mode
– Programmable Serial USART
• Standard UART mode
• 16/17 bit Biphase Mode for DALI Communications
– Master/Slave SPI Serial Interface
– 10-bit ADC
• Up To 11 Single Ended Channels and 2 Fully Differential ADC Channel Pairs
• Programmable Gain (5x, 10x, 20x, 40x on Differential Channels)
• Internal Reference Voltage
– 10-bit DAC
– Two or three Analog Comparator with Resistor-Array to Adjust Comparison
Voltage
– 4 External Interrupts
– Programmable Watchdog Timer with Separate On-Chip Oscillator
Special Microcontroller Features
– Low Power Idle, Noise Reduction, and Power Down Modes
– Power On Reset and Programmable Brown Out Detection
– Flag Array in Bit-programmable I/O Space (4 bytes)
8-bit
Microcontroller
with 8K Bytes
In-System
Programmable
Flash
AT90PWM2
AT90PWM3
AT90PWM2B
AT90PWM3B
4317I–AVR–01/08

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Summary of Contents for Atmel AT90PWM2

  • Page 1 • Peripheral Features – Two or three 12-bit High Speed PSC (Power Stage Controllers) with 4-bit Resolution Enhancement AT90PWM2 • Non Overlapping Inverted PWM Output Pins With Flexible Dead-Time AT90PWM3 • Variable PWM duty Cycle and Frequency • Synchronous Update of all PWM Registers •...
  • Page 2: History

    Extended Operating Temperature: – -40°C to +105° 12 bit PWM with Analog Product Package deadtime Input Diff Compar Application AT90PWM2 SO24 2 x 2 One fluorescent ballast AT90PWM2B AT90PWM3 SO32, HID ballast, fluorescent ballast, 3 x 2 QFN32 Motor control AT90PWM3B 1.
  • Page 3: Pin Configurations

    AT90PWM2/3/2B/3B 3. Pin Configurations Figure 3-1. SOIC 24-pin Package AT90PWM2/2B SOIC24 (PSCOUT00/XCK/SS_A) PD0 PB7(ADC4/PSCOUT01/SCK) (RESET/OCD) PE0 PB6 (ADC7/ICP1B) (PSCIN0/CLKO) PD1 PB5 (ADC6/INT2) (PSCIN2/OC1A/MISO_A) PD2 PB4 (AMP0+) (TXD/DALI/OC0A/SS/MOSI_A) PD3 PB3 (AMP0-) AREF (MISO/PSCOUT20) PB0 AVCC (MOSI/PSCOUT21) PB1 PB2 (ADC5/INT1) (OC0B/XTAL1) PE1...
  • Page 4: Pin Descriptions

    (MISO/PSCOUT20) PB0 Pin Descriptions Table 3-1. Pin out description S024 Pin SO32 Pin QFN32 Pin Number Number Number Mnemonic Type Name, Function & Alternate Function Power Ground: 0V reference AGND Power Analog Ground: 0V reference for analog part AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 5 AT90PWM2/3/2B/3B Table 3-1. Pin out description (Continued) S024 Pin SO32 Pin QFN32 Pin Number Number Number Mnemonic Type Name, Function & Alternate Function power Power Supply: Analog Power Supply: This is the power supply voltage for analog part AVCC Power For a normal use this pin must be connected.
  • Page 6: Overview

    1. PSCOUT10 & PSCOUT11 are not present on 24 pins package 4. Overview The AT90PWM2/2B/3/3B is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the AT90PWM2/2B/3/3B achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
  • Page 7: Block Diagram

    CISC microcontrollers. The AT90PWM2/2B/3/3B provides the following features: 8K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes EEPROM, 512 bytes SRAM, 53 general...
  • Page 8: Pin Descriptions

    Atmel AT90PWM2/3 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The AT90PWM2/3 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
  • Page 9: About Code Examples

    As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the AT90PWM2/2B/3/3B as listed page 4.2.6 Port E (PE2..0) RESET/ XTAL1/...
  • Page 10: Avr Cpu Core

    AT90PWM2/3/2B/3B 5. AVR CPU Core Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.
  • Page 11: Alu - Arithmetic Logic Unit

    SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the AT90PWM2/2B/3/3B has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.
  • Page 12: Status Register

    AT90PWM2/3/2B/3B Status Register The Status Register contains information about the result of the most recently executed arith- metic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference.
  • Page 13: General Purpose Register File

    The registers R26..R31 have some added functions to their general purpose usage. These reg- isters are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 5-3. Figure 5-3. The X-, Y-, and Z-registers AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 14: Stack Pointer

    AT90PWM2/3/2B/3B X-register R27 (0x1B) R26 (0x1A) Y-register R29 (0x1D) R28 (0x1C) Z-register R31 (0x1F) R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details).
  • Page 15: Reset And Interrupt Handling

    “Interrupts” on page 57 for more infor- mation. The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Pro- gramming” on page 265. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 16 AT90PWM2/3/2B/3B 5.8.1 Interrupt Behavior When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis- abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction –...
  • Page 17 A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 18: Memories

    The Flas h memory has an endur ance of at leas t 10,000 write/eras e cyc les. The AT90PWM2/2B/3/3B Program Counter (PC) is 12 bits wide, thus addressing the 4K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in “Boot Loader Support –...
  • Page 19 X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and the 512 bytes of internal data SRAM in the AT90PWM2/2B/3/3B are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File”...
  • Page 20: Eeprom Data Memory

    Next Instruction EEPROM Data Memory The AT90PWM2/2B/3/3B contains 512 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.
  • Page 21 Initial Value • Bits 15..9 – Reserved Bits These bits are reserved bits in the AT90PWM2/2B/3/3B and will always read as zero. • Bits 8..0 – EEAR8..0: EEPROM Address The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 512 bytes EEPROM space.
  • Page 22 AT90PWM2/3/2B/3B • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter- rupt when EEWE is cleared.
  • Page 23 The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 24 AT90PWM2/3/2B/3B Assembly Code Example EEPROM_write: ; Wait for completion of previous write sbic EECR,EEWE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to data register out EEDR,r16 ; Write logical one to EEMWE sbi EECR,EEMWE ;...
  • Page 25 BOD does not match the needed detection level, an external low V reset Protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be com- pleted provided that the power supply voltage is sufficient. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 26: I/O Memory

    “Register Summary” on page 337. All AT90PWM2/2B/3/3B I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions.
  • Page 27 6.5.4 General Purpose I/O Register 3– GPIOR3 GPIOR37 GPIOR36 GPIOR35 GPIOR34 GPIOR33 GPIOR32 GPIOR31 GPIOR30 GPIOR3 Read/Write Initial Value AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 28: System Clock

    In order to reduce power consumption, the clocks to unused modules can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 41. The clock systems are detailed below. Figure 7-1. Clock Distribution AT90PWM2/3 PSC0/1/2 General I/O Flash and CPU Core Modules...
  • Page 29 The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul- taneously with the CPU clock. 7.1.4 PLL Clock – clk The PLL clock allows the PSC modules to be clocked directly from a 64/32 MHz clock. A 16 MHz clock is also derived for the CPU. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 30: Clock Sources

    AT90PWM2/3/2B/3B 7.1.5 ADC Clock – clk The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results. Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as illustrated Table 7-1.
  • Page 31: Default Clock Source

    7-4. For ceramic resonators, the capacitor values given by the manufacturer should be used. For more information on how to choose capacitors and other details on Oscillator operation, refer to the Multi-purpose Oscillator Application Note. Figure 7-3. Crystal Oscillator Connections XTAL2 XTAL1 AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 32: Calibrated Internal Rc Oscillator

    AT90PWM2/3/2B/3B The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 7-4. Table 7-4. Crystal Oscillator Operating Modes Recommended Range for Capacitors C1 and CKSEL3..1...
  • Page 33 8.0 MHz at 25°C. The application software can write this register to change the oscillator frequency. The oscillator can be calibrated to any frequency in the range 7.3 - 8.1 MHz within ±1% accuracy. Calibration outside that range is not guaranteed. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 34: Pll

    7.6.1 Internal PLL for PSC The internal PLL in AT90PWM2/2B/3/3B generates a clock frequency that is 64x multiplied from nominally 1 MHz input. The source of the 1 MHz PLL input clock is the output of the internal RC Oscillator which is divided down to 1 MHz. See the...
  • Page 35 This value do not provide a proper restart ; do not use PD in this clock scheme This value do not provide a proper restart ; do not use PD in this clock scheme Figure 7-4. PCK Clocking System AT90PWM2/3 PLLF OSCCAL...
  • Page 36: 128 Khz Internal Oscillator

    Initial Value • Bit 7..3 – Res: Reserved Bits These bits are reserved bits in the AT90PWM2/2B/3/3B and always read as zero. • Bit 2 – PLLF: PLL Factor The PLLF bit is used to select the division factor of the PLL.
  • Page 37: Clock Output Buffer

    7.10 System Clock Prescaler The AT90PWM2/2B/3/3B system clock can be divided by setting the Clock Prescale Register – CLKPR. This feature can be used to decrease power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals.
  • Page 38 AT90PWM2/3/2B/3B When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting, nor the clock frequency corre- sponding to the new setting.
  • Page 39 The device is shipped with the CKDIV8 Fuse programmed. Table 7-12. Clock Prescaler Select CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor Reserved Reserved Reserved Reserved Reserved Reserved Reserved AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 40: Power Management And Sleep Modes

    If a reset occurs during sleep mode, the MCU wakes up and exe- cutes from the Reset Vector. Figure 7-1 on page 29 presents the different clock systems in the AT90PWM2/2B/3/3B, and their distribution. The figure is helpful in selecting an appropriate sleep mode. 8.0.1 Sleep Mode Control Register –...
  • Page 41: Idle Mode

    Reset Time-out period, as described in “Clock Sources” on page Standby Mode When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 42: Power Reduction Register

    AT90PWM2/3/2B/3B with the exception that the Oscillator is kept running. From Standby mode, the device wakes up in six clock cycles. Table 8-2. Active Clock Domains and Wake-up Sources in the Different Sleep Modes. Oscillator Active Clock Domains Wake-up Sources...
  • Page 43: Minimizing Power Consumption

    Internal Voltage Reference as input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independent of sleep mode. Refer to “Analog Comparator” on page 227 for details on how to configure the Analog Comparator. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 44 AT90PWM2/3/2B/3B 8.6.3 Brown-out Detector If the Brown-out Detector is not needed by the application, this module should be turned off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute sig- nificantly to the total current consumption.
  • Page 45: System Control And Reset

    “Clock Sources” on page 9.0.2 Reset Sources The AT90PWM2/2B/3/3B has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V •...
  • Page 46 AT90PWM2/3/2B/3B Figure 9-1. Reset Logic DATA BUS MCU Status Register (MCUSR) Power-on Reset Circuit Brown-out Reset Circuit BODLEVEL [2..0] Pull-up Resistor Spike Filter Watchdog Oscillator Delay Counters Clock TIMEOUT Generator CKSEL[3:0] SUT[1:0] Table 9-1. Reset Characteristics Symbol Parameter Condition Min.
  • Page 47 Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – V – on its positive edge, the delay counter starts the MCU after the Time-out period – t – has expired. TOUT Figure 9-4. External Reset During Operation AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 48 9.0.5 Brown-out Detection AT90PWM2/2B/3/3B has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection.
  • Page 49 • Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 1 – EXTRF: External Reset Flag AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 50: Internal Voltage Reference

    MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags. Internal Voltage Reference AT90PWM2/2B/3/3B features an internal bandgap reference (1.1V). This reference is used for Brown-out Detection. can be used as A 2.56V voltage reference is generated thanks to the bandgap...
  • Page 51: Watchdog Timer

    WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. 2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as desired, but with the WDCE bit cleared. This must be done in one operation. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 52 AT90PWM2/3/2B/3B The following code example shows one assembly and one C function for turning off the Watch- dog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of these functions.
  • Page 53 WDIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 54 AT90PWM2/3/2B/3B • Bit 6 - WDIE: Watchdog Interrupt Enable When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer occurs.
  • Page 55 64 ms 16K (16384) cycles 0.125 s 32K (32768) cycles 0.25 s 64K (65536) cycles 0.5 s 128K (131072) cycles 1.0 s 256K (262144) cycles 2.0 s 512K (524288) cycles 4.0 s 1024K (1048576) cycles 8.0 s Reserved AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 56: Interrupts

    T h i s s e c t i o n d e s c r i b e s t h e s p e c i f i c s o f t h e i n t e r r u p t h a n d l i n g a s p e r f o r m e d i n AT90PWM2/2B/3/3B. For a general explanation of the AVR interrupt handling, refer to “Reset...
  • Page 57 Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 10-2. Reset and Interrupt Vectors Placement in AT90PWM2/2B/3/3B BOOTRST IVSEL Reset Address...
  • Page 58 When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses in AT90PWM2/2B/3/3B is: Address Labels Code...
  • Page 59 When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses in AT90PWM2/2B/3/3B is: Address Labels Code Comments .org 0xC00...
  • Page 60 AT90PWM2/3/2B/3B Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling.
  • Page 61: O-Ports

    I/O. 11.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 11-2 shows a func- tional description of one I/O-port pin, here generically called Pxn. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 62: Ports As General Digital I/O

    AT90PWM2/3/2B/3B Figure 11-2. General Digital I/O DDxn RESET PORTxn RESET SLEEP SYNCHRONIZER PINxn WDx: WRITE DDRx PUD: PULLUP DISABLE RDx: READ DDRx SLEEP: SLEEP CONTROL WRx: WRITE PORTx : I/O CLOCK RRx: READ PORTx REGISTER RPx: READ PORTx PIN WPx: WRITE PINx REGISTER Note: 1.
  • Page 63 Figure 11-3 shows a timing dia- gram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation delays are denoted t and t respectively. pd,max pd,min AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 64 AT90PWM2/3/2B/3B Figure 11-3. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS in r17, PINx SYNC LATCH PINxn 0x00 0xFF pd, max pd, min Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH”...
  • Page 65 “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned sleep modes, as the clamping in these sleep modes produces the requested logic change. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 66: Alternate Port Functions

    AT90PWM2/3/2B/3B 11.3 Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. Figure 11-5 shows how the port pin control signals from the simplified Figure 11-2 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family.
  • Page 67 Refer to the alternate function description for further details. 11.3.1 MCU Control Register – MCUCR SPIPS – – – – IVSEL IVCE MCUCR Read/Write Initial Value • Bit 4 – PUD: Pull-up Disable AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 68 AT90PWM2/3/2B/3B When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). Se 11.3.2 Alternate Functions of Port B...
  • Page 69 PSCen11 PSCout01 • SPIPS + PSCout01 • PSCen01 • SPIPS PVOV PSCOUT11 + PSCout01 • PSCen01 • SPIPS DIEOE ADC4D ADC7D ADC6D + In2en AMP0ND DIEOV In2en SCKin • SPIPS • ICP1B INT2 ireset ADC4 ADC7 ADC6 AMP0+ AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 70 AT90PWM2/3/2B/3B Table 11-5. Overriding Signals for Alternate Functions in PB3..PB0 PB1/MOSI/ PB0/MISO/ Signal Name PB3/AMP0- PB2/ADC5/INT1 PSCOUT21 PSCOUT20 PUOE – – PUOV – – DDOE – – DDOV – – PVOE – – PVOV – – DIEOE AMP0ND ADC5D + In1en...
  • Page 71 This pin is also the output pin for the PWM mode timer function. • PSCOUT10/INT3 – Bit 0 PSCOUT10: Output 0 of PSC 1. INT3, External Interrupt source 3: This pin can serve as an external interrupt source to the MCU. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 72 AT90PWM2/3/2B/3B Table 11-7 Table 11-8 relate the alternate functions of Port C to the overriding signals shown in Figure 11-5 on page Table 11-7. Overriding Signals for Alternate Functions in PC7..PC4 PC6/ADC10/ PC5/ADC9/ PC4/ADC8/ Signal Name PC7/D2A ACMP1 AMP1+ AMP1-...
  • Page 73 Ana- log Comparator. INT0, External Interrupt source 0. This pin can serve as an external interrupt source to the MCU. • ADC2/ACMP2 – Bit 5 ADC2, Analog to Digital Converter, input channel 2. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 74 AT90PWM2/3/2B/3B ACMP2, Analog Comparator 1 Positive Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Ana- log Comparator. • ADC1/RXD/ICP1/SCK_A – Bit 4 ADC1, Analog to Digital Converter, input channel 1.
  • Page 75 PD4 • PUOV RXEN + SPE • DDOE MSTR • SPIPS DDOV SPE • MSTR • PVOE SPIPS PVOV – DIEOE ACMP0D ADC3D + In0en ADC2D ADC1D DIEOV In0en – INT0 ICP1A ADC3 ADC2 ACOMP0 ADC1 ACMPM ACOMP2 AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 76 AT90PWM2/3/2B/3B Table 11-11. Overriding Signals for Alternate Functions in PD3..PD0 PD3/TXD/OC0A/ PD2/PSCIN2/ PD1/PSCIN0/ PD0/PSCOUT00/X Signal Name SS/MOSI_A OC1A/MISO_A CLKO CK/SS_A TXEN + SPE • SPE • PUOE – MSTR • SPIPS MSTR • SPIPS TXEN • SPE • MSTR PUOV –...
  • Page 77: Register Description For I/O-Ports

    Register Description for I/O-Ports 11.4.1 Port B Data Register – PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 PORTB Read/Write Initial Value 11.4.2 Port B Data Direction Register – DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRB Read/Write AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 78 AT90PWM2/3/2B/3B Initial Value 11.4.3 Port B Input Pins Address – PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 PINB Read/Write Initial Value 11.4.4 Port C Data Register – PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 PORTC Read/Write Initial Value 11.4.5...
  • Page 79 Port E Data Direction Register – DDRE – – – – – DDE2 DDE1 DDE0 DDRE Read/Write Initial Value 11.4.12 Port E Input Pins Address – PINE – – – – – PINE2 PINE1 PINE0 PINE Read/Write Initial Value AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 80: External Interrupts

    AT90PWM2/3/2B/3B 12. External Interrupts The External Interrupts are triggered by the INT3:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT3:0 pins are configured as outputs. This feature provides a way of gen- erating a software interrupt. The External Interrupts can be triggered by a falling or rising edge or a low level.
  • Page 81 (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. These flags are always cleared when INT3:0 are configured as level interrupt. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 82: Timer/Counter0 And Timer/Counter1 Prescalers

    AT90PWM2/3/2B/3B 13. Timer/Counter0 and Timer/Counter1 Prescalers Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. 13.0.1 Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This...
  • Page 83 When the TSM bit is written to zero, the PSRSYNC bit is cleared by hardware, and the Timer/Counters start counting simultaneously. • Bit6 – ICPSEL1: Timer 1 Input Capture selection AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 84 AT90PWM2/3/2B/3B Timer 1 capture function has two possible inputs ICP1A (PD4) and ICP1B (PB6). The selection is made thanks to ICPSEL1 bit as described in Table Table 13-1. ICPSEL1 ICPSEL1 Description Select ICP1A as trigger for timer 1 input capture Select ICP1B as trigger for timer 1 input capture •...
  • Page 85: 14 8-Bit Timer/Counter0 With Pwm

    Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing Timer/Counter0 counter value and so on. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 86: Timer/Counter Clock Sources

    AT90PWM2/3/2B/3B The definitions in Table 14-1 are also used extensively throughout the document. Table 14-1. Definitions BOTTOM The counter reaches the BOTTOM when it becomes 0x00. The counter reaches its MAXimum when it becomes 0xFF (decimal 255). The counter reaches the TOP when it becomes equal to the highest value in the count sequence.
  • Page 87: Output Compare Unit

    Waveform Generator for handling the special cases of the extreme values in some modes of operation (“Modes of Operation” on page 91). Figure 14-3 shows a block diagram of the Output Compare unit. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 88 AT90PWM2/3/2B/3B Figure 14-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn (8-bit Comparator ) OCFnx (Int.Req.) bottom Waveform Generator OCnx FOCn WGMn1:0 COMnx1:0 The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou- ble buffering is disabled.
  • Page 89: Compare Match Output Unit

    The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM0x1:0 = 0 tells the Waveform Generator that no action on the OC0x Register is to be performed on the next compare match. For compare output actions in the AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 90: Modes Of Operation

    AT90PWM2/3/2B/3B non-PWM modes refer to Table 14-2 on page 97. For fast PWM mode, refer to Table 14-3 on page 97, and for phase correct PWM refer to Table 14-4 on page A change of the COM0x1:0 bits state will have effect at the first compare match after the bits are written.
  • Page 91 The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 14-6. The TCNT0 value is in the timing diagram shown as a his- togram for illustrating the single-slope operation. The diagram includes non-inverted and AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 92 AT90PWM2/3/2B/3B inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0x and TCNT0. Figure 14-6. Fast PWM Mode, Timing Diagram OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set TCNTn (COMnx1:0 = 2)
  • Page 93 The PWM waveform is generated by clearing (or setting) the OC0x Register at the compare match between OCR0x and TCNT0 when the counter increments, and setting (or clearing) the OC0x Register at compare AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 94: Timer/Counter Timing Diagrams

    AT90PWM2/3/2B/3B match between OCR0x and TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: clk_I/O ----------------- - ⋅ OCnxPCPWM N 510 The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
  • Page 95: 8-Bit Timer/Counter Register Description

    (f clk_I/O (clk TCNTn TOP - 1 BOTTOM BOTTOM + 1 (CTC) OCRnx OCFnx 14.8 8-bit Timer/Counter Register Description 14.8.1 Timer/Counter Control Register A – TCCR0A COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 TCCR0A Read/Write Initial Value AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 96 AT90PWM2/3/2B/3B • Bits 7:6 – COM0A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected to.
  • Page 97 “Phase Correct PWM Mode” on page 93 for more details. • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the AT90PWM2/2B/3/3B and will always read as zero. • Bits 1:0 – WGM01:0: Waveform Generation Mode AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 98 AT90PWM2/3/2B/3B Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of wave- form generation to be used, see Table 14-8. Modes of operation supported by the Timer/Counter...
  • Page 99 The FOC0B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the AT90PWM2/2B/3/3B and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the “Timer/Counter Control Register A –...
  • Page 100 Initial Value • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the AT90PWM2/2B/3/3B and will always read as zero. • Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled.
  • Page 101 When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Table 14-8, “Waveform Generation Mode Bit Description” on page AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 102: 16-Bit Timer/Counter1 With Pwm

    AT90PWM2/3/2B/3B 15. 16-bit Timer/Counter1 with PWM The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: • True 16-bit Design (i.e., Allows 16-bit PWM) • Two independent Output Compare Units •...
  • Page 103 PWM or variable frequency output on the Output Compare pin (OCnx). See “Output Compare Units” on page 111. The compare match event will also set the Compare Match Flag (OCFnx) which can be used to generate an Output Compare interrupt request. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 104: Accessing 16-Bit Registers

    AT90PWM2/3/2B/3B The Input Capture Register can capture the Timer/Counter value at a given external (edge trig- gered) event on either the Input Capture pin (ICPn). The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes.
  • Page 105 Therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 106 AT90PWM2/3/2B/3B The following code examples show how to do an atomic read of the TCNTn Register contents. Reading any of the OCRnx or ICRn Registers can be done by using the same principle. Assembly Code Example TIM16_ReadTCNTn: ; Save global interrupt flag in r18,SREG ;...
  • Page 107 Clock Select logic which is controlled by the Clock Select (CSn2:0) bits located in the Timer/Counter control Register B (TCCRnB). For details on clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on page AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 108 AT90PWM2/3/2B/3B 15.4 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 15-2 shows a block diagram of the counter and its surroundings. Figure 15-2. Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int.Req.)
  • Page 109 (WGMn3:0) bits must be set before the TOP value can be written to the ICRn Register. When writing the ICRn Register the high byte must be written to the ICRnH I/O location before the low byte is written to ICRnL. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 110 AT90PWM2/3/2B/3B For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 105. 15.5.1 Input Capture Trigger Source The trigger sources for the Input Capture unit arethe Input Capture pin (ICP1A & ICP1B). Be aware that changing trigger source can trigger a capture. The Input Capture Flag must there- fore be cleared after the change.
  • Page 111 16-bit registers. Writing the OCRnx Registers must be done via the TEMP Reg- ister since the compare of all 16 bits is done continuously. The high byte (OCRnxH) has to be written first. When the high byte I/O location is written by the CPU, the TEMP Register will be AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 112 AT90PWM2/3/2B/3B updated by the value written. Then when the low byte (OCRnxL) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the OCRnx buffer or OCRnx Compare Register in the same system clock cycle.
  • Page 113 The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGMn3:0) and Compare Output mode (COMnx1:0) bits. The Compare Output mode bits do not affect the counting sequence, AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 114 AT90PWM2/3/2B/3B while the Waveform Generation mode bits do. The COMnx1:0 bits control whether the PWM out- put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COMnx1:0 bits control whether the output should be set, cleared or toggle at a compare match (See “Compare Match Output Unit”...
  • Page 115 The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when a compare match occurs. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 116 AT90PWM2/3/2B/3B Figure 15-7. Fast PWM Mode, Timing Diagram OCRnx/TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches TOP. In addition the OCnA or ICFn Flag is set at the same timer clock cycle as TOVn is set when either OCRnA or ICRn is used for defining the TOP value.
  • Page 117 The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx Inter- rupt Flag will be set when a compare match occurs. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 118 AT90PWM2/3/2B/3B Figure 15-8. Phase Correct PWM Mode, Timing Diagram OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM.
  • Page 119 The diagram includes non- inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes repre- sent compare matches between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when a compare match occurs. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 120 AT90PWM2/3/2B/3B Figure 15-9. Phase and Frequency Correct PWM Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Updateand TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3)
  • Page 121 PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOVn Flag at BOTTOM. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 122 AT90PWM2/3/2B/3B Figure 15-12. Timer/Counter Timing Diagram, no Prescaling (clk TCNTn TOP - 1 BOTTOM BOTTOM + 1 (CTC and FPWM) TCNTn TOP - 1 TOP - 1 TOP - 2 (PC and PFC PWM) TOVn (FPWM) and ICFn (if used...
  • Page 123 COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase correct or the phase and frequency correct, PWM mode. Table 15-3. Compare Output Mode, Phase Correct and Phase and Frequency Correct COMnA1/COMnB1 COMnA0/COMnB0 Description Normal port operation, OCnA/OCnB disconnected. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 124 AT90PWM2/3/2B/3B Table 15-3. Compare Output Mode, Phase Correct and Phase and Frequency Correct COMnA1/COMnB1 COMnA0/COMnB0 Description WGMn3:0 = 8, 9 10 or 11: Toggle OCnA on Compare Match, OCnB disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected.
  • Page 125 No clock source (Timer/Counter stopped). /1 (No prescaling) /8 (From prescaler) /64 (From prescaler) /256 (From prescaler) /1024 (From prescaler) External clock source on Tn pin. Clock on falling edge. External clock source on Tn pin. Clock on rising edge. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 126 AT90PWM2/3/2B/3B If external pin modes are used for the Timer/Countern, transitions on the Tn pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 15.10.3 Timer/Counter1 Control Register C – TCCR1C...
  • Page 127 Initial Value • Bit 7, 6 – Res: Reserved Bits These bits are unused bits in the AT90PWM2/2B/3/3B, and will always read as zero. • Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled.
  • Page 128 Initial Value • Bit 7, 6 – Res: Reserved Bits These bits are unused bits in the AT90PWM2/2B/3/3B, and will always read as zero. • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGMn3:0 to be used as the TOP value, the ICF1 Flag is set when the counter reaches the TOP value.
  • Page 129 The PSC can be chained and synchronized to provide a configuration to drive three half bridges. Thanks to this feature it is possible to generate a three phase waveforms for applications such as Asynchronous or BLDC motor drive. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 130 AT90PWM2/3/2B/3B 16.3 PSC Description Figure 16-1. Power Stage Controller 0 or 1 Block Diagram PSC Counter Waveform PSCOUTn1 Generator B ( From Analog OCRnRB Comparator n Ouput ) PSC Input PSCn Input B Module B OCRnSB PISELnB Part B PSCn Input A...
  • Page 131 (See “Output Matrix” on page 158.) 16.3.2 Output Polarity The polarity “active high” or “active low” of the PSC outputs is programmable. All the timing dia- grams in the following examples are given in the “active high” polarity. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 132 AT90PWM2/3/2B/3B 16.4 Signal Description Figure 16-3. PSC External Block View SYnIn StopOut OCRnRB[11:0] PSCOUTn0 OCRnSB[11:0] PSCOUTn1 OCRnRA[11:0] PSCOUTn2 OCRnSA[11:0] PSCOUTn3 OCRnRB[15:12] (Flank Width Modulation) PICRn[11:0] PSCINn IRQ PSCn Analog Comparator n Output StopIn SYnOut PSCnASY Note: 1. available only for PSC2 2.
  • Page 133 PSC Interrupt Request : three souces, overflow, fault, and input IRQPSCn Signal capture PSCnASY ADC Synchronization (+ Amplifier Syncho. ) Signal StopOut Stop Output (for synchronized mode) Note: 1. See Figure 16-38 on page 159 See “Analog Synchronization” on page 158. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 134 AT90PWM2/3/2B/3B 16.5 Functional Description 16.5.1 Waveform Cycles The waveform generated by PSC can be described as a sequence of two waveforms. The first waveform is relative to PSCOUTn0 output and part A of PSC. The part of this waveform is sub-cycle A in the following figure.
  • Page 135 In Two Ramp mode, the whole cycle is divided in two moments One moment for PSCn0 description with OT0 which gives the time of the whole moment One moment for PSCn1 description with OT1 which gives the time of the whole moment AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 136 AT90PWM2/3/2B/3B Figure 16-7. PSCn0 & PSCn1 Basic Waveforms in Two Ramp mode OCRnRA OCRnRB PSC Counter OCRnSA OCRnSB On-Time 0 On-Time 1 PSCOUTn0 PSCOUTn1 Dead-Time 0 Dead-Time 1 PSC Cycle PSCOUTn0 and PSCOUTn1 signals are defined by On-Time 0, Dead-Time 0, On-Time 1 and...
  • Page 137 Dead-Time 0 = (OCRnSAH/L + 1) * 1/Fclkpsc Dead-Time 1 = (OCRnSBH/L - OCRnRAH/L) * 1/Fclkpsc Note: Minimal value for Dead-Time 0 = 1/Fclkpsc 16.5.2.4 Center Aligned Mode In center aligned mode, the center of PSCn00 and PSCn01 signals are centered. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 138 AT90PWM2/3/2B/3B Figure 16-9. PSCn0 & PSCn1 Basic Waveforms in Center Aligned Mode PSC Counter OCRnRB OCRnSB OCRnSA On-Time 0 On-Time 1 On-Time 1 PSCOUTn0 PSCOUTn1 (AT90PWM2/3) PSCOUTn1 (AT90PWM2B/3B) Dead-Time Dead-Time PSC Cycle On-Time 0 = 2 * OCRnSAH/L * 1/Fclkpsc...
  • Page 139 Lamp Ballast applications need an enhanced resolution down to 50Hz. The method to improve the normal resolution is based on Flank Width Modulation (also called Fractional Divider). Cycles are grouped into frames of 16 cycles. Cycles are modulated by a sequence given by the AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 140 AT90PWM2/3/2B/3B fractional divider number. The resulting output frequency is the average of the frequencies in the frame. The fractional divider (d) is given by OCRnRB[15:12]. The PSC output period is directly equal to the PSCOUTn0 On Time + Dead Time (OT0+DT0) and PSCOUTn1 On Time + DeadTime (OT1+DT1) values.
  • Page 141 While ‘X’ in the table, f prime to f in cycle corresponding cycle. So for each row, a number of fb2 take place of fb1. Figure 16-12. Resulting Frequency versus d. 9 10 11 12 13 14 15 AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 142 AT90PWM2/3/2B/3B 16.7.2 Modes of Operation 16.7.2.1 Normal Mode The simplest mode of operation is the normal mode. See Figure 16-6. The active time of PSCOUTn0 is given by the OT0 value. The active time of PSCOUTn1 is given by the OT1 value. Both of them are 12 bit values. Thanks to DT0 & DT1 to ajust the dead time between PSCOUTn0 and PSCOUTn1 active signals.
  • Page 143 PSCn Input A is configurable thanks to a sense control block. PSCn Input A can be the Output of the analog comparator or the PSCINn input. As the period of the cycle decreases, the instantaneous frequency of the two outputs increases. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 144 AT90PWM2/3/2B/3B Figure 16-15. PSCOUTn0 retriggered by PSCn Input A (Edge Retriggering) On-Time 0 On-Time 1 PSCOUTn0 PSCOUTn1 PSCn Input A (falling edge) PSCn Input A (rising edge) Dead-Time 0 Dead-Time 1 Note: This exemple is given in “Input Mode 8” in “2 or 4 ramp mode” See Figure 16-31. for details.
  • Page 145 This exemple is given in “Input Mode 1” in “2 or 4 ramp mode” See Figure 16-20. for details. 16.8.3.1 Burst Generation On level mode, it’s possible to use PSC to generate burst by using Input Mode 3 or Note: Mode 4 ( See Figure 16-24. and Figure 16-25. for details.) AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 146 AT90PWM2/3/2B/3B Figure 16-19. Burst Generation BURST PSCOUTn0 PSCOUTn1 PSCn Input A (high level) PSCn Input A (low level) 16.8.4 PSC Input Configuration The PSC Input Configuration is done by programming bits in configuration registers. 16.8.4.1 Filter Enable If the “Filter Enable” bit is set, a digital filter of 4 cycles is inserted before evaluation of the signal.
  • Page 147 See “PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and Dis- 1110b activate Output” on page 155. Reserved : Do not use 1111b Notice: All following examples are given with rising edge or high level active inputs. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 148 AT90PWM2/3/2B/3B 16.9 PSC Input Mode 1: Stop signal, Jump to Opposite Dead-Time and Wait Figure 16-20. PSCn behaviour versus PSCn Input A in Fault Mode 1 PSCOUTn0 PSCOUTn1 PSC Input A PSC Input B PSC Input A is taken into account during DT0 and OT0 only. It has no effect during DT1 and OT1.
  • Page 149 When PSC Input B event occurs, PSC releases PSCOUTn1, jumps and executes DT0 plus OT0 and then waits for PSC Input B inactive state. Even if PSC Input B is released during DT0 or OT0, DT0 plus OT0 sub-cycle is always com- pletely executed. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 150 AT90PWM2/3/2B/3B 16.11 PSC Input Mode 3: Stop signal, Execute Opposite while Fault active Figure 16-24. PSCn behaviour versus PSCn Input A in Mode 3 DT0 OT0 DT1 PSCOUTn0 PSCOUTn1 PSC Input A PSC Input B PSC Input A is taken into account during DT0 and OT0 only. It has no effect during DT1 and OT1.
  • Page 151 Figure 16-28. PSC behaviour versus PSCn Input A in Fault Mode 5 DT0 OT0 PSCOUTn0 PSCOUTn1 PSCn Input A PSCn Input B Used in Fault mode 5, PSCn Input A or PSCn Input B act indifferently on On-Time0/Dead-Time0 or on On-Time1/Dead-Time1. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 152 AT90PWM2/3/2B/3B 16.14 PSC Input Mode 6: Stop signal, Jump to Opposite Dead-Time and Wait. Figure 16-29. PSC behaviour versus PSCn Input A in Fault Mode 6 DT0 OT0 PSCOUTn0 PSCOUTn1 PSCn Input A PSCn Input B Used in Fault mode 6, PSCn Input A or PSCn Input B act indifferently on On-Time0/Dead-Time0 or on On-Time1/Dead-Time1.
  • Page 153 The retrigger event is taken into account only if it occurs during the corresponding On-Time. Note: In one ramp mode, the retrigger event on input A resets the whole ramp. So the PSC doesn’t jump to the opposite dead-time. 16.17 PSC Input Mode 9: Fixed Frequency Edge Retrigger PSC AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 154 AT90PWM2/3/2B/3B Figure 16-33. PSC behaviour versus PSCn Input A in Mode 9 PSCOUTn0 PSCOUTn1 PSCn Input A The output frequency is not modified by the occurence of significative edge of retriggering input. Only the output is disactivated when significative edge on retriggering input occurs.
  • Page 155 Retrigger/Fault input is actve. The PSC runs at con- stant frequency. AT90PWM2/3 : The retrigger event is taken into account only if it occurs during the correspond- ing On-Time. In the case of the retrigger event is not taken into account, the following active outputs remains active, they are not desactivated.
  • Page 156 AT90PWM2/3/2B/3B 16.18.1 Available Input Mode according to Running Mode Some Input Modes are not consistent with some Running Modes. So the table below gives the input modes which are valid according to running modes.. Table 16-7. Available Input Modes according to Running Modes...
  • Page 157 Figure 16-37. PSCOUT22 and PSCOUT23 Outptuts PSCOUT20 Waveform Generator A PSCOUT22 POS22 Output POS23 Matrix PSCOUT23 PSCOUT21 Waveform Generator B 16.20 Analog Synchronization PSC generates a signal to synchronize the sample and hold; synchronisation is mandatory for measurements. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 158 AT90PWM2/3/2B/3B This signal can be selected between all falling or rising edge of PSCn0 or PSCn1 outputs. In center aligned mode, OCRnRAH/L is not used, so it can be used to specified the synchroniza- tion of the ADC. It this case, it’s minimum value is 1.
  • Page 159 Figure 16-39. Clock selection PRESCALER PCLKSELn PPREn1/0 (1) : CK/16 for AT90PWM2/3 PSCn (2) : CK/64 for AT90PWM2/3 PCLKSELn bit in PSC n Configuration register (PCNFn) is used to select the clock source. PPREn1/0 bits in PSC n Control Register (PCTLn) are used to select the divide factor of the clock.
  • Page 160 PSC counter or Synchro Error. 16.26.216.26.2See PSCn Interrupt Mask Register page 171 and PSCn Interrupt Flag Register page 172. 16.24.2 PSC Interrupt Vectors in AT90PWM2/2B/3/3B Table 16-10. PSC Interrupt Vectors Vector Program Address Source Interrupt Definition...
  • Page 161 Send signal on trailing edge of PSCOUTn0 (match with OCRnRA or fault/retrigger on part A) Send signal on leading edge of PSCOUTn1 (match with OCRnSB) Send signal on trailing edge of PSCOUTn1 (match with OCRnRB or fault/retrigger on part B) AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 162 AT90PWM2/3/2B/3B Table 16-12. Synchronization Source Description in Centered Mode PSYNCn1 PSYNCn0 Description Send signal on match with OCRnRA (during counting down of PSC). The min value of OCRnRA must be 1. Send signal on match with OCRnRA (during counting up of PSC). The min value of OCRnRA must be 1.
  • Page 163 • Bit 6 - PALOCKn: PSC n Autolock When this bit is set, the Output Compare Registers RA, SA, SB, the Output Matrix POM2 and the PSC Output Configuration PSOCn can be written without disturbing the PSC cycles. The AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 164 AT90PWM2/3/2B/3B update of the PSC internal registers will be done at the end of the PSC cycle if the Output Com- pare Register RB has been the last written. When set, this bit prevails over LOCK (bit 5) • Bit 5 – PLOCKn: PSC n Lock When this bit is set, the Output Compare Registers RA, RB, SA, SB, the Output Matrix POM2 and the PSC Output Configuration PSOCn can be written without disturbing the PSC cycles.
  • Page 165 • Bit 0 – PRUN0 : PSC 0 Run Writing this bit to one starts the PSC 0. When set, this bit prevails over PARUN0 bit. 16.25.12 PSC 1 Control Register – PCTL1 PPRE11 PPRE10 PBFM1 PAOC1B PAOC1A PARUN1 PCCYC1 PRUN1 PCTL1 Read/Write Initial Value AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 166 AT90PWM2/3/2B/3B • Bit 7:6 – PPRE11:0 : PSC 1 Prescaler Select This two bits select the PSC input clock division factor.All generated waveform will be modified by this factor. Table 16-15. PSC 1 Prescaler Selection PPRE11 PPRE10 Description PWM2/3 Description PWM2B/3B...
  • Page 167 Writing this bit to one starts the PSC 2. When set, this bit prevails over PARUN2 bit. 16.25.14 PSC n Input A Control Register – PFRCnA PCAEnA PISELnA PELEVnA PFLTEnA PRFMnA3 PRFMnA2 PRFMnA1 PRFMnA0 PFRCnA Read/Write Initial Value AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 168 AT90PWM2/3/2B/3B 16.25.15 PSC n Input B Control Register – PFRCnB PCAEnB PISELnB PELEVnB PFLTEnB PRFMnB3 PRFMnB2 PRFMnB1 PRFMnB0 PFRCnB Read/Write Initial Value The Input Control Registers are used to configure the 2 PSC’s Retrigger/Fault block A & B. The 2 blocks are identical, so they are configured on the same way.
  • Page 169 CPU accesses these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit or 12-bit registers. Note for AT90PWM2/3 : This register is read only and a write to this register is not allowed. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 170 AT90PWM2/3/2B/3B 16.26 PSC2 Specific Register 16.26.1 PSC 2 Output Matrix – POM2 POMV2B3 POMV2B2 POMV2B1 POMV2B0 POMV2A3 POMV2A2 POMV2A1 POMV2A0 POM2 Read/Write Initial Value • Bit 7 – POMV2B3: Output Matrix Output B Ramp 3 This bit gives the state of the PSCOUT21 (and/or PSCOUT23) during ramp 3 •...
  • Page 171 Read/Write Initial Value • Bit 7 – POACnB : PSC n Output B Activity (not implemented on AT90PWM2/3) This bit is set by hardware each time the output PSCOUTn1 changes from 0 to 1 or from 1 to 0. Must be cleared by software by writing a one to its location.
  • Page 172 AT90PWM2/3/2B/3B This feature is useful to detect that a PSC output doesn’t change due to a freezen external input signal. • Bit 5 – PSEIn : PSC n Synchro Error Interrupt This bit is set by hardware when the update (or end of PSC cycle) of the PSCn configured in auto run (PARUNn = 1) does not occur at the same time than the PSCn-1 which has generated the input run signal.
  • Page 173 17. Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT90PWM2/2B/3/3B and peripheral devices or between several AVR devices. The AT90PWM2/2B/3/3B SPI includes the following features: 17.1 Features • Full-duplex, Three-wire Synchronous Data Transfer •...
  • Page 174 AT90PWM2/3/2B/3B the required clock pulses on the SCK line to interchange data. Data is always shifted from Mas- ter to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the Master In – Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling high the Slave Select, SS, line.
  • Page 175 DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB2, replace DD_MOSI with DDB2 and DDR_SPI with DDRB. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 176 AT90PWM2/3/2B/3B Assembly Code Example SPI_MasterInit: ; Set MOSI and SCK output, all others input r17,(1<<DD_MOSI)|(1<<DD_SCK) DDR_SPI,r17 ; Enable SPI, Master, set clock rate fck/16 r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0) SPCR,r17 SPI_MasterTransmit: ; Start transmission of data (r16) SPDR,r16 Wait_Transmit: ; Wait for transmission complete...
  • Page 177 When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 178 AT90PWM2/3/2B/3B means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high. The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous with the master clock generator. When the SS pin is driven high, the SPI slave will immediately reset the send and receive logic, and drop any partially received data in the Shift Register.
  • Page 179 Figure 17-4 for an example. The CPOL functionality is summarized below: Table 17-3. CPHA Functionality CPHA Leading Edge Trailing Edge Sample Setup Setup Sample • Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 180 SPI Data Register. • Bit 5..1 – Res: Reserved Bits These bits are reserved bits in the AT90PWM2/2B/3/3B and will always read as zero. • Bit 0 – SPI2X: Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI...
  • Page 181 CHANGE 0 MISO PIN MSB first (DORD = 0) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB first (DORD = 1) Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 182 AT90PWM2/3/2B/3B Figure 17-4. SPI Transfer Format with CPHA = 1 SCK (CPOL = 0) mode 1 SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN MSB first (DORD = 0) Bit 6...
  • Page 183 – Bit ordering configuration (MSB or LSB first) – Sleep mode exit under reception of EUSART frame 18.2 Overview A simplified block diagram of the USART Transmitter is shown in Figure 18-1. CPU accessible I/O Registers and I/O pins are shown in bold. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 184 AT90PWM2/3/2B/3B Figure 18-1. USART Block Diagram Clock Generator UBRR[H:L] CLKio BAUD RATE GENERATOR SYNC LOGIC CONTROL Transmitter UDR (Transmit) CONTROL PARITY GENERATOR TRANSMIT SHIFT REGISTER CONTROL Receiver CLOCK RECOVERY CONTROL DATA RECEIVE SHIFT REGISTER RECOVERY CONTROL PARITY UDR (Receive) CHECKER...
  • Page 185 Receiver’s clock and data recovery units. However, the recovery units use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the UMSEL, U2X and DDR_XCK bits. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 186 AT90PWM2/3/2B/3B Table 18-1 contains equations for calculating the baud rate (in bits per second) and for calculat- ing the UBRR value for each mode of operation using an internally generated clock source. Table 18-1. Equations for Calculating Baud Rate Register Setting...
  • Page 187 When a complete frame is transmitted, it can be directly followed by a new frame, or the communication line can be set to an idle (high) state. Figure 18-4 illustrates the possible combinations of the frame formats. Bits inside brackets are optional. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 188 AT90PWM2/3/2B/3B Figure 18-4. Frame Formats FRAME (IDLE) Sp1 [Sp2] (St / IDLE) Start bit, always low. Data bits (0 to 8). Parity bit. Can be odd or even. Stop bit, always high. IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be high.
  • Page 189 Register. When the Transmitter is enabled, the normal port operation of the TxDn pin is overrid- den by the USART and given the function as the Transmitter’s serial output. The baud rate, mode of operation and frame format must be set up once before doing any transmissions. If syn- AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 190 AT90PWM2/3/2B/3B chronous operation is used, the clock on the XCK pin will be overridden and used as transmission clock. 18.6.1 Sending Frames with 5 to 8 Data Bit A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The CPU can load the transmit buffer by writing to the UDR I/O location.
  • Page 191 When the Data Register Empty Interrupt Enable (UDRIE) bit in UCSRB is written to one, the USART Data Register Empty Interrupt will be executed as long as UDRE is set (provided that global interrupts are enabled). UDRE is cleared by writing UDR. When interrupt-driven data AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 192 AT90PWM2/3/2B/3B transmission is used, the Data Register Empty interrupt routine must either write new data to UDR in order to clear UDRE or disable the Data Register Empty interrupt, otherwise a new inter- rupt will occur once the interrupt routine terminates.
  • Page 193 FIFO and consequently the TXB8, FE, DOR and UPE bits, which all are stored in the FIFO, will change. The following code example shows a simple USART receive function that handles both nine bit characters and the status bits. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 194 AT90PWM2/3/2B/3B Assembly Code Example USART_Receive: ; Wait for data to be received sbis UCSRA, RXC0 rjmp USART_Receive ; Get status and 9th bit, then data from buffer r18, UCSRA lds r17, UCSRB lds r16, UDR ; If error, return -1 andi r18,(1<<FE0)|(1<<DOR0)|(1<<UPE0)
  • Page 195 CH1 and CH2, CH3 is lost. When a Data OverRun condition is detected, the OverRun error is memorized. When the two characters CH1 and CH2 are read from the receive buffer, the DOR bit is set (and not before) and RxC remains set to warn the application about the overrun error. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 196 AT90PWM2/3/2B/3B Figure 18-5. Data OverRun example RxC=1 RxC=1 RxC=1 Software Access UDR=CH2 UDR=XX UDR=CH1 to Receive buffer DOR=0 DOR=1 DOR=0 The Parity Error (UPE) Flag indicates that the next frame in the receive buffer had a Parity Error when received. If Parity Check is not enabled the UPE bit will always be read zero. For compati- bility with future devices, always set this bit to zero when writing to UCSRA.
  • Page 197 The clock recovery logic then uses samples 8, 9, and 10 for Normal mode, and sam- ples 4, 5, and 6 for Double Speed mode (indicated with sample numbers inside boxes on the figure), to decide if a valid start bit is received. If two or more of these three samples have logical AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 198 AT90PWM2/3/2B/3B high levels (the majority wins), the start bit is rejected as a noise spike and the Receiver starts looking for the next high to low-transition. If however, a valid start bit is detected, the clock recov- ery logic is synchronized and the data recovery can begin. The synchronization process is repeated for each start bit.
  • Page 199 Max Total Error (%) Receiver Error (%) slow fast 93.20 106.67 +6.67/-6.8 ± 3.0 94.12 105.79 +5.79/-5.88 ± 2.5 94.81 105.11 +5.11/-5.19 ± 2.0 95.36 104.58 +4.58/-4.54 ± 2.0 95.81 104.14 +4.14/-4.19 ± 1.5 96.17 103.78 +3.78/-3.83 ± 1.5 AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 200 AT90PWM2/3/2B/3B Table 18-3. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (U2X = 1) Recommended Max # (Data+Parity Bit) Max Total Error (%) Receiver Error (%) slow fast 94.12 105.66 +5.66/-5.88 ± 2.5 94.92 104.92 +4.92/-5.08 ± 2.0 95.52...
  • Page 201 Transmit Shift Register when the Shift Register is empty. Then the data will be seri- ally transmitted on the TxDn pin. The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the receive buffer is accessed. This register is available in both USART and EUSART modes. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 202 AT90PWM2/3/2B/3B 18.10.2 USART Control and Status Register A – UCSRA UDRE MPCM UCSRA Read/Write Initial Value • Bit 7 – RXC: USART Receive Complete This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e., does not contain any unread data).
  • Page 203 Transmit Shift Register and Transmit Buffer Register do not contain data to be trans- mitted. When disabled, the Transmitter will no longer override the TxDn port. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 204 AT90PWM2/3/2B/3B This bit is available for both USART and EUSART mode. • Bit 2 – UCSZ2: Character Size The UCSZ2 bits combined with the UCSZ1:0 bit in UCSRC sets the number of data bits (Char- acter SiZe) in a frame the Receiver and Transmitter use.
  • Page 205 SiZe) in a frame the Receiver and Transmitter use. Table 18-7. UCSZ Bits Settings UCSZ2 UCSZ1 UCSZ0 Character Size 5-bit 6-bit 7-bit 8-bit Reserved Reserved Reserved 9-bit When the EUSART mode is set, these bits have no effect. • Bit 0 – UCPOL: Clock Polarity AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 206 AT90PWM2/3/2B/3B This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK). Table 18-8.
  • Page 207 0.2% 0.0% 0.0% 57.6k 0.0% 0.0% 8.5% -3.5% 0.0% 0.0% 76.8k 0.0% 0.0% 8.5% -7.0% 0.0% 0.0% 115.2k 0.0% 0.0% 8.5% 8.5% 0.0% 0.0% 230.4k 0.0% 0.0% 8.5% 8.5% 0.0% 0.0% 250k -7.8% -7.8% 0.0% 0.0% -7.8% -7.8% AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 208 AT90PWM2/3/2B/3B Table 18-10. Examples of UBRR Settings for Commonly Frequencies (Continued) = 3.6864 MHz = 4.0000 MHz = 7.3728 MHz Baud U2X = 0 U2X = 1 U2X = 0 U2X = 1 U2X = 0 U2X = 1 Rate...
  • Page 209 0.0% 0.0% – – -33.3% – – -7.8% – – 0.0% – – – – – – – – Max. 0.5 Mbps 1 Mbps 625 kbps 1.25 Mbps 691.2 kbps 1.3824 Mbps UBRR = 0, Error = 0.0% AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 210 AT90PWM2/3/2B/3B Table 18-12. Examples of UBRR Settings for Commonly Frequencies (Continued) = 12.0000 MHz = 14.7456 MHz = 16.0000 MHz Baud U2X = 0 U2X = 1 U2X = 0 U2X = 1 U2X = 0 U2X = 1 Rate...
  • Page 211 Manchester encoded • data transmition MSB or LSB first (bit ordering) • no, even or odd parity bit • 1 or 2 stop bits: – Stop bits insertion for transmition – Stop bits value read access in reception AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 212 AT90PWM2/3/2B/3B The fr ame format used by the EUSART can be configur ed thr ough the following USART/EUSART registers: • UTxS3:0 and URxS3:0 (EUCSRA of EUSART register) select the number of data bits per frame • UPM1:0 bits enable and set the type of parity bit (when configured in Manchester mode, the parity should be fixed to none).
  • Page 213 In Manchester mode, the clock used for sampling the EUSART input signal is programmed by the baudrate generator. The edge detector of the Manchester decoder is based upon a 16 bits up/down counter which maximum value can be configured through the MUBRRH and MUBRRL registers. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 214 AT90PWM2/3/2B/3B The maximum counter value is given by the following formula: MUBRR[H:L]=F / (baud rate frequency) CLKIO MBURR[H:L] is used to calibrate the detect window of the start bit and to detect time overflow of the other bits. 19.3.4 Double Speed Operation (U2X) Double Speed Operation is controlled by U2X bit in UCSRA.
  • Page 215 When configured in Manchester mode, the framing error (FE) of the USCRA register is not used, the EUSART generates a dedicated Frame Error Manchester (FEM) when a data data bit is not detected during the detection window (See Figure 19-5). AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 216 AT90PWM2/3/2B/3B Figure 19-5. Manchester Frame error detection Internal Manchester Clock Resynchronize Internal Manchester Clock Start Bit Bit 1 Bit 2 Start Bit Bit 1 Bit 2 Manchester Data front shift back shift Framing Error Counter Start Bit Start Bit Overflow...
  • Page 217 For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 218 AT90PWM2/3/2B/3B 19.4.4 Sending 17 Data Bit Frames In this configuration the seventeenth bit shoud be loaded in the RXB8 bit register, the rest of the most significant bits (9, 10, 11, 12, 13, 14, 15 and 16) should be loaded in the EUDR register, before the low byte of the character is written to UDR.
  • Page 219 All can be accessed by reading UCSRA. (See “Receiver Error Flags” in USART section). When the EUSART is configured in Machester mode, the EUSART has two errors flags: Data OverRun (DOR), and Manchester framing error (FEM bit of EUCSRC). AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 220 AT90PWM2/3/2B/3B All the receiver error flags are valid only when the RxC bit is set and until the UDR register is read. 19.5.5.1 Parity Checker The parity checker of the EUSART is available only when data bits are level encoded and behaves as is USART mode (See Parity checker of the USART).
  • Page 221 For 17 bit character the seventeenth bit is locate in RxB8 or TXB8 register. In transmitter mode, the data should be written MSB first. The data transmission starts when the UDR register is written. Figure 19-8. 17 bits communication data access Data 16:0 RxB8 (receive) EUDR or TxB8 (transmit) AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 222 AT90PWM2/3/2B/3B 19.6.3 EUSART Control and Status Register A – EUCSRA UTxS3 UTxS2 UTxS1 UTxS0 URxS3 URxS2 URxS1 URxS0 EUCSRA Read/Write Initial Value • Bit 7:4 – EUSART Transmit Character Size The UTxS3:0 bits sets the number of data bits (Character Size) in a frame the Transmitter use.
  • Page 223 USBS bit of in the of the USART. • Bit 2–Reserved Bit This bit is reserved for future use. For compatibilty with future devices, this bit must be written to zero when EUSCRB is written. • Bit 1 – Manchester mode AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 224 AT90PWM2/3/2B/3B When set the EUSART operates in manchester encoder/decoder mode (Manchester encoded frames). When cleared the EUSART detected and transmit level encoded frames. Table 19-4. USART/EUSART modes selection summary UMSEL EMCH EUSART Mode Asynchronous up to 9 bits level encoded (standard...
  • Page 225 CLKIO Table 19-5. Examples of MUBRR Settings for Commonly Frequencies Baud Rate 1.8432 2.0000 4.0000 8.0000 11.0592 16.000 (bps) 1200 1536 1667 3333 6667 9216 13333 2400 1667 3333 4608 6667 4800 1667 2304 3333 9600 1152 1667 AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 226 The Analog Comparator compares the input values on the positive pin ACMPx and negative pin ACMPM. 20.1 Overview The AT90PWM2/2B/3/3B features three fast analog comparators. Each comparator has a dedicated input on the positive input, and the negative input can be con- figured as: •...
  • Page 227 • Bit 6– AC0IE: Analog Comparator 0 Interrupt Enable bit Set this bit to enable the analog comparator 0 interrupt. Clear this bit to disable the analog comparator 0 interrupt. • Bit 5, 4– AC0IS1, AC0IS0: Analog Comparator 0 Interrupt Select bit AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 228 AT90PWM2/3/2B/3B These 2 bits determine the sensitivity of the interrupt trigger. The different setting are shown in Table 20-1. Table 20-1. Interrupt sensitivity selection AC0IS1 AC0IS0 Description Comparator Interrupt on output toggle Reserved Comparator interrupt on output falling edge Comparator interrupt on output rising edge •...
  • Page 229 AC2EN AC2IE AC2IS1 AC2IS0 AC2M2 AC2M1 AC2M0 AC2CON Read/Write Initial Value • Bit 7– AC2EN: Analog Comparator 2 Enable Bit Set this bit to enable the analog comparator 2. Clear this bit to disable the analog comparator 2. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 230 AT90PWM2/3/2B/3B • Bit 6– AC2IE: Analog Comparator 2 Interrupt Enable bit Set this bit to enable the analog comparator 2 interrupt. Clear this bit to disable the analog comparator 2 interrupt. • Bit 5, 4– AC2IS1, AC2IS0: Analog Comparator 2 Interrupt Select bit These 2 bits determine the sensitivity of the interrupt trigger.
  • Page 231 • Bit 5, 2: ACMP0D and ACMP1 Digital Input Disable When this bit is written logic one, the digital input buffer on the corresponding analog pin is dis- abled. The corresponding PIN Register bit will always read as zero when this bit is set. When an AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 232 AT90PWM2/3/2B/3B analog signal is applied to one of these pins and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. 4317I–AVR–01/08...
  • Page 233 Interrupt on ADC Conversion Complete • Sleep Mode Noise Canceler The AT90PWM2/2B/3/3B features a 10-bit successive approximation ADC. The ADC is con- nected to an 15-channel Analog Multiplexer which allows eleven single-ended input. The single- ended voltage inputs refer to 0V (GND).
  • Page 234 AMP0+ CONTROL ADC CONVERSION COMPLETE IRQ Bandgap PRESCALER AMP0CSR AMP1CSR REFS1 REFS0 ADLAR MUX3 MUX2 MUX1 MUX0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 ADMUX ADCSRA Edge ADATE Detector Only on AT90PWM2/3 ADASCR ADTS3 ADTS2 ADTS1 ADTS0 ADCSRB 4317I–AVR–01/08...
  • Page 235 Global Interrupt Enable bit in SREG is cleared. A conversion can thus be triggered without causing an interrupt. However, the interrupt flag must be cleared in order to trigger a new conversion at the next interrupt event. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 236 AT90PWM2/3/2B/3B Figure 21-2. ADC Auto Trigger Logic ADTS[2:0] PRESCALER START ADIF ADATE SOURCE 1 CONVERSION LOGIC EDGE DETECTOR SOURCE n ADSC Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, con- stantly sampling and updating the ADC Data Register.
  • Page 237 Figure 21-5. ADC Timing Diagram, Single Conversion One Conversion Next Conversion Cycle Number ADC Clock ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample & Hold Conversion MUX and REFS MUX and REFS Complete Update Update AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 238 AT90PWM2/3/2B/3B Figure 21-6. ADC Timing Diagram, Auto Triggered Conversion One Conversion Next Conversion Cycle Number ADC Clock Trigger Source ADATE ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample & Prescaler Conversion Prescaler Hold Reset Complete Reset...
  • Page 239 AREF pin, the user may switch between AV and 2.56V as reference selection. The first ADC conversion result after switching reference voltage source may be inaccurate, and the user is advised to discard this result. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 240 AT90PWM2/3/2B/3B If differential channels are used, the selected reference should not be closer to AV than indi- cated in Table 26-3 on page 306. 21.6 ADC Noise Canceler The ADC features a noise canceler that enables conversion during sleep mode to reduce noise induced from the CPU core and other I/O peripherals.
  • Page 241 Figure 21-9. ADC Power Connections PB7(ADC4) PB6 (ADC7) PB5 (ADC6) PC7 (D2A) PB4 (AMP0+) PB3 (AMP0-) PC6 (ADC10/ACMP1) AREF AGND AVCC PC5 (ADC9/AMP1+) 100nF PC4 (ADC8/AMP1-) PB2 (ADC5) PD7 (ACMP0) (ADC0) PE2 PD6 (ADC3/ACMPM) (ADC1) PD4 PD5 (ADC2/ACMP2) Analog Ground Plane AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 242 AT90PWM2/3/2B/3B 21.6.3 Offset Compensation Schemes The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential mea- surements as much as possible. The remaining offset in the analog path can be measured directly by shortening both differential inputs using the AMPxIS bit with both inputs unconnected.
  • Page 243 Figure 21-12. Integral Non-linearity (INL) Output Code Ideal ADC Actual ADC Input Voltage • Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 244 AT90PWM2/3/2B/3B Figure 21-13. Differential Non-linearity (DNL) Output Code 0x3FF 1 LSB 0x000 Input Voltage • Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB.
  • Page 245 ADMUX = 0xED (ADC3 - ADC2, 10x gain, 2.56V reference, left adjusted result) – Voltage on ADC3 is 300 mV, voltage on ADC2 is 500 mV. – ADCR = 512 * 10 * (300 - 500) / 2560 = -400 = 0x270 AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 246 21.8 ADC Register Description The ADC of the AT90PWM2/2B/3/3B is controlled through 3 different registers. The ADCSRA and The ADCSRB registers which are the ADC Control and Status registers, and the ADMUX which allows to select the Vref source and the channel to be converted.
  • Page 247 The first conversion performs the initialization of the ADC. • Bit 5 – ADATE: ADC Auto trigger Enable Bit Set this bit to enable the auto triggering mode of the ADC. Clear it to return in single conversion mode. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 248 ADC clock frequency higher than 200KHz. • Bit 4– ADASCR: Analog to Digital Conversion on Amplified Channel Start Conversion Request Bit (AT90PWM2/3 only - NA on AT90PWM2B/3B) Set this to request a conversion on an amplified channel. Cleared by hardware as soon as the Analog to Digital Conversion is started.
  • Page 249 For trigger on any PSC event, if the PSC uses the PLL clock, the core must use PLL/4 clock source. Table 21-7. ADC Auto Trigger Source Selection for amplified conversions ADTS3 ADTS2 ADTS1 ADTS0 Description Free Running Mode Reserved Reserved Reserved Reserved Reserved Reserved Reserved PSC0ASY Event PSC1ASY Event AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 250 AT90PWM2/3/2B/3B Table 21-7. ADC Auto Trigger Source Selection for amplified conversions ADTS3 ADTS2 ADTS1 ADTS0 Description PSC2ASY Event Reserved Reserved Reserved Reserved Reserved For trigger on any PSC event, if the PSC uses the PLL clock, the core must use PLL/4 clock source.
  • Page 251 - By setting the ADASCR (Analog to Digital Conversion on Amplified Channel Start Conversion Request) bit in the ADCSRB register on AT90PWM2/3. Then, the ADSC bit of the ADCSRA Register is automatically set on the next amplifier clock event, and a conversion is started.
  • Page 252 In order to have a better understanding of the functioning of the amplifier synchronization, a tim- ing diagram example is shown Figure 21-15 for AT90PWM2/3. Figure 21-15. Amplifier synchronization timing diagram for AT90PWM2/3. Delta V 4th stable sample Signal to be...
  • Page 253 CK ADC Valid sample ADSC Activity Conv Conv Sampling Sampling ADC Result ADC Result Ready Ready Figure 21-17. Amplifier synchronization timing diagram for AT90PWM2B/3B ADSC is set when the amplifier output is changing due to the amplifier clock switch. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 254 AT90PWM2/3/2B/3B Si g nal to be measu red PS Cn_ASY Block AMPLI_clk (Sync Clock) CK ADC Valid sample ADSC Sampling Aborted Activity Conv Conv Sampling Sampling ADC Result ADC Result Ready Ready 4317I–AVR–01/08...
  • Page 255 The conversion result is stored on ADCH and ADCL register which contain respectively the most significant bits and the less significant bits. 21.10.1 Amplifier 0 Control and Status register – AMP0CSR AMP0EN AMP0IS AMP0G1 AMP0G0 AMP0TS1 AMP0TS0 AMP0CSR Read/Write Initial Value AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 256 AT90PWM2/3/2B/3B • Bit 7 – AMP0EN: Amplifier 0 Enable Bit Set this bit to enable the Amplifier 0. Clear this bit to disable the Amplifier 0. Clearing this bit while a conversion is running will take effect at the end of the conversion.
  • Page 257 1. This trigger source is necessary to start the conversion on the amplified channel. Table 21-11. AMP1 Auto Trigger source selection AMP1TS1 AMP1TS0 Description Auto synchronization on ADC Clock/8 Trig on PSC0ASY Trig on PSC1ASY Trig on PSC2ASY AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 258 • Output impedance around 100 Ohm. The AT90PWM2/2B/3/3B features a 10-bit Digital to Analog Converter. This DAC can be used for the analog comparators and/or can be output on the D2A pin of the microcontroller via a ded- icated driver.
  • Page 259 If another positive edge occurs on the trigger signal during conversion, the edge will be ignored. Note that an interrupt flag will be set even if the specific interrupt is disabled or the Global Inter- AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 260 AT90PWM2/3/2B/3B rupt Enable bit in SREG is cleared. A conversion can thus be triggered without causing an interrupt. However, the interrupt flag must be cleared in order to trigger a new conversion at the next interrupt event. 22.3.1 DAC Voltage Reference The reference voltage for the ADC (V ) indicates the conversion range for the DAC.
  • Page 261 22.4.2.1 DALA = 0 DAC9 DAC8 DACH DAC7 DAC6 DAC5 DAC4 DAC3 DAC2 DAC1 DAC0 DACL Read/Write Initial Value 22.4.2.2 DALA = 1 DAC9 DAC8 DAC7 DAC6 DAC5 DAC4 DAC3 DAC2 DACH DAC1 DAC0 DACL Read/Write Initial Value AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 262 AT90PWM2/3/2B/3B To work with the 10-bit DAC, two registers have to be updated. In order to avoid intermediate value, the DAC input values which are really converted into analog signal are buffering into unreachable registers. In normal mode, the update of the shadow register is done when the reg- ister DACH is written.
  • Page 263 The system clock is not affected by debugWIRE and will always be the clock source selected by the CKSEL Fuses. When designing a system where debugWIRE will be used, the following observations must be made for correct operation: AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 264 24. Boot Loader Support – Read-While-Write Self-Programming In AT90PWM2/2B/3/3B, the Boot Loader Support provides a real Read-While-Write Self-Pro- gramming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resi- dent Boot Loader program.
  • Page 265 When erasing or writing a page located inside the RWW section, the NRWW section can be read during the operation. • When erasing or writing a page located inside the NRWW section, the CPU is halted during the entire operation. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 266 AT90PWM2/3/2B/3B Note that the user software can never read any code that is located inside the RWW section dur- ing a Boot Loader software operation. The syntax “Read-While-Write section” refers to which section that is being programmed (erased or written), not which section that actually is being read during a Boot Loader software update.
  • Page 267 Figure 24-1. Read-While-Write vs. No Read-While-Write Read-While-Write (RWW) Section Z-pointer Addresses NRWW Section Z-pointer Addresses RWW No Read-While-Write (NRWW) Section Section CPU is Halted During the Operation Code Located in NRWW Section Can be Read During the Operation AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 268 AT90PWM2/3/2B/3B Figure 24-2. Memory Sections Program Memory Program Memory BOOTSZ = '11' BOOTSZ = '10' 0x0000 0x0000 Application Flash Section Application Flash Section End RWW End RWW Start NRWW Start NRWW Application Flash Section Application Flash Section End Application End Application...
  • Page 269 Table 24-4. Boot Reset Fuse BOOTRST Reset Address Reset Vector = Application Reset (address 0x0000) Reset Vector = Boot Loader Reset (see Table 24-6 on page 278) Note: 1. “1” means unprogrammed, “0” means programmed AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 270 • Bit 5 – Res: Reserved Bit This bit is a reserved bit in the AT90PWM2/2B/3/3B and always read as zero. • Bit 4 – RWWSRE: Read-While-Write Section Read Enable When programming (Page Erase or Page Write) to the RWW section, the RWW section is blocked for reading (the RWWSB will be set by hardware).
  • Page 271 The content of the Z-pointer is ignored and will have no effect on the operation. The LPM instruction does also use the Z-pointer to store the address. Since this instruction addresses the Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 272 AT90PWM2/3/2B/3B Figure 24-3. Addressing the Flash During SPM ZPCMSB ZPAGEMSB Z - REGISTER PCMSB PAGEMSB PROGRAM PCPAGE PCWORD COUNTER PAGE ADDRESS WORD ADDRESS WITHIN THE FLASH WITHIN A PAGE PROGRAM MEMORY PAGE PCWORD[PAGEMSB:0]: PAGE INSTRUCTION WORD PAGEEND Note: 1. The different variables used in...
  • Page 273 XXXXXXX, or the interrupts must be disabled. Before addressing the RWW sec- tion after the programming is completed, the user software must clear the RWWSB by writing the RWWSRE. See “Simple Assembly Code Example for a Boot Loader” on page 276 for an example. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 274 AT90PWM2/3/2B/3B 24.7.7 Setting the Boot Loader Lock Bits by SPM To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The only accessible Lock bits are the Boot Lock bits that may prevent the Application and Boot Loader section from any soft- ware update by the MCU.
  • Page 275 ;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24), ; loophi (r25), spmcrval (r20) ; storing and restoring of registers is not included in the routine ; register usage can be optimized at the expense of code size AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 276 AT90PWM2/3/2B/3B ;-It is assumed that either the interrupt table is moved to the Boot ; loader section or that the interrupts are disabled. .equ PAGESIZEB = PAGESIZE*2 ;PAGESIZEB is page size in BYTES, not words .org SMALLBOOTSTART Write_page: ; Page Erase spmcrval, (1<<PGERS) | (1<<SPMEN)
  • Page 277 0xC00 - 0xBFF 0xC00 words 0xBFF 0xFFF Note: The different BOOTSZ Fuse configurations are shown in Figure 24-2. Table 24-7. Read-While-Write Limit Section Pages Address Read-While-Write section (RWW) 0x000 - 0xBFF No Read-While-Write section (NRWW) 0xC00 - 0xFFF AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 278 25. Memory Programming 25.1 Program And Data Memory Lock Bits The AT90PWM2/2B/3/3B provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 25-2. The Lock bits can only be erased to “1”...
  • Page 279 Application section, interrupts are disabled while executing from the Boot Loader section. Notes: 1. Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2. 2. “1” means unprogrammed, “0” means programmed AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 280 AT90PWM2/3/2B/3B 25.2 Fuse Bits The AT90PWM2/2B/3/3B has three Fuse bytes. Table 25-4 Table 25-6 describe briefly the functionality of all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed.
  • Page 281 Programming mode. This does not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in Normal mode. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 282 25.5 Calibration Byte The AT90PWM2/2B/3/3B has a byte calibration value for the internal RC Oscillator. This byte resides in the high byte of address 0x000 in the signature address space. During reset, this byte is automatically written into the OSCCAL Register to ensure correct frequency of the calibrated RC Oscillator.
  • Page 283 Byte Select 2 (“0” selects Low byte, “1” selects 2’nd High byte) Bi-directional Data bus (Output when OE is DATA PB[7:0] low) Table 25-8. Pin Values Used to Enter Programming Mode Symbol Value PAGEL Prog_enable[3] Prog_enable[2] Prog_enable[1] Prog_enable[0] AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 284 AT90PWM2/3/2B/3B Table 25-9. XA1 and XA0 Coding Action when XTAL1 is Pulsed Load Flash or EEPROM Address (High or low address byte determined by BS1). Load Data (High or Low data byte for Flash determined by BS1). Load Command No Action, Idle Table 25-10.
  • Page 285 2. Set BS1 to “0”. 3. Set DATA to “1000 0000”. This is the command for Chip Erase. 4. Give XTAL1 a positive pulse. This loads the command. 5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 286 AT90PWM2/3/2B/3B 6. Wait until RDY/BSY goes high before loading a new command. 25.8.4 Programming the Flash The Flash is organized in pages, see Table 25-11 on page 285. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be pro- grammed simultaneously.
  • Page 287 Figure 25-3. Programming the Flash Waveforms 0x10 ADDR. LOW DATA LOW DATA HIGH ADDR. LOW DATA LOW DATA HIGH ADDR. HIGH DATA XTAL1 RDY/BSY RESET +12V PAGEL Note: 1. “XX” is don’t care. The letters refer to the programming description above. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 288 AT90PWM2/3/2B/3B 25.8.5 Programming the EEPROM The EEPROM is organized in pages, see Table 25-12 on page 285. When programming the EEPROM, the program data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM data memory is as follows (refer to “Programming the Flash”...
  • Page 289 3. 3. Set BS1 to “0” and BS2 to “1”. This selects extended data byte. 4. 4. Give WR a negative pulse and wait for RDY/BSY to go high. 5. 5. Set BS2 to “0”. This selects low data byte. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 290 AT90PWM2/3/2B/3B Figure 25-5. Programming the FUSES Waveforms Write Fuse Low byte Write Fuse high byte Write Extended Fuse byte 0x40 DATA 0x40 DATA 0x40 DATA DATA XTAL1 RDY/BSY RESET +12V PAGEL 25.8.11 Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to “Programming the Flash”...
  • Page 291 4. Set OE to “1”. 25.8.15 Parallel Programming Characteristics Figure 25-7. Parallel Programming Timing, Including some General Timing Requirements XLWL XHXL XTAL1 DVXH XLDX Data & Contol (DATA, XA0/1, BS1, BS2) BVPH PLBX BVWL WLBX PAGEL PHPL WLWH PLWL WLRL RDY/BSY WLRH AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 292 AT90PWM2/3/2B/3B Figure 25-8. Parallel Programming Timing, Loading Sequence with Timing Requirements LOAD ADDRESS LOAD DATA LOAD DATA LOAD DATA LOAD ADDRESS (LOW BYTE) (LOW BYTE) (HIGH BYTE) (LOW BYTE) XLPH XLXH PLXH XTAL1 PAGEL DATA ADDR0 (Low Byte) DATA (Low Byte)
  • Page 293 After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. NOTE, in Table 25-13 on page 285, the pin mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal SPI interface. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 294 >= 12 MHz 25.9.1 Serial Programming Algorithm When writing serial data to the AT90PWM2/2B/3/3B, data is clocked on the rising edge of SCK. When reading data from the AT90PWM2/2B/3/3B, data is clocked on the falling edge of SCK. Figure 25-11 for timing details.
  • Page 295 See WD_EEPROM Table 25-15 for t value. WD_EEPROM Table 25-15. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol Minimum Wait Delay 4.5 ms WD_FLASH 3.6 ms WD_EEPROM 9.0 ms WD_ERASE AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 296 AT90PWM2/3/2B/3B Figure 25-11. Serial Programming Waveforms SERIAL DATA INPUT (MOSI) SERIAL DATA OUTPUT (MISO) SERIAL CLOCK INPUT (SCK) SAMPLE Table 25-16. Serial Programming Instruction Set Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte4 Operation Enable Serial Programming after...
  • Page 297 = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care 25.9.4 SPI Serial Programming Characteristics For characteristics of the SPI module see “SPI Serial Programming Characteristics” on page 298. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 298 AT90PWM2/3/2B/3B 26. Electrical Characteristics 26.1 Absolute Maximum Ratings* *NOTICE: Stresses beyond those listed under “Absolute Operating Temperature........-40°C to +105°C Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and Storage Temperature ........-65°C to +150°C...
  • Page 299 = -0.4 mA, V = 3V Input Leakage = 5.5V, pin low µA Current I/O Pin (absolute value) Input Leakage = 5.5V, pin high µA Current I/O Pin (absolute value) Reset Pull-up Resistor kΩ I/O Pin Pull-up Resistor kΩ AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 300 AT90PWM2/3/2B/3B = -40°C to +105°C, V = 2.7V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Condition Min. Typ. Max. Units Active 8 MHz, V = 3V, RC osc, PRR = 0xFF Active 16 MHz, V = 5V, Ext Clock, PRR = 0xFF...
  • Page 301 Max. Min. Max. Min. Max. Units Oscillator CLCL Frequency Clock Period CLCL High Time CHCX Low Time CLCX μs Rise Time CLCH μs Fall Time CHCL Change in period Δ from one clock CLCL cycle to the next AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 302 Figure 26-2 , the Maximum Frequency equals 8Mhz when V is contained between 2.7V and 4.5V and equals 16Mhz when V contained between 4.5V and 5.5V. Figure 26-2. Maximum Frequency vs. V , AT90PWM2/2B/3/3B 16Mhz 8Mhz Safe Operating Area 2.7V 4.5V 5.5V...
  • Page 303 In SPI Programming mode the minimum SCK high/low period is: - 2 t for f < 12 MHz CLCL - 3 t for f >12 MHz CLCL Figure 26-3. SPI Interface Timing Requirements (Master Mode) (CPOL = 0) (CPOL = 1) MISO (Data Input) MOSI (Data Output) AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 304 AT90PWM2/3/2B/3B Figure 26-4. SPI Interface Timing Requirements (Slave Mode) (CPOL = 0) (CPOL = 1) MOSI (Data Input) MISO (Data Output) 4317I–AVR–01/08...
  • Page 305 Single Ended Conversion = 4.5V, V = 4V ADC clock = 500 kHz Differential Non-linearity Differential Conversion = 4.5V, V = 4V ADC clock = 1MHz Differential Conversion = 4.5V, V = 4V ADC clock = 500 kHz AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 306 AT90PWM2/3/2B/3B Table 26-5. ADC Characteristics - T = -40°C to +105°C, V = 2.7V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Condition Units Single Ended Conversion = 4.5V, V = 4V ADC clock = 1MHz Single Ended Conversion = 4.5V, V...
  • Page 307 PAGEL DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) Note: 1. The timing requirements shown in Figure 26-5 (i.e., t , and t ) also apply to load- DVXH XHXL XLDX ing operation. AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 308 AT90PWM2/3/2B/3B Figure 26-7. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements LOAD ADDRESS READ DATA READ DATA LOAD ADDRESS (LOW BYTE) (LOW BYTE) (HIGH BYTE) (LOW BYTE) XLOL XTAL1 BVDV OLDV OHDZ ADDR1 (Low Byte) DATA...
  • Page 309 2. t is valid for the Chip Erase command. WLRH_CE 27. AT90PWM2/2B/3/3B Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled.
  • Page 310 AT90PWM2/3/2B/3B 27.1 Active Supply Current Figure 27-1. Active Supply Current vs. Frequency (0.1 - 1.0 MHz) ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 3.0 V 2.7 V Frequency (MHz) Figure 27-2. Active Supply Current vs. Frequency (1 - 24 MHz) ACTIVE SUPPLY CURRENT vs.
  • Page 311 105 °C 85 °C 25 °C -40 °C Figure 27-4. Active Supply Current vs. V (Internal PLL Oscillator, 16 MHz) ACTIVE SUPPLY CURRENT vs. V INTERNAL PLL OSCILLATOR, 16 MHz 105 °C 85 °C 25 °C -40 °C AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 312 AT90PWM2/3/2B/3B 27.2 Idle Supply Current Figure 27-5. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz) IDLE SUPPLY CURRENT vs. LOW FREQUENCY 0,45 5.5 V 0,35 5.0 V 4.5 V 0,25 4.0 V 3.3 V 3.0 V 0,15 2.7 V...
  • Page 313 27.2.1 Using the Power Reduction Register The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 314 AT90PWM2/3/2B/3B are controlled by the Power Reduction Register. See “Power Reduction Register” on page 43 details. Table 27-1. Additional Current Consumption for the different I/O modules (absolute values) PRR bit Typical numbers = 3V, F = 8MHz = 5V, F = 16MHz...
  • Page 315 7.0mA 0.085 0.043 0.053 0.156 0.105 12.2mA total 27.3 Power-Down Supply Current Figure 27-9. Power-Down Supply Current vs. V (Watchdog Timer Disabled) POWER-DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER DISABLED 105 °C 85 °C -40 °C 25 °C AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 316 AT90PWM2/3/2B/3B Figure 27-10. Power-Down Supply Current vs. V (Watchdog Timer Enabled) POWER-DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ENABLED 105 °C 85 °C -40 °C 25 °C 27.4 Pin Pull-up Figure 27-11. I/O Pin Pull-Up Resistor Current vs. Input Voltage (V = 5V) I/O PIN (including PE1 &...
  • Page 317 85 °C 105 °C Figure 27-13. Reset Pull-Up Resistor Current vs. Reset Pin Voltage (V = 5V) PE0 and RESET PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 5.0 V 25 °C -40 °C 85 °C 105 °C AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 318 AT90PWM2/3/2B/3B Figure 27-14. Reset Pull-Up Resistor Current vs. Reset Pin Voltage (V = 2.7V) PE0 and RESET PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 2.7 V 25 °C -40 °C 85 °C 105 °C 27.5 Pin Driver Strength Figure 27-15. I/O Pin Source Current vs. Output Voltage (V = 5V) I/O PIN (including PE1 &...
  • Page 319 25 °C -40 °C Figure 27-17. I/O Pin Sink Current vs. Output Voltage (V = 5V) I/O PIN (including PE1 & PE2) SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 5.0 V 85 °C -40 °C 25 °C 105 °C AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 320 AT90PWM2/3/2B/3B Figure 27-18. I/O Pin Sink Current vs. Output Voltage (V = 2.7V) I/O PIN (including PE1 & PE2) SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7 V -40 °C 25 °C 85 °C 105 °C 27.6 Pin Thresholds and Hysteresis Figure 27-19.
  • Page 321 I/O PIN (including PE1 & PE2) INPUT THRESHOLD VOLTAGE vs. V VIL, IO PIN READ AS '0' -40 °C 25 °C 85 °C 105 °C Figure 27-21. I/O Pin Input HysteresisVoltage vs. V I/O PIN INPUT HYSTERESIS vs. V -40 C 25 C 85 C AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 322 AT90PWM2/3/2B/3B Figure 27-22. Reset Input Threshold Voltage vs. V (VIH, Reset Pin Read As '1') RESET INPUT THRESHOLD VOLTAGE vs. V VIH, RESET PIN READ AS '1' -40 °C 25 °C 85 °C 105 °C Figure 27-23. Reset Input Threshold Voltage vs. V (VIL, Reset Pin Read As '0') RESET INPUT THRESHOLD VOLTAGE vs.
  • Page 323 25 °C 85 °C 105 °C Figure 27-25. XTAL1 Input Threshold Voltage vs. V (XTAL1 Pin Read As '1') XTAL1 INPUT THRESHOLD VOLTAGE vs. V XTAL1 PIN READ AS "1" -40 °C 25 °C 85 °C 105 °C AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 324 AT90PWM2/3/2B/3B Figure 27-26. XTAL1 Input Threshold Voltage vs. V (XTAL1 Pin Read As '0') XTAL1 INPUT THRESHOLD VOLTAGE vs. V XTAL1 PIN READ AS "0" -40 °C 25 °C 85 °C 105 °C Figure 27-27. PE0 Input Threshold Voltage vs. V (PE0 Pin Read As '1') PE0 INPUT THRESHOLD VOLTAGE vs.
  • Page 325 -40 °C 27.7 BOD Thresholds and Analog Comparator Offset Figure 27-29. BOD Thresholds vs. Temperature (BODLEVEL Is 4.3V) BOD THRESHOLDS vs. TEMPERATURE BODLV IS 4.3 V 4,42 Rising Vcc 4,38 4,36 4,34 Falling Vcc 4,32 4,28 Temperature (C) AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 326 AT90PWM2/3/2B/3B Figure 27-30. BOD Thresholds vs. Temperature (BODLEVEL Is 2.7V) BOD THRESHOLDS vs. TEMPERATURE BODLV IS 2.7 V 2,82 Rising Vcc 2,78 2,76 2,74 Falling Vcc 2,72 2,68 Temperature (C) Figure 27-31. Analog Comparator Offset Voltage vs. Common Mode Voltage (V =5V) ANALOG COMPARATOR TYPICAL OFFSET VOLTAGE vs.
  • Page 327 Common Mode Voltage (V) Note: corrected on AT90PWM2B/3B to allow almost full scale use. 27.8 Analog Reference Figure 27-33. AREF Voltage vs. V AREF VOLTAGE vs. V 105 °C 85 °C 25 °C 2,55 -40 °C 2,45 2,35 Vcc (V) AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 328 AT90PWM2/3/2B/3B Figure 27-34. AREF Voltage vs. Temperature AREF VOLTAGE vs. TEMPERATURE 2.59 2.58 2.57 2.56 2.55 2.54 2.53 2.52 Temperature 27.9 Internal Oscillator Speed Figure 27-35. Watchdog Oscillator Frequency vs. V -40 °C 25 °C 85 °C 105 °C 4317I–AVR–01/08...
  • Page 329 Figure 27-36. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 10000 Cycles sampled w ith 250nS Temperature Figure 27-37. Calibrated 8 MHz RC Oscillator Frequency vs. V INT RC OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE 10000 Cycles sampled w ith 250nS AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 330 AT90PWM2/3/2B/3B Figure 27-38. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value OSCCAL 27.10 Current Consumption of Peripheral Units Figure 27-39. Brownout Detector Current vs. V BROWNOUT DETECTOR CURRENT vs. V 105 °C 85 °C 25 °C -40 °C 4317I–AVR–01/08...
  • Page 331 (ADC at 50 kHz) AREF vs. V ADC AT 50 KHz -40 °C 25 °C 85 °C Figure 27-41. Aref Current vs. V (ADC at 1 MHz) AREF vs. V ADC AT 1 MHz 85 ˚C 25 ˚C -40 ˚C AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 332 AT90PWM2/3/2B/3B Figure 27-42. Analog Comparator Current vs. V ANALOG COMPARATOR CURRENT vs. V -40 °C 105 °C 85 °C 25 °C Figure 27-43. Programming Current vs. V PROGRAMMING CURRENT vs. V -40 ˚C 25 ˚C 85 ˚C 4317I–AVR–01/08...
  • Page 333 Figure 27-45. Reset Supply Current vs. V (1 - 24 MHz, Excluding Current through the Reset Pull-up) RESET SUPPLY CURRENT vs. V EXCLUDING CURRENT THROUGH THE RESET PULLUP 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 3.0 V 2.7 V Frequency (MHz) AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 334 AT90PWM2/3/2B/3B Figure 27-46. Reset Supply Current vs. V (Clock Stopped, Excluding Current through the Reset Pull-up) RESET CURRENT vs. V (CLOCK STOPPED) EXCLUDING CURRENT THROUGH THE RESET PULLUP 0,05 0,04 0,03 0,02 105 °C -40 °C 0,01 85 °C 25 °C -0,01 Figure 27-47.
  • Page 335 AT90PWM2/3/2B/3B 28. Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0xFF) PICR2H page 170 (0xFE) PICR2L page 170 (0xFD) PFRC2B PCAE2B PISEL2B PELEV2B PFLTE2B PRFM2B3 PRFM2B2 PRFM2B1...
  • Page 336 WGM11 WGM10 page 123 (0x7F) DIDR1 – – ACMP0D AMP0PD AMP0ND ADC10D/ACMP1D ADC9D/AMP1PD ADC8D/AMP1ND page 252 (0x7E) DIDR0 ADC7D ADC6D ADC5D ADC4D ADC3D/ACMPMD ADC2D/ACMP2D ADC1D ADC0D page 252 (0x7D) Reserved – – – – – – – – AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 337 AT90PWM2/3/2B/3B Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0x7C) ADMUX REFS1 REFS0 ADLAR – MUX3 MUX2 MUX1 MUX0 page 247 (0x7B) ADCSRB ADHSM – – ADASCR ADTS3 ADTS2...
  • Page 338 4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The AT90PWM2/2B/3/3B is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
  • Page 339 AT90PWM2/3/2B/3B 29. Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS Rd ← Rd + Rr Rd, Rr Add two Registers Z,C,N,V,H Rd ← Rd + Rr + C Rd, Rr Add with Carry two Registers Z,C,N,V,H Rdh:Rdl ←...
  • Page 340 Store Program Memory None Rd ← P Rd, P In Port None P ← Rr P, Rr Out Port None STACK ← Rr PUSH Push Register on Stack None Rd ← STACK Pop Register from Stack None MCU CONTROL INSTRUCTIONS AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 341 AT90PWM2/3/2B/3B Mnemonics Operands Description Operation Flags #Clocks No Operation None SLEEP Sleep (see specific descr. for Sleep function) None Watchdog Reset (see specific descr. for WDR/timer) None BREAK Break For On-chip Debug Only None 4317I–AVR–01/08...
  • Page 342 Note: All packages are Pb free, fully LHF Note: This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. Note: Parts numbers are for shipping in sticks (SO) or in trays (QFN). Thes devices can also be supplied in Tape and Reel. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.
  • Page 343 AT90PWM2/3/2B/3B 31. Package Information Package Type SO24 24-Lead, Small Outline Package SO32 32-Lead, Small Outline Package QFN32 32-Lead, Quad Flat No lead 4317I–AVR–01/08...
  • Page 344 31.1 SO24 AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 345 AT90PWM2/3/2B/3B 31.2 SO32 4317I–AVR–01/08...
  • Page 346 31.3 QFN32 AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 347 AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 348 32. Errata 32.1 AT90PWM2&3 Rev. A (Mask Revision) • PGM: PSCxRB Fuse • PSC: Prescaler • PSC: PAOCnA and PAOCnB Register Bits (Asynchronous output control) • PSC: PEVxA/B Flag Bits • PSC: Output Polarity in Centered Mode • PSC: Output Activity •...
  • Page 349 AT90PWM2/3/2B/3B 5. PSC: Output Polarity in Centered Mode In centered mode, PSCOUTn1 outputs are not inverted, so they are active at the same time as PSCOUTn0. Workaround: Use an external inverter (or a driver with inverting output) to drive the load on PSCOUTn1.
  • Page 350 At 2 Mhz the ADC can be used as a 7 bits ADC. 3. DAC Driver linearity above 3.6V With 5V Vcc, the DAC driver linearity is poor when DAC output level is above Vcc-1V. At 5V, DAC output for 1023 will be around 5V - 40mV. Work around: . AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 351 AT90PWM2/3/2B/3B Use, when Vcc=5V, Vref below Vcc-1V. Or, when Vref=Vcc=5V, do not uses codes above 800. 4. DAC Update in Autotrig mode If the cpu writes in DACH register at the same instant that the selected trigger source occurs and DAC Auto Trigger is enabled, the DACH register is not updated by the new value.
  • Page 352 33. Datasheet Revision History for AT90PWM2/2B/3/3B Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 33.1 Changes from 4317A- to 4317B 1. PSC section has been rewritten.
  • Page 353 AT90PWM2/3/2B/3B 3. PSC : the Balance Flank Width Modulation is done On-Time 1 rather than On-Time 0 (correction of figures) 4. Updated “Maximum Speed vs. VCC” on page 303 (formulas are removed) 5. Update of the “Errata” on page 350 33.8...
  • Page 354: Table Of Contents

    General Purpose I/O Registers ...............27 System Clock ..................29 Clock Systems and their Distribution ...............29 Clock Sources ....................31 Default Clock Source ..................32 Low Power Crystal Oscillator ................32 Calibrated Internal RC Oscillator ..............33 PLL ........................35 128 kHz Internal Oscillator ................37 External Clock ....................37 AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 355 Minimizing Power Consumption ..............44 System Control and Reset ..............46 Internal Voltage Reference ................51 Watchdog Timer ....................52 10 Interrupts ....................57 10.1 Interrupt Vectors in AT90PWM2/2B/3/3B ............57 11 I/O-Ports ....................62 11.1 Introduction ......................62 11.2 Ports as General Digital I/O ................63 11.3...
  • Page 356 PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and Disactivate Out- put 156 16.19 PSC2 Outputs ....................158 16.20 Analog Synchronization .................159 16.21 Interrupt Handling ..................159 16.22 PSC Synchronization ..................159 16.23 PSC Clock Sources ..................160 16.24 Interrupts .......................161 16.25 PSC Register Definition .................162 16.26 PSC2 Specific Register .................171 AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 357 AT90PWM2/3/2B/3B 17 Serial Peripheral Interface – SPI ............174 17.1 Features ......................174 17.2 SS Pin Functionality ..................179 17.3 Data Modes ....................182 18 USART ....................184 18.1 Features ......................184 18.2 Overview ......................185 18.3 Clock Generation ...................186 18.4 Serial Frame ....................188 18.5 USART Initialization ..................189...
  • Page 358 25.5 Calibration Byte .....................283 25.6 Parallel Programming Parameters, Pin Mapping, and Commands ....283 25.7 Serial Programming Pin Mapping ..............285 25.8 Parallel Programming ..................286 25.9 Serial Downloading ..................294 (1) ....................299 26 Electrical Characteristics 26.1 Absolute Maximum Ratings* .................299 AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 359 QFN32 ......................348 32 Errata ..................... 350 32.1 AT90PWM2&3 Rev. A (Mask Revision) ............350 32.2 AT90PWM2B/3B ...................352 33 Datasheet Revision History for AT90PWM2/2B/3/3B ......354 33.1 Changes from 4317A- to 4317B ..............354 33.2 Changes from 4317B- to 4317C ..............354 33.3 Changes from 4317C- to 4317D ..............354...
  • Page 360 33.4 Changes from 4317D to 4317E ..............354 33.5 Changes from 4317E to 4317F ..............354 33.6 Changes from 4317F to 4317G ..............354 33.7 Changes from 4317G to 4317H ..............354 33.8 Changes from 4317H to 4317I ..............355 AT90PWM2/3/2B/3B 4317I–AVR–01/08...
  • Page 361 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY...

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