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5.8
Reset and Interrupt Handling
AT90PWM2/3/2B/3B
16
Figure 5-4.
The Parallel Instruction Fetches and Instruction Executions
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 5-5
shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Figure 5-5.
Single Cycle ALU Operation
clk
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate program vector in the program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt. Depending on the Program
Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12
are programmed. This feature improves software security. See the section
ming" on page 279
for details.
The lowest addresses in the program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is PSC2 CAPT – the PSC2 Capture
Event. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the
IVSEL bit in the MCU Control Register (MCUCR). Refer to
mation. The Reset Vector can also be moved to the start of the Boot Flash section by
programming the BOOTRST Fuse, see
gramming" on page
265.
T1
CPU
T1
CPU
"Boot Loader Support – Read-While-Write Self-Pro-
T2
T3
T2
T3
"Memory Program-
"Interrupts" on page
57. The list also
"Interrupts" on page 57
T4
T4
for more infor-
4317I–AVR–01/08
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