Clock Sources - Atmel AT90PWM2 Manual

7.1.5 ADC Clock – clk
7.2

Clock Sources

4317I–AVR–01/08
ADC
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks
in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion
results.
The device has the following clock source options, selectable by Flash Fuse bits as illustrated
Table 7-1. The clock from the selected source is input to the AVR clock generator, and routed to
the appropriate modules.
Table 7-1. Device Clocking Options Select
Device Clocking Option
External Crystal/Ceramic Resonator
Reserved
PLL output divided by 4 : 16 MHz
Calibrated Internal RC Oscillator
Reserved
External Clock
Note: 1. For all fuses "1" means unprogrammed while "0" means programmed.
Table 7-2. Device Clocking Options Select AT90PWM2B/3B
Device Clocking Option
External Crystal/Ceramic Resonator
PLL output divided by 4 : 16 MHz / PLL driven by External
Crystal/Ceramic Resonator
PLL output divided by 4 : 16 MHz / PLL driven by External
Crystal/Ceramic Resonator
Reserved
PLL output divided by 4 : 16 MHz
Calibrated Internal RC Oscillator
PLL output divided by 4 : 16 MHz / PLL driven by External
clock
External Clock
1.For all fuses "1" means unprogrammed while "0" means programmed
2.Ext Osc : External Osc
3.RC Osc : Internal RC Oscillator
4.Ext Clk : External Clock Input
The various choices for each clocking option is given in the following sections. When the CPU
wakes up from Power-down or Power-save, the selected clock source is used to time the start-
up, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts
AT90PWM2/3/2B/3B
(1)
AT90PWM2/3
System
Clock PLL Input
(2)
Ext Osc RC Osc
Ext Osc Ext Osc
PLL / 4 Ext Osc
N/A N/A
PLL / 4 RC Osc
RC Osc RC Osc
PLL / 4 Ext Clk
Ext Clk RC Osc
CKSEL3..0
1111 - 1000
0111- 0100
0011
0010
0001
0000
CKSEL3..0
(1)
(3)
1111 - 1000
0100
0101
0111- 0110
0011
0010
(4)
0001
0000
31