Avr Cpu Core; Introduction; Architectural Overview - Atmel AT90PWM2 Manual

5. AVR CPU Core

5.1

Introduction

5.2

Architectural Overview

4317I–AVR–01/08
This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.
Figure 5-1. Block Diagram of the AVR Architecture
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Control Lines
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruc-
tion is pre-fetched from the program memory. This concept enables instructions to be executed
in every clock cycle. The program memory is In-System Reprogrammable Flash memory.
Data Bus 8-bit
Program Status
Counter and Control
32 x 8
General
Purpose
Registrers
Data
SRAM
EEPROM
I/O Lines
AT90PWM2/3/2B/3B
Interrupt
Watchdog
Timer
ALU
Analog
Comparator
I/O Module1
I/O Module 2
I/O Module n
Unit
SPI
Unit
11