Atmel AVR AT90S2313 Manual
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Atmel AVR AT90S2313 Manual

8-bit avr microcontroller with 2k bytes of in-system programmable flash
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Features
®
•
Utilizes the AVR
RISC Architecture
•
AVR – High-performance and Low-power RISC Architecture
– 118 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General-purpose Working Registers
– Up to 10 MIPS Throughput at 10 MHz
•
Data and Nonvolatile Program Memory
– 2K Bytes of In-System Programmable Flash
Endurance 1,000 Write/Erase Cycles
– 128 Bytes of SRAM
– 128 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
•
Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler
– One 16-bit Timer/Counter with Separate Prescaler,
Compare, Capture Modes and 8-, 9- or 10-bit PWM
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
– SPI Serial Interface for In-System Programming
– Full Duplex UART
•
• Special Microcontroller Features
– Low-power Idle and Power-down Modes
– External and Internal Interrupt Sources
•
• Specifications
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation
•
Power Consumption at 4 MHz, 3V, 25°C
– Active: 2.8 mA
– Idle Mode: 0.8 mA
– Power-down Mode: <1 µA
•
I/O and Packages
– 15 Programmable I/O Lines
– 20-pin PDIP and SOIC
•
Operating Voltages
– 2.7 - 6.0V (AT90S2313-4)
– 4.0 - 6.0V (AT90S2313-10)
•
Speed Grades
– 0 - 4 MHz (AT90S2313-4)
– 0 - 10 MHz (AT90S2313-10)
Pin Configuration
PDIP/SOIC
8-bit
Microcontroller
with 2K Bytes
of In-System
Programmable
Flash
AT90S2313
Rev. 0839G–08/01
1

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Summary of Contents for Atmel AVR AT90S2313

  • Page 1 Features ® • Utilizes the AVR RISC Architecture • AVR – High-performance and Low-power RISC Architecture – 118 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General-purpose Working Registers – Up to 10 MIPS Throughput at 10 MHz •...
  • Page 2 Description The AT90S2313 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the AT90S2313 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general-purpose working regis- ters.

  • Page 3: Pin Descriptions

    SPI serial interface or by a conventional nonvolatile memory programmer. By combining an enhanced RISC 8-bit CPU with In-System Pro- grammable Flash on a monolithic chip, the Atmel AT90S2313 is a powerful microcontroller that provides a highly flexible and cost-effective solution to many embed- ded control applications.

  • Page 4: Crystal Oscillator

    Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator, as shown in Figure 2. Either a quartz crystal or a ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure 3.

  • Page 5: Architectural Overview

    AT90S2313 Architectural The fast-access register file concept contains 32 x 8-bit general-purpose working regis- ters with a single clock cycle access time. This means that during one single clock cycle, Overview one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from the register file, the operation is executed, and the result is stored back in the register file –...
  • Page 6 The I/O memory space contains 64 addresses for CPU peripheral functions such as control registers, timer/counters, A/D converters and other I/O functions. The I/O mem- ory can be accessed directly or as the Data Space locations following those of the register file, $20 - $5F.
  • Page 7 AT90S2313 Figure 5. Memory Maps A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the Status Register. All the different interrupts have a sepa- r a te i nt er r up t v e c to r i n t h e i n te r r u pt v ec t or t a bl e at th e b e gi n ni n g of th e program memory.

  • Page 8: General-Purpose Register File

    General-purpose Figure 6 shows the structure of the 32 general-purpose registers in the CPU. Register File Figure 6. AVR CPU General-purpose Working Registers Addr. … General Purpose Working Registers … X-register low byte X-register high byte Y-register low byte Y-register high byte Z-register low byte Z-register high byte All the register operating instructions in the instruction set have direct and single-cycle...

  • Page 9: Alu - Arithmetic Logic Unit

    AT90S2313 In the different addressing modes these address registers have functions as fixed dis- placement, automatic increment and decrement (see the descriptions for the different instructions). ALU – Arithmetic Logic The high-performance AVR ALU operates in direct connection with all the 32 general- Unit purpose working registers.

  • Page 10: Sram Data Memory

    SRAM Data Memory Figure 8 shows how the AT90S2313 data memory is organized. Figure 8. SRAM Organization Register File Data Address Space … … I/O Registers … … Internal SRAM … The 224 data memory locations address the Register file, I/O memory and the data SRAM.

  • Page 11: Program And Data Addressing Modes

    AT90S2313 Program and Data The AT90S2313 AVR RISC microcontroller supports powerful and efficient addressing Addressing Modes modes for access to the program memory (Flash) and data memory. This section describes the different addressing modes supported by the AVR architecture. In the fig- ures, OP means the operation code part of the instruction word.

  • Page 12: Data Indirect With Displacement

    Operand address is contained in 6 bits of the instruction word. n is the destination or source register address. Data Direct Figure 12. Direct Data Addressing A 16-bit data address is contained in the 16 LSBs of a 2-word instruction. Rd/Rr specify the destination or source register.
  • Page 13 AT90S2313 Data Indirect with Pre- Figure 15. Data Indirect Addressing with Pre-decrement decrement The X-, Y- or Z-register is decremented before the operation. Operand address is the decremented contents of the X-, Y- or Z-register. Data Indirect with Post- Figure 16. Data Indirect Addressing with Post-increment increment The X-, Y- or Z-register is incremented after the operation.

  • Page 14: Memory Access And Instruction Execution Timing

    Indirect Program Addressing, Figure 18. Indirect Program Memory Addressing IJMP and ICALL Program execution continues at address contained by the Z-register (i.e., the PC is loaded with the contents of the Z-register). Relative Program Addressing, Figure 19. Relative Program Memory Addressing RJMP and RCALL Program execution continues at address PC + k + 1.
  • Page 15 AT90S2313 Figure 20. The Parallel Instruction Fetches and Instruction Executions System Clock Ø 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 21 shows the internal timing concept for the register file. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register.
  • Page 16 I/O Memory The I/O space definition of the AT90S2313 is shown in Table 1. Table 1. AT90S2313 I/O Space Address Hex Name Function $3F ($5F) SREG Status Register $3D ($5D) Stack Pointer Low $3B ($5B) GIMSK General Interrupt MaSK register $3A ($5A) GIFR General Interrupt Flag Register...
  • Page 17 AT90S2313 pose working registers and the I/O space. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details.

  • Page 18: Reset And Interrupt Handling

    • Bit 0 – C: Carry Flag The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set description for detailed information. Note that the Status Register is not automatically stored when entering an interrupt rou- tine and restored when returning from an interrupt routine.

  • Page 19: Reset Sources

    AT90S2313 Table 2. Reset and Interrupt Vectors (Continued) Vector No. Program Address Source Interrupt Definition $008 UART, UDRE UART Data Register Empty $009 UART, TX UART, TX Complete $00A ANA_COMP Analog Comparator The most typical and general program setup for the Reset and Interrupt vector addresses are: Address Labels Code Comments...

  • Page 20: Power-On Reset

    Figure 23. Reset Logic Table 3. Reset Characteristics (V = 5.0V) Symbol Parameter Units Power-on Reset Threshold Voltage (rising) Power-on Reset Threshold Voltage (falling) RESET Pin Threshold Voltage – 0.85 V Reset Delay Time-out Period 11.0 16.0 21.0 TOUT FSTRT Unprogrammed Reset Delay Time-out Period 0.25 0.28...

  • Page 21: External Reset

    AT90S2313 Figure 24. MCU Start-up, RESET Tied to V RESET TOUT TIME-OUT INTERNAL RESET Figure 25. MCU Start-up, RESET Controlled Externally RESET TOUT TIME-OUT INTERNAL RESET External Reset An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running.

  • Page 22: Interrupt Handling

    Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one XTAL cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t . Refer to page 38 for details on operation of the Watchdog. TOUT Figure 27.
  • Page 23 AT90S2313 General Interrupt Mask Register – GIMSK $3B ($5B) INT1 INT0 – – – – – – GIMSK Read/Write Initial value • Bit 7 – INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled.

  • Page 24: Timer/Counter Interrupt Mask Register - Timsk

    Timer/Counter Interrupt Mask Register – TIMSK $39 ($59) TOIE1 OCIE1A – – TICIE1 – TOIE0 – TIMSK Read/Write Initial value • Bit 7 – TOIE1: Timer/Counter1 Overflow Interrupt Enable When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow Interrupt is enabled.

  • Page 25: External Interrupts

    AT90S2313 when executing the corresponding interrupt handling vector. Alternatively, OCF1A is cleared by writing a logical “1” to the flag. When the I-bit in SREG and OCIE1A (Timer/Counter1 Compare Match Interrupt Enable) and the OCF1A are set (one), the Timer/Counter1 Compare Match Interrupt is executed. •...
  • Page 26 MCU Control Register – The MCU Control Register contains control bits for general MCU functions. MCUCR $35 ($55) – – ISC11 ISC10 ISC01 ISC00 MCUCR Read/Write Initial value • Bits 7, 6 – Res: Reserved Bits These bits are reserved bits in the AT90S2313 and always read as zero. •...

  • Page 27: Sleep Modes

    AT90S2313 Sleep Modes To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruc- tion must be executed. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU awakes, executes the interrupt routine, and resumes execution from the instruction following SLEEP.

  • Page 28: Timer/Counter Prescaler

    Timer/Counter Prescaler Figure 28 shows the general Timer/Counter prescaler. Figure 28. Timer/Counter Prescaler TCK1 TCK0 The four different prescaled selections are: CK/8, CK/64, CK/256 and CK/1024, where CK is the oscillator clock. For the two Timer/Counters, added selections such as CK, external clock source and stop can be selected as clock sources.

  • Page 29: Timer/Counter0 Control Register - Tccr0

    AT90S2313 Figure 29. Timer/Counter0 Block Diagram Timer/Counter0 Control Register – TCCR0 $33 ($53) – – – – – CS02 CS01 CS00 TCCR0 Read/Write Initial value • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the AT90S2313 and always read zero. •...

  • Page 30: Timer/Counter0 - Tcnt0

    The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from the CK oscillator clock. If the external pin modes are used for Timer/Counter0, transitions on PD4/(T0) will clock the counter even if the pin is configured as an output.

  • Page 31: Timer/Counter1 Control Register A - Tccr1A

    AT90S2313 When Timer/Counter1 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period.

  • Page 32: Timer/Counter1 Control Register B - Tccr1B

    direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 8. Table 8. Compare 1 Mode Select COM1A1 COM1A0 Description Timer/Counter1 disconnected from output pin OC1 Toggle the OC1 output line. Clear the OC1 output line (to zero).
  • Page 33 AT90S2313 • Bit 3 – CTC1: Clear Timer/Counter1 on Compare Match When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock cycle after a compareA match. If the CTC1 control bit is cleared, Timer/Counter1 contin- ues counting and is unaffected by a compare match.
  • Page 34 rupts must be disabled during access from the main program or interrupts if interrupts are re-enabled. • TCNT1 Timer/Counter1 Write: When the CPU writes to the high byte TCNT1H, the written data is placed in the TEMP register. Next, when the CPU writes the low byte TCNT1L, this byte of data is combined with the byte data in the TEMP register, and all 16 bits are written to the TCNT1 Timer/Counter1 register simultaneously.

  • Page 35: Timer/Counter1 Input Capture Register - Icr1H And Icr1L

    AT90S2313 Timer/Counter1 Input Capture Register – ICR1H and ICR1L $25 ($45) ICR1H $24 ($44) ICR1L Read/Write Initial value The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting [ICES1]) of the signal at the input capture pin (ICP) is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register (ICR1).
  • Page 36 Table 12. Compare1 Mode Select in PWM Mode COM1A1 COM1A0 Effect on OC1 Not connected Not connected Cleared on compare match, upcounting. Set on compare match, down-counting (non-inverted PWM). Cleared on compare match, downcounting. Set on compare match, up-counting (inverted PWM). Note that in the PWM mode, the 10 least significant OCR1A bits, when written, are transferred to a temporary location.
  • Page 37 AT90S2313 Table 13. PWM Outputs OCR = $0000 or TOP COM1A1 COM1A0 OCR1A Output OC1 $0000 $0000 In PWM mode, the Timer Overflow Flag1 (TOV1) is set when the counter advances from $0000. Timer Overflow Interrupt1 operates exactly as in normal Timer/Counter mode (i.e., it is executed when TOV1 is set, provided that Timer Overflow Interrupt1 and global interrupts are enabled).

  • Page 38: Watchdog Timer Control Register - Wdtcr

    Watchdog Timer The Watchdog Timer is clocked from a separate on-chip oscillator that runs at 1 MHz. This is the typical value at V = 5V. See characterization data for typical values at other levels. By controlling the Watchdog Timer prescaler, the Watchdog reset interval can be adjusted.
  • Page 39 AT90S2313 • Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1 and 0 The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding time-out periods are shown in Table 14. Table 14.

  • Page 40: Eeprom Control Register

    EEPROM Read/Write The EEPROM access registers are accessible in the I/O space. Access The write access time is in the range of 2.5 - 4 ms, depending on the V voltages. A self-timing function, however, lets the user software detect when the next byte can be written.
  • Page 41 AT90S2313 • Bit 2 – EEMWE: EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set (one), setting EEWE will write data to the EEPROM at the selected address.
  • Page 42 1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This is best done by an external low V Reset Protection circuit, often referred to as a Brown-out Detector (BOD). Please refer to the AVR 180 applica- tion note for design considerations regarding power-on reset and low-voltage detection.

  • Page 43: Data Transmission

    AT90S2313 UART The AT90S2313 features a full duplex (separate receive and transmit registers) Univer- sal Asynchronous Receiver and Transmitter (UART). The main features are: • Baud Rate Generator that can Generate a Large Number of Baud Rates (bps) • High Baud Rates at Low XTAL Frequencies •...

  • Page 44: Data Reception

    Register (USR) is set. When this bit is set (one), the UART is ready to receive the next character. At the same time as the data is transferred from UDR to the 10(11)-bit shift register, bit 0 of the shift register is cleared (start bit) and bit 9 or 10 is set (stop bit). If 9- bit data word is selected (the CHR9 bit in the UART Control Register [UCR] is set), the TXB8 bit in UCR is transferred to bit 9 in the Transmit shift register.
  • Page 45 AT90S2313 The receiver front-end logic samples the signal on the RXD pin at a frequency of 16 times the baud rate. While the line is idle, one single sample of logical “0” will be inter- preted as the falling edge of a start bit, and the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample.

  • Page 46: Uart Control

    UART Control The UART I/O Data Register – $0C ($2C) Read/Write Initial value The UDR register is actually two physically separate registers sharing the same I/O address. When writing to the register, the UART Transmit Data register is written. When reading from UDR, the UART Receive Data register is read.
  • Page 47 AT90S2313 The FE bit is cleared when the stop bit of received data is one. • Bit 3 – OR: Overrun This bit is set if an Overrun condition is detected (i.e., when a character already present in the UDR register is not read before the next character has been shifted into the Receiver Shift register).
  • Page 48 Baud Rate Generator The baud rate generator is a frequency divider that generates baud rates according to the following equation: BAUD ------------------------------------ - 16(UBRR • BAUD = Baud Rate • = Crystal Clock frequency • UBRR = Contents of the UART Baud Rate register (UBRR) (0 - 255) For standard crystal frequencies, the most commonly used baud rates can be generated by using the UBRR settings in Table 15.
  • Page 49 AT90S2313 Table 15. UBRR Settings at Various Crystal Frequencies Baud Rate 1 MHz %Error 1.8432 MHz %Error 2 MHz %Error 2.4576 MHz %Error 2400 UBRR= 0.2 UBRR= 0.0 UBRR= 0.2 UBRR= 4800 UBRR= 0.2 UBRR= 0.0 UBRR= 0.2 UBRR= 9600 UBRR= 7.5 UBRR= 0.0 UBRR= 0.2 UBRR=...

  • Page 50: Analog Comparator

    Analog Comparator The Analog Comparator compares the input values on the positive input AIN0 (PB0) and the negative input PB1(AIN1). When the voltage on the positive input PB0 (AIN0) is higher than the voltage on the negative input PB1 (AIN1), the Analog Comparator Out- put, ACO is set (one).
  • Page 51 AT90S2313 • Bit 3 – ACIE: Analog Comparator Interrupt Enable When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the Ana- log Comparator interrupt is activated. When cleared (zero), the interrupt is disabled. •...
  • Page 52 I/O Ports All AVR ports have true read-modify-write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintention- ally changing the direction of any other pin with the SBI and CBI instructions. The same applies for changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
  • Page 53 AT90S2313 The Port B Input Pins address (PINB) is not a register; this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the pins are read. Port B as General Digital I/O All eight pins in Port B have equal functionality when used as digital I/O pins.
  • Page 54 Port B Schematics Note that all port pins are synchronized. The synchronization latches are, however, not shown in the figures. Figure 38. Port B Schematic Diagram (Pins PB0 and PB1) AT90S2313 0839G–08/01...
  • Page 55 AT90S2313 Figure 39. Port B Schematic Diagram (Pin PB3) PULL- RESET DDB3 RESET PORTB3 COM1A0 WRITE PORTB COM1A1 WRITE DDRB READ PORTB LATCH OUTPUT COMP. MATCH1 READ PORTB PIN MODE SELECT READ DDRB Figure 40. Port B Schematic Diagram (Pins PB2 and PB4) 0839G–08/01...
  • Page 56 Figure 41. Port B Schematic Diagram (Pin PB5) Figure 42. Port B Schematic Diagram (Pin PB6) AT90S2313 0839G–08/01...
  • Page 57 AT90S2313 Figure 43. Port B Schematic Diagram (Pin PB7) Port D Three I/O memory address locations are allocated for the Port D: one each for the Data Register – PORTD, $12($32), Data Direction Register – DDRD, $11($31) and the Port D Input Pins –...

  • Page 58: Alternate Functions Of Port D

    Port D Data Register – PORTD $12 ($32) – PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 PORTD Read/Write Initial value Port D Data Direction Register – DDRD $11 ($31) – DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 DDRD Read/Write Initial value Port D Input Pins Address –...

  • Page 59: Port D Schematics

    AT90S2313 • INT0 – Port D, Bit 2 INT0, External Interrupt Source 0. The PD2 pin can serve as an external interrupt source to the MCU. See the interrupt description for further details and how to enable the source. • TXD – Port D, Bit 1 Transmit Data (Data output pin for the UART).
  • Page 60 Figure 45. Port D Schematic Diagram (Pin PD1) PULL- RESET DDD1 RESET PORTD1 WRITE PORTD TXEN WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD TXD: UART TRANSMIT DATA UART TRANSMIT ENABLE TXEN: Figure 46. Port D Schematic Diagram (Pins PD2 and PD3) AT90S2313 0839G–08/01...
  • Page 61 AT90S2313 Figure 47. Port D Schematic Diagram (Pins PD4 and PD5) PULL- RESET DDDn RESET PORTDn WRITE PORTD TIMERm CLOCK WRITE DDRD SENSE CONTROL SOURCE MUX READ PORTD LATCH READ PORTD PIN READ DDRD 4, 5 0, 1 CSm0 CSm2 CSm1 Figure 48.

  • Page 62: Memory Programming

    Chip Erase. Signature Bytes All Atmel microcontrollers have a 3-byte signature code that identifies the device. This code can be read in both serial and parallel mode. The three bytes reside in a separate address space.

  • Page 63: Parallel Programming

    AT90S2313 Table 22. Supply Voltage during Programming Part Serial Programming Parallel Programming AT90S2313 2.7 - 6.0V 4.5 - 5.5V Parallel Programming This section describes how to parallel program and verify Flash program memory, EEPROM data memory, Lock bits and Fuse bits in the AT90S2313. Signal Names In this section, some pins of the AT90S2313 are referenced by signal names describing their function during parallel programming.

  • Page 64: Enter Programming Mode

    Table 24. XA1 and XA0 Coding Action when XTAL1 is Pulsed Load Flash or EEPROM Address (High or low address byte determined by BS) Load Data (High or Low data byte for Flash determined by BS) Load Command No Action, Idle Table 25.
  • Page 65 AT90S2313 4. Give XTAL1 a positive pulse. This loads the command. B: Load Address High Byte 1. Set XA1, XA0 to “00”. This enables address loading. 2. Set BS to “1”. This selects high byte. 3. Set DATA = Address high byte ($00 - $03). 4.

  • Page 66: Reading The Flash

    Figure 50. Programming the Flash DATA ADDR. HIGH ADDR. LOW DATA LOW XTAL1 RDY/BSY RESET Figure 51. Programming the Flash (Continued) DATA DATA HIGH XTAL1 RDY/BSY RESET +12V Reading the Flash The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash”...

  • Page 67: Programming The Lock Bits

    AT90S2313 Programming the EEPROM The programming algorithm for the EEPROM data memory is as follows (refer to “Pro- gramming the Flash” for details on command, address and data loading): 1. A: Load Command “0001 0001”. 2. C: Load Address Low Byte ($00 - $7F). 3.

  • Page 68: Parallel Programming Characteristics

    Reading the Signature Bytes The algorithm for reading the signature bytes is as follows (refer to “Programming the Flash” on page 64 for details on command and address loading): 1. A: Load Command “0000 1000”. 2. C: Load Address Low Byte ($00 - $02). Set OE to “0”, and BS to “0”.

  • Page 69: Serial Downloading

    AT90S2313 Serial Downloading Both the program and data memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). See Figure 53. After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase instructions can be executed.
  • Page 70 2. Wait for at least 20 ms and enable serial programming by sending the Program- ming Enable serial instruction to the MOSI (PB5) pin. 3. The serial programming instructions will not work if the communication is out of synchronization. When in sync, the second byte ($53) will echo back when issu- ing the third byte of the Programming Enable instruction.

  • Page 71: Operation

    AT90S2313 Figure 54. Serial Programming Waveforms Table 28. Serial Programming Instruction Set Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte4 Operation Enable serial programming while 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Programming Enable RESET is low. Chip erase Flash and EEPROM 1010 1100 100x xxxx...

  • Page 72: Serial Programming Characteristics

    Serial Programming Figure 55. Serial Programming Timing Characteristics MOSI SLSH OVSH SHOX SHSL MISO SLIV Table 29. Serial Programming Characteristics, T = -40°C to 85°C, V = 2.7 - 6.0V (unless otherwise noted) Symbol Parameter Units Oscillator Frequency (V = 2.7 - 6.0V) CLCL Oscillator Period (V = 2.7 - 6.0V)

  • Page 73: Electrical Characteristics

    AT90S2313 Electrical Characteristics Absolute Maximum Ratings* *NOTICE: Stresses beyond those listed under “Absolute Operating Temperature........-55°C to +125°C Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and Storage Temperature ........-65°C to +150°C functional operation of the device at these or Voltage on Any Pin Except RESET other conditions beyond those indicated in the...

  • Page 74: External Clock Drive Waveforms

    Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low. 2. “Min” means the lowest value where the pin is guaranteed to be read as high. 3. Although each I/O port can sink more than the test conditions (20 mA at V = 5V, 10 mA at V = 3V) under steady state conditions (non-transient), the following must...

  • Page 75: Typical Characteristics

    AT90S2313 Typical The following charts show typical behavior. These figures are not tested during manu- facturing. All current consumption measurements are performed with all I/O pins Characteristics configured as inputs and with internal pull-ups enabled. A sine wave generator with rail- to-rail output is used as clock source.
  • Page 76 Figure 58. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs. V FREQUENCY = 4 MHz T = 25 ˚ T = 85 ˚ Figure 59. Idle Supply Current vs. Frequency IDLE SUPPLY CURRENT vs. FREQUENCY T = 25˚C = 6V = 5.5V = 5V = 4.5V...
  • Page 77 AT90S2313 Figure 60. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs. V FREQUENCY = 4 MHz T = 25 ˚ T = 85 ˚ Figure 61. Power-down Supply Current vs. V POWER DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER DISABLED T = 85 ˚...
  • Page 78 Figure 62. Power-down Supply Current vs. V POWER DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ENABLED T = 25 ˚ T = 85 ˚ Figure 63. Analog Comparator Current vs. V ANALOG COMPARATOR CURRENT vs. V T = 25 ˚ T = 85 ˚...
  • Page 79 AT90S2313 Note: Analog Comparator offset voltage is measured as absolute offset. Figure 64. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE V = 5V T = 25 ˚ T = 85 ˚ Common Mode Voltage (V) Figure 65.
  • Page 80 Figure 66. Analog Comparator Input Leakage Current ANALOG COMPARATOR INPUT LEAKAGE CURRENT V = 6V T = 25 ˚ V (V) Figure 67. Watchdog Oscillator Frequency vs. V WATCHDOG OSCILLATOR FREQUENCY vs. V 1600 T = 25 ˚ 1400 T = 85 ˚...
  • Page 81 AT90S2313 Note: Sink and source capabilities of I/O ports are measured on one pin at a time. Figure 68. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE V = 5V T = 25 ˚ T = 85 ˚...
  • Page 82 Figure 70. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE V = 5V T = 25 ˚ T = 85 ˚ Figure 71. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE V = 5V T = 25 ˚...
  • Page 83 AT90S2313 Figure 72. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE V = 2.7V T = 25 ˚ T = 85 ˚ Figure 73. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE V = 2.7V T = 25 ˚...
  • Page 84 Figure 74. I/O Pin Input Threshold Voltage vs. V I/O PIN INPUT THRESHOLD VOLTAGE vs. V T = 25 ˚ Figure 75. I/O Pin Input Hysteresis vs. V I/O PIN INPUT HYSTERESIS vs. V T = 25 ˚ 0.18 0.16 0.14 0.12 0.08...

  • Page 85: Register Summary

    AT90S2313 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page $3F ($5F) SREG page 17 $3E ($5E) Reserved $3D ($5D) page 18 $3C ($5C) Reserved $3B ($5B) GIMSK INT1 INT0 page 23...

  • Page 86: Instruction Set Summary

    Instruction Set Summary Mnemonic Operands Description Operation Flags # Clocks ARITHMETIC AND LOGIC INSTRUCTIONS Rd, Rr Add Two Registers Rd ← Rd + Rr Z,C,N,V,H Rd, Rr Add with Carry Two Registers Rd ← Rd + Rr + C Z,C,N,V,H ADIW Rdl, K Add Immediate to Word...
  • Page 87 AT90S2313 Instruction Set Summary (Continued) Mnemonic Operands Description Operation Flags # Clocks DATA TRANSFER INSTRUCTIONS Rd, Rr Move between Registers None ← Rd, K Load Immediate None ← Rd, X Load Indirect None ← Rd, X+ Load Indirect and Post-Inc. (X), X X + 1 None...

  • Page 88: Ordering Information

    Ordering Information Speed (MHz) Power Supply Ordering Code Package Operation Range 2.7 - 6.0V AT90S2313-4PC 20P3 Commercial AT90S2313-4SC (0°C to 70°C) AT90S2313-4PI 20P3 Industrial AT90S2313-4SI (-40°C to 85°C) 4.0 - 6.0V AT90S2313-10PC 20P3 Commercial AT90S2313-10SC (0°C to 70°C) AT90S2313-10PI 20P3 Industrial AT90S2313-10SI (-40°C to 85°C)

  • Page 89: Packaging Information

    AT90S2313 Packaging Information 20P3, 20-lead, 0.300" Wide, 20S, 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) Plastic Gull Wing Small Outline (SOIC) Dimensions in Inches and (Millimeters) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-001 BA 1.060(26.9) 0.020 (0.508) 0.013 (0.330) .980(24.9) .280(7.11) 0.299 (7.60)
  • Page 90 No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems.
  • Page 91 WWW.ALLDATASHEET.COM Copyright © Each Manufacturing Company. All Datasheets cannot be modified without permission. This datasheet has been download from : www.AllDataSheet.com 100% Free DataSheet Search Site. Free Download. No Register. Fast Search System. www.AllDataSheet.com...

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