Atmel AT90PWM2 Manual page 308

4317I–AVR–01/08
Figure 26-7. Parallel Programming Timing, Reading Sequence (within the Same Page) with
Timing Requirements
LOAD ADDRESS
(LOW BYTE)
XTAL1
BS1
OE
DATA ADDR0 (Low Byte)
XA0
XA1
Note: 1. ggThe timing requirements shown in
reading operation.
Table 26-6. Parallel Programming Characteristics, V
Symbol Parameter
V Programming Enable Voltage
PP
I Programming Enable Current
PP
t Data and Control Valid before XTAL1 High
DVXH
t XTAL1 Low to XTAL1 High
XLXH
t XTAL1 Pulse Width High
XHXL
t Data and Control Hold after XTAL1 Low
XLDX
t XTAL1 Low to WR Low
XLWL
t XTAL1 Low to PAGEL high
XLPH
t PAGEL low to XTAL1 high
PLXH
t BS1 Valid before PAGEL High
BVPH
t PAGEL Pulse Width High
PHPL
t BS1 Hold after PAGEL Low
PLBX
t BS2/1 Hold after WR Low
WLBX
t PAGEL Low to WR Low
PLWL
t BS1 Valid to WR Low
BVWL
t WR Pulse Width Low
WLWH
t WR Low to RDY/BSY Low
WLRL
t WR Low to RDY/BSY High
WLRH
t WR Low to RDY/BSY High for Chip Erase
WLRH_CE
(1)
READ DATA
(LOW BYTE)
t
XLOL
t
OLDV
DATA (Low Byte)
Figure 26-5
(1)
AT90PWM2/3/2B/3B
READ DATA
(HIGH BYTE)
t
BVDV
t
OHDZ
DATA (High Byte)
(i.e., t , t , and t
DVXH XHXL
= 5V ± 10%
CC
Min. Typ.
11.5
67
200
150
67
0
0
150
67
150
67
67
67
67
150
0
3.7
(2)
7.5
LOAD ADDRESS
(LOW BYTE)
ADDR1 (Low Byte)
) also apply to
XLDX
Max. Units
12.5 V
μA
250
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
1
5 ms
10 ms
309