Table of Contents
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Features
®
•
Utilizes the AVR
RISC Architecture
•
AVR – High-performance and Low-power RISC Architecture
– 89 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Up to 12 MIPS Throughput at 12 MHz
•
Data and Non-volatile Program Memory
– 1K Byte of In-System Programmable Flash
Endurance: 1,000 Write/Erase Cycles
– 64 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
•
Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
– SPI Serial Interface for In-System Programming
•
Special Microcontroller Features
– Low-power Idle and Power-down Modes
– External and Internal Interrupt Sources
– Selectable On-chip RC Oscillator for Zero External Components
•
Specifications
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation
•
Power Consumption at 4 MHz, 3V, 25°C
– Active: 2.0 mA
– Idle Mode: 0.4 mA
– Power-down Mode: <1 µA
•
I/O and Packages
– 15 Programmable I/O Lines
– 20-pin PDIP, SOIC and SSOP
•
Operating Voltages
– 2.7 - 6.0V (AT90S1200-4)
– 4.0 - 6.0V (AT90S1200-12)
•
Speed Grades
– 0 - 4 MHz, (AT90S1200-4)
– 0 - 12 MHz, (AT90S1200-12)
Pin Configuration
8-bit
Microcontroller
with 1K Byte
of In-System
Programmable
Flash
AT90S1200
Rev. 0838H–AVR–03/02
1
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Table of Contents
Related Manuals for Atmel AVR AT90S1200
Summary of Contents for Atmel AVR AT90S1200
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Page 1: Table Of Contents Features
Features ® • Utilizes the AVR RISC Architecture • AVR – High-performance and Low-power RISC Architecture – 89 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Up to 12 MIPS Throughput at 12 MHz •... -
Page 2: Description
Description The AT90S1200 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the AT90S1200 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with the 32 general purpose working reg- isters. -
Page 3: Pin Descriptions
SPI serial interface or by a conventional nonvolatile memory programmer. By combining an enhanced RISC 8-bit CPU with In-System Pro- grammable Flash on a monolithic chip, the Atmel AT90S1200 is a powerful microcontroller that provides a highly flexible and cost-effective solution to many embed- ded control applications. -
Page 4: On-Chip Rc Oscillator
Figure 2. Oscillator Connections MAX 1 HC BUFFER XTAL2 XTAL1 Note: When using the MCU Oscillator as a clock for an external device, an HC buffer should be connected as indicated in the figure. Figure 3. External Clock Drive Configuration On-chip RC Oscillator An On-chip RC Oscillator running at a fixed frequency of 1 MHz can be selected as the MCU clock source. -
Page 5: Architectural Overview
AT90S1200 Architectural The fast-access register file concept contains 32 x 8-bit general purpose working regis- ters with a single clock cycle access time. This means that during one single clock cycle, Overview one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from the register file, the operation is executed, and the result is stored back in the register file –... -
Page 6: General Purpose Register File
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the stack. The stack is a 3-level-deep hardware stack dedicated for subrou- tines and interrupts. The I/O memory space contains 64 addresses for CPU peripheral functions such as Control Registers, Timer/Counters, A/D Converters and other I/O functions. -
Page 7: Program And Data Addressing Modes
AT90S1200 Program and Data The AT90S1200 AVR RISC Microcontroller supports powerful and efficient addressing modes. This section describes the different addressing modes supported in the Addressing Modes AT90S1200. In the figures, OP means the operation code part of the instruction word. To simplify, not all figures show the exact location of the addressing bits. -
Page 8: Subroutine And Interrupt Hardware Stack
Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd). I/O Direct Figure 9. I/O Direct Addressing Operand address is contained in 6 bits of the instruction word. n is the destination or source register address. -
Page 9: Eeprom Data Memory
AT90S1200 EEPROM Data Memory The AT90S1200 contains 64 bytes of data EEPROM memory. It is organized as a sepa- rate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described on page 25 specifying the EEPROM address register, the EEPROM data register, and the EEPROM control register. -
Page 10: I/O Memory
I/O Memory The I/O space definition of the AT90S1200 is shown in the following table. Table 1. The AT90S1200 I/O Space Address Hex Name Function SREG Status REGister GIMSK General Interrupt MaSK register TIMSK Timer/Counter Interrupt MaSK register TIFR Timer/Counter Interrupt Flag register MCUCR MCU general Control Register TCCR0... - Page 11 AT90S1200 Status Register – SREG The AVR status register (SREG) at I/O space location $3F is defined as: SREG Read/Write Initial Value • Bit 7 – I: Global Interrupt Enable The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers.
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Page 12: Reset And Interrupt Handling
Reset and Interrupt The AT90S1200 provides three different interrupt sources. These interrupts and the separate reset vector, each have a separate program vector in the program memory Handling space. All the interrupts are assigned individual enable bits that must be set (one) together with the I-bit in the Status Register in order to enable the interrupt. - Page 13 AT90S1200 Figure 13. Reset Logic Power-on Reset Circuit 100 - 500K Reset Circuit RESET Watchdog Timer Time-out On-chip 14-stage Ripple Counter RC Oscillator Table 3. Reset Characteristics (V = 5.0V) Symbol Parameter Units Power-on Reset Threshold Voltage (rising) Power-on Reset Threshold Voltage (falling) Pin Threshold Voltage –...
- Page 14 been applied, the Power-on Reset period can be extended. Refer to Figure 15 for a tim- ing example on this. Figure 15. MCU Start-up, RESET Controlled Externally RESET TOUT TIME-OUT INTERNAL RESET External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running.
- Page 15 AT90S1200 Figure 17. Watchdog Reset during Operation Interrupt Handling The AT90S1200 has two Interrupt Mask Control Registers: the GIMSK (General Inter- rupt Mask Register) at I/O space address $3B and the TIMSK (Timer/Counter Interrupt Mask Register) at I/O address $39. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all inter- rupts are disabled.
- Page 16 • Bit 6 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bit 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or low level sensed.
- Page 17 AT90S1200 External Interrupts The External Interrupt is triggered by the INT0 pin. The interrupt can trigger on rising edge, falling edge or low level. This is set up as described in the specification for the MCU Control Register (MCUCR). When INT0 is level triggered, the interrupt is pending as long as INT0 is held low.
- Page 18 MCU Control Register The MCU Control Register contains general microcontroller control bits for general MCU – MCUCR control functions. – – – – ISC01 ISC00 MCUCR Read/Write Initial Value • Bits 7, 6 – Res: Reserved Bits These bits are reserved bits in the AT90S1200 and always read as zero. •...
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Page 19: Sleep Modes
AT90S1200 Sleep Modes To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruc- tion must be executed. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU awakes, executes the interrupt routine, and resumes execution from the instruction following SLEEP. -
Page 20: Timer/Counter0
Timer/Counter0 Th e A T90 S 12 00 pr o v id e s o ne ge ne r al pu r p os e 8 - bi t Ti m er / Co un te r . Th e Timer/Counter0 gets the prescaled clock from the 10-bit prescaling timer. - Page 21 AT90S1200 Figure 19. Timer/Counter0 Block Diagram The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK or an external pin. In addition it can be stopped as described in the specification for the Timer/Counter0 Control Register (TCCR0). The overflow status flag is found in the Timer/Counter Interrupt Flag Register (TIFR).
- Page 22 • Bits 2, 1, 0 – CS02, CS01, CS00: Clock Select0, Bits 2, 1 and 0 The Clock Select0 bits 2, 1 and 0 define the prescaling source of Timer/Counter0. Table 5. Clock 0 Prescale Select CS02 CS01 CS00 Description Stop, the Timer/Counter0 is stopped.
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Page 23: Watchdog Timer
AT90S1200 Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator that runs at 1 MHz. This is the typical value at V = 5V. See characterization data for typical values at other levels. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted, see Table 6 for a detailed description. - Page 24 Table 6. Watchdog Timer Prescale Select Number of WDT Typical Time-out Typical Time-out WDP2 WDP1 WDP0 Oscillator Cycles at V = 3.0V at V = 5.0V 16K cycles 47 ms 15 ms 32K cycles 94 ms 30 ms 64K cycles 0.19 s 60 ms 128K cycles...
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Page 25: Eeprom Read/Write Access
AT90S1200 EEPROM Read/Write The EEPROM access registers are accessible in the I/O space. Access The write access time is in the range of 2.5 - 4 ms, depending on the V voltages. A self-timing function, however, lets the user software detect when the next byte can be written. -
Page 26: Prevent Eeprom Corruption
• Bit 1 – EEWE: EEPROM Write Enable The EEPROM Write Enable Signal (EEWE) is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. -
Page 27: Analog Comparator
AT90S1200 Analog Comparator The Analog Comparator compares the input values on the positive input PB0 (AIN0) and the negative input PB1 (AIN1). When the voltage on the positive input PB0 (AIN0) is higher than the voltage on the negative input PB1 (AIN1), the Analog Comparator Out- put (ACO) is set (one). - Page 28 • Bit 3 – ACIE: Analog Comparator Interrupt Enable When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the Ana- log Comparator Interrupt is activated. When cleared (zero), the interrupt is disabled. •...
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Page 29: I/O Ports
AT90S1200 I/O Ports All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without uninten- tionally changing the direction of any other pin with the SBI and CBI instructions. The same applies for changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). - Page 30 Port B as General Digital I/O All eight pins in Port B have equal functionality when used as digital I/O pins. PBn, General I/O pin: The DDBn bit in the DDRB Register selects the direction of this pin, if DDBn is set (one), PBn is configured as an output pin. If DDBn is cleared (zero), PBn is configured as an input pin.
- Page 31 AT90S1200 Port B Schematics Note that all port pins are synchronized. The synchronization latches are, however, not shown in the figures. Figure 22. Port B Schematic Diagram (Pins PB0 and PB1) 0838H–AVR–03/02...
- Page 32 Figure 23. Port B Schematic Diagram (Pins PB2, PB3, and PB4) Figure 24. Port B Schematic Diagram (Pin PB5) AT90S1200 0838H–AVR–03/02...
- Page 33 AT90S1200 Figure 25. Port B Schematic Diagram (Pin PB6) Figure 26. Port B Schematic Diagram (Pin PB7) 0838H–AVR–03/02...
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Page 34: Port D
Port D Three I/O memory address locations are allocated for Port D, one each for the Data Register – PORTD ($12), Data Direction Register – DDRD ($11), and the Port D Input Pins – PIND ($10). The Port D Input Pins address is read-only, while the Data Register and the Data Direction Register are read/write. - Page 35 AT90S1200 Table 11. DDDn Bits’ Effect on Port D Pins DDDn PORTDn Pull-up Comment Input Tri-state (High-Z) Input PDn will source current if ext. pulled low. Output Push-pull Zero Output Output Push-pull One Output Note: n: 6…0, pin number. Alternate Functions for Port D The alternate functions of Port D are: •...
- Page 36 Figure 28. Port D Schematic Diagram (Pin PD2) Figure 29. Port D Schematic Diagram (Pin PD4) PULL- RESET DDD4 RESET PORTD4 WRITE PORTD TIMER0 CLOCK SENSE CONTROL WRITE DDRD SOURCE MUX READ PORTD LATCH READ PORTD PIN READ DDRD CS00 CS02 CS01 AT90S1200...
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Page 37: Memory Programming
Fuse bits is not affected by Chip Erase. Signature Bytes All Atmel microcontrollers have a 3-byte signature code that identifies the device. This code can be read in both Serial and Parallel modes. The three bytes reside in a sepa- rate address space. -
Page 38: Parallel Programming
the self-timed write instruction in the Serial Programming mode. During programming, the supply voltage must be in accordance with Table 13. Table 13. Supply Voltage during Programming Part Serial Programming Parallel Programming AT90S1200 2.7 - 6.0V 4.5 - 5.5V Parallel Programming This section describes how to parallel program and verify Flash program memory, EEPROM data memory, Lock bits and Fuse bits in the AT90S1200. - Page 39 AT90S1200 Table 15. XA1 and XA0 Coding Action when XTAL1 is Pulsed Load Flash or EEPROM Address (High or low address byte for Flash determined by BS). Load Data (High or low data byte for Flash determined by BS). Load Command No Action, Idle Table 16.
- Page 40 4. Give XTAL1 a positive pulse. This loads the command. B: Load Address High Byte 1. Set XA1, XA0 to “00”. This enables address loading. 2. Set BS to “1”. This selects high byte. 3. Set DATA = Address high byte ($00 - $01). 4.
- Page 41 AT90S1200 Figure 31. Programming the Flash Waveforms DATA ADDR. HIGH ADDR.LOW DATA LOW XTAL1 RDY/BSY RESET Figure 32. Programming the Flash Waveforms (Continued) DATA DATA HIGH XTAL1 RDY/BSY RESET +12V Reading the Flash The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash”...
- Page 42 Programming the EEPROM The programming algorithm for the EEPROM data memory is as follows (refer to “Pro- gramming the Flash” for details on command, address and data loading): 1. A: Load Command “0001 0001”. 2. C: Load Address Low Byte ($00 - $3F). 3.
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Page 43: Parallel Programming Characteristics
AT90S1200 Reading the Signature Bytes The algorithm for reading the signature bytes is as follows (refer to “Programming the Flash” on page 39 for details on command and address loading): 1. A: Load Command “0000 1000”. 2. C: Load Address Low Byte ($00 - $02). Set OE to “0”, and BS to “0”. -
Page 44: Serial Downloading
Serial Downloading Both the program and data memory arrays can be programmed using the SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output) (see Figure 34). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase instructions can be executed. - Page 45 AT90S1200 3. If a Chip Erase is performed (must be done to erase the Flash), wait t WD_ERASE after the instruction, give RESET a positive pulse, and start over from step 2. See Table 21 on page 47 for t value.
- Page 46 Figure 35. Serial Programming Waveforms Table 19. Serial Programming Instruction Set for AT90S1200 Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte4 Operation Programming Enable serial programming while RESET is low. 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Chip Erase Chip erase both Flash and EEPROM memory...
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Page 47: Serial Programming Characteristics
AT90S1200 Serial Programming Figure 36. Serial Programming Timing Characteristics MOSI SLSH OVSH SHOX SHSL MISO SLIV = -40 ° C to 85 ° C, V Table 20. Serial Programming Characteristics, T = 2.7 - 6.0V (unless otherwise noted) Symbol Parameter Units Oscillator Frequency (V = 2.7 - 4.0V) -
Page 48: Electrical Characteristics
Electrical Characteristics Absolute Maximum Ratings* *NOTICE: Stresses beyond those listed under “Absolute Operating Temperature........-55°C to +125°C Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and Storage Temperature ........-65°C to +150°C functional operation of the device at these or Voltage on Any Pin Except RESET other conditions beyond those indicated in the... - Page 49 AT90S1200 DC Characteristics = -40×C to 85×C, V = 2.7V to 6.0V (unless otherwise noted) (Continued) Symbol Parameter Condition Units Analog Comparator = 5V 40.0 ACIO Input Offset Voltage Analog Comparator = 5V -50.0 50.0 ACLK Input Leakage Current Analog Comparator = 2.7V 750.0 ACPD...
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Page 50: External Clock Drive Waveforms
External Clock Drive Figure 37. External Clock Drive Waveforms VIH1 VIL1 External Clock Drive Table 23. External Clock Drive = 2.7V to 4.0V = 4.0V to 6.0V Symbol Parameter Units Oscillator Frequency 12.0 CLCL Clock Period 250.0 83.3 CLCL High Time 100.0 33.3 CHCX... -
Page 51: Typical Characteristics
AT90S1200 Typical The following charts show typical behavior. These figures are not tested during manu- facturing. All current consumption measurements are performed with all I/O pins Characteristics configured as inputs and with internal pull-ups enabled. A sine wave generator with rail- to-rail output is used as clock source. - Page 52 Figure 39. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs. V FREQUENCY = 4 MHz T = -40 ˚ T = 25 ˚ T = 85 ˚ Figure 40. Active Supply Current vs. V , Device Clocked by Internal Oscillator ACTIVE SUPPLY CURRENT vs.
- Page 53 AT90S1200 Figure 41. Idle Supply Current vs. Frequency IDLE SUPPLY CURRENT vs. FREQUENCY T = 25˚C = 6V = 5.5V = 5V = 4.5V = 4V = 3.6V = 3.3V = 3.0V = 2.7V Frequency (MHz) Figure 42. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs.
- Page 54 Figure 43. Idle Supply Current vs. V , Device Clocked by Internal Oscillator IDLE SUPPLY CURRENT vs. V DEVICE CLOCKED BY INTERNAL RC OSCILLATOR T = 25 ˚ 0.35 T = 85 ˚ 0.25 0.15 0.05 Figure 44. Power-down Supply Current vs. V , Watchdog Timer Disabled POWER DOWN SUPPLY CURRENT vs.
- Page 55 AT90S1200 Figure 45. Power-down Supply Current vs. V , Watchdog Timer Enabled POWER DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ENABLED T = 25 ˚ T = 85 ˚ Figure 46. Internal RC Oscillator Frequency vs. V INTERNAL RC OSCILLATOR FREQUENCY vs. V 1600 T = 25 ˚...
- Page 56 Figure 47. Analog Comparator Current vs. V ANALOG COMPARATOR CURRENT vs. V T = -40 ˚ T = 25 ˚ T = 85 ˚ Note: Analog comparator offset voltage is measured as absolute offset. Figure 48. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs.
- Page 57 AT90S1200 Figure 49. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE V = 2.7V T = 25 ˚ T = 85 ˚ Common Mode Voltage (V) Figure 50. Analog Comparator Input Leakage Current ANALOG COMPARATOR INPUT LEAKAGE CURRENT V = 6V T = 25...
- Page 58 Note: Sink and source capabilities of I/O ports are measured on one pin at a time. Figure 51. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE V = 5V T = 25 ˚ T = 85 ˚...
- Page 59 AT90S1200 Figure 53. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE V = 5V T = 25 ˚ T = 85 ˚ Figure 54. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE V = 5V T = 25 ˚...
- Page 60 Figure 55. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE V = 2.7V T = 25 ˚ T = 85 ˚ Figure 56. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE V = 2.7V T = 25 ˚...
- Page 61 AT90S1200 Note: Input threshold is measured at the center point of the hysteresis. Figure 57. I/O Pin Input Threshold Voltage vs. V I/O PIN INPUT THRESHOLD VOLTAGE vs. V T = 25 ˚ Figure 58. I/O Pin Input Hysteresis vs. V I/O PIN INPUT HYSTERESIS vs.
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Page 62: At90S1200 Register Summary
AT90S1200 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page SREG page 11 Reserved Reserved Reserved GIMSK INT0 page 15 Reserved TIMSK TOIE0 page 16 TIFR TOV0 page 16 Reserved Reserved MCUCR... -
Page 63: Instruction Set Summary
AT90S1200 Instruction Set Summary Mnemonic Operands Description Operation Flags # Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ← Rd, Rr Add Two Registers Rd + Rr Z,C,N,V,H ← Rd, Rr Add with Carry Two Registers Rd + Rr + C Z,C,N,V,H ← Rd, Rr Subtract Two Registers Rd - Rr... - Page 64 Instruction Set Summary (Continued) Mnemonic Operands Description Operation Flags # Clocks BIT AND BIT-TEST INSTRUCTIONS ← P, b Set Bit in I/O Register I/O(P,b) None ← P, b Clear Bit in I/O Register I/O(P,b) None ← ← Logical Shift Left Rd(n+1) Rd(n), Rd(0) Z,C,N,V...
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Page 65: Ordering Information
AT90S1200 Ordering Information Speed (MHz) Power Supply Ordering Code Package Operation Range 2.7 - 6.0V AT90S1200-4PC 20P3 Commercial AT90S1200-4SC (0°C to 70°C) AT90S1200-4YC AT90S1200-4PI 20P3 Industrial AT90S1200-4SI (-40°C to 85°C) AT90S1200-4YI 4.0 - 6.0V AT90S1200-12PC 20P3 Commercial AT90S1200-12SC (0°C to 70°C) AT90S1200-12YC AT90S1200-12PI 20P3... -
Page 66: Packaging Information
Packaging Information 20P3 SEATING PLANE COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL NOTE – – 5.334 0.381 – – 25.984 – 25.493 Note 2 7.620 – 8.255 6.096 – 7.112 Note 2 0.356 – 0.559 1.270 – 1.551 Notes: 1. - Page 67 AT90S1200 20S, 20-lead, Plastic Gull Wing Small Outline (SOIC), 0.300" body. Dimensions in Millineters and (Inches)* JEDEC STANDARD MS-013 0.51(0.020) 0.33(0.013) 10.65 (0.419) 7.60 (0.2992) 10.00 (0.394) 7.40 (0.2914) PIN 1 ID PIN 1 1.27 (0.050) BSC 13.00 (0.5118) 2.65 (0.1043) 12.60 (0.4961) 2.35 (0.0926) 0.30(0.0118)
- Page 68 20Y, 20-lead Plastic Shrink Small Outline (SSOP), 5.3mm body Width. Dimensions in Millimeters and (inches)* 0.38 (0.015) 0.25 (0.010) 5.38 (0.212) 7.90 (0.311) 5.20 (0.205) 7.65 (0.301) PIN 1 ID PIN 1 0.65 (0.0256) BSC 7.33 (0.289) 1.99 (0.078) 7.07 (0.278) 1.73 (0.068) 0.21 (0.008) 0.05 (0.002)
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Page 69: Table Of Contents
AT90S1200 Table of Contents Features....................1 Pin Configuration.................. 1 Description .................... 2 Block Diagram ...................... 2 Pin Descriptions....................3 Crystal Oscillator....................3 On-chip RC Oscillator ................... 4 Architectural Overview................. 5 General Purpose Register File ................6 ALU – Arithmetic Logic Unit.................. 6 In-System Programmable Flash Program Memory .......... - Page 70 Electrical Characteristics..............48 Absolute Maximum Ratings*................48 DC Characteristics....................48 External Clock Drive Waveforms ................ 50 External Clock Drive ................... 50 Typical Characteristics ..............51 AT90S1200 Register Summary............62 Instruction Set Summary ..............63 Ordering Information ............... 65 Packaging Information ............... 66 20P3 ........................
- Page 71 No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems.
- Page 72 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Atmel AT90S1200-12SC AT90S1200A-4YI AT90S1200A-4SI AT90S1200A-12PC AT90S1200A-4PC...
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