Clock Output Buffer; System Clock Prescaler - Atmel AT90PWM2 Manual

7.9

Clock Output Buffer

7.10

System Clock Prescaler

AT90PWM2/3/2B/3B
38
Figure 7-6. External Clock Drive Configuration
Table 7-10. External Clock Frequency
CKSEL3..0
0000
When this clock source is selected, start-up times are determined by the SUT Fuses as shown in
Table 7-11.
Table 7-11. Start-up Times for the External Clock Selection
Start-up Time from Power-
SUT1..0 down and Power-save
00
01
10
11
When applying an external clock, it is required to avoid sudden changes in the applied clock fre-
quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from
one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the
MCU is kept in Reset during such changes in the clock frequency.
Note that the System Clock Prescaler can be used to implement run-time changes of the internal
clock frequency while still ensuring stable operation. Refer to
38 for details.
When the CKOUT Fuse is programmed, the system Clock will be output on CLKO. This mode is
suitable when chip clock is used to drive other circuits on the system. The clock will be output
also during reset and the normal operation of I/O pin will be overridden when the fuse is pro-
grammed. Any clock source, including internal RC Oscillator, can be selected when CLKO
serves as clock output. If the System Clock Prescaler is used, it is the divided system clock that
is output (CKOUT Fuse programmed).
The AT90PWM2/2B/3/3B system clock can be divided by setting the Clock Prescale Register –
CLKPR. This feature can be used to decrease power consumption when the requirement for
processing power is low. This can be used with all clock source options, and it will affect the
clock frequency of the CPU and all synchronous peripherals. clk
are divided by a factor as shown in
NC
External
Clock
Signal
Frequency Range
0 - 16 MHz
Additional Delay from
Reset (V
6 CK
6 CK
6 CK
Reserved
Table 7-12.
XTAL2
XTAL1
GND
= 5.0V) Recommended Usage
CC
14CK BOD enabled
14CK + 4.1 ms Fast rising power
14CK + 65 ms Slowly rising power
"System Clock Prescaler" on page
, clk
I/O ADC
, clk , and clk
CPU FLASH
4317I–AVR–01/08