Atmel AT90PWM2 Manual page 35

AT90PWM2/3/2B/3B
36
Table 7-9. Start-up Times when the PLL is selected as system clock
CKSEL
3..0 SUT1..0
00
01
0101
Ext Osc
10
11
00
01
0001
Ext Clk
10
11
1. This value do not provide a proper restart ; do not use PD in this clock scheme
2. This value do not provide a proper restart ; do not use PD in this clock scheme
3. This value do not provide a proper restart ; do not use PD in this clock scheme
Figure 7-4. PCK Clocking System AT90PWM2/3
OSCCAL
RC OSCILLATOR 8 MHz
XTAL1
OSCILLATORS
XTAL2
Start-up Time from Power-down
and Power-save
1K CK
1K CK
16K CK
16K CK
(1)
6 CK
(2)
6 CK
(3)
6 CK
PLLE
DIVIDE PLL
BY 8 64x
Additional Delay from Reset
(V
CC
14CK
14CK + 4 ms
14CK + 4 ms
14CK + 64 ms
14CK
14CK + 4 ms
14CK + 64 ms
Reserved
PLLF
Lock PLOCK
Detector
CLK
PLL
DIVIDE
BY 2
DIVIDE
BY 4
CK
= 5.0V)
SOURCE
4317I–AVR–01/08