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Features
®
•
Utilizes the AVR
RISC Architecture
•
AVR – High-performance and Low-power RISC Architecture
– 118 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General-purpose Working Registers
– Up to 10 MIPS Throughput at 10 MHz
•
Data and Nonvolatile Program Memory
– 2K Bytes of In-System Programmable Flash
Endurance: 1,000 Write/Erase Cycles
– 128 Bytes Internal RAM
– 128 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
•
Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler
– Programmable Watchdog Timer with On-chip Oscillator
– SPI Serial Interface for In-System Programming
•
Special Microcontroller Features
– Low-power Idle and Power-down Modes
– External and Internal Interrupt Sources
– Power-on Reset Circuit
– Selectable On-chip RC Oscillator
•
Specifications
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation
•
Power Consumption at 4 MHz, 3V, 25°C
– Active: 2.4 mA
– Idle Mode: 0.5 mA
– Power-down Mode: <1 µA
•
I/O and Packages
– Three Programmable I/O Lines for AT90S/LS2323
– Five Programmable I/O Lines for AT90S/LS2343
– 8-pin PDIP and SOIC
•
Operating Voltages
– 4.0 - 6.0V for AT90S2323/AT90S2343
– 2.7 - 6.0V for AT90LS2323/AT90LS2343
•
Speed Grades
– 0 - 10 MHz for AT90S2323/AT90S2343-10
– 0 - 4 MHz for AT90LS2323/AT90LS2343-4
– 0 - 1 MHz for AT90LS2343-1
Pin Configuration
RESET
1
(CLOCK) PB3
2
PB4
3
GND
4
AT90S/LS2343
PDIP/SOIC
8
VCC
RESET
7
PB2 (SCK/T0)
XTAL1
6
PB1 (MISO/INT0)
XTAL2
5
PB0 (MOSI)
GND
1
8
VCC
2
7
PB2 (SCK/T0)
3
6
PB1 (MISO/INT0)
4
5
PB0 (MOSI)
AT90S/LS2323
8-bit
Microcontroller
with 2K Bytes of
In-System
Programmable
Flash
AT90S2323
AT90LS2323
AT90S2343
AT90LS2343
Rev. 1004D–09/01
1
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Summary of Contents for Atmel AVR AT90S2323
- Page 1 Features ® • Utilizes the AVR RISC Architecture • AVR – High-performance and Low-power RISC Architecture – 118 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General-purpose Working Registers – Up to 10 MIPS Throughput at 10 MHz •...
- Page 2 Description The AT90S/LS2323 and AT90S/LS2343 are low-power, CMOS, 8-bit microcontrollers based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the AT90S2323/2343 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general-purpose working regis- ters.
- Page 3 Power-down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On-chip Flash allows the program memory to be reprogrammed in-system through an SPI serial interface.
- Page 4 Atmel AT90S2323/2343 is a powerful microcontroller that provides a highly flexible and cost-effective solution to many embedded control applications. The AT90S2323/2343 AVR is supported with a full suite of program and system devel- opment tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators and evaluation kits.
- Page 5 AT90S/LS2323/2343 Pin Descriptions AT90S/LS2343 Supply voltage pin. Ground pin. Port B (PB4..PB0) Port B is a 5-bit bi-directional I/O port with internal pull-up resistors. The Port B output buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low, will source current if the pull-up resistors are activated.
- Page 6 Figure 4. External Clock Drive Configuration AT90S/LS2343 AT90S/LS2323 XTAL2 EXTERNAL EXTERNAL OSCILATOR OSCILATOR XTAL1 SIGNAL SIGNAL AT90S/LS2323/2343 1004D–09/01...
- Page 7 AT90S/LS2323/2343 Architectural The fast-access register file concept contains 32 x 8-bit general-purpose working regis- ters with a single clock cycle access time. This means that during one single clock cycle, Overview one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from the register file, the operation is executed and the result is stored back in the register file –...
- Page 8 The AVR has Harvard architecture – with separate memories and buses for program and data. The program memory is accessed with a two-stage pipeline. While one instruction is being executed, the next instruction is pre-fetched from the program mem- ory. This concept enables instructions to be executed in every clock cycle. The program memory is in-system downloadable Flash memory.
- Page 9 AT90S/LS2323/2343 General-purpose Figure 7 shows the structure of the 32 general-purpose registers in the CPU. Register File Figure 7. AVR CPU General-purpose Working Registers Addr. … General Purpose Working Registers … X-register low byte X-register high byte Y-register low byte Y-register high byte Z-register low byte Z-register high byte...
- Page 10 X-register, Y-register and Z- The registers R26..R31 have some added functions to their general-purpose usage. register These registers are the address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y, and Z, are defined in Figure 8. Figure 8.
- Page 11 AT90S/LS2323/2343 SRAM Data Memory Figure 9 shows how the AT90S2323/2343 Data Memory is organized. Figure 9. SRAM Organization Register File Data Address Space … … I/O Registers … … Internal SRAM … The 224 data memory locations address the Register file, I/O memory and the data SRAM.
- Page 12 Program and Data The AT90S2323/2343 AVR RISC microcontroller supports powerful and efficient Addressing Modes addressing modes for access to the program memory (Flash) and data memory. This section describes the different addressing modes supported by the AVR architecture. In the figures, OP means the operation code part of the instruction word. To simplify, not all figures show the exact location of the addressing bits.
- Page 13 AT90S/LS2323/2343 I/O Direct Figure 12. I/O Direct Addressing Operand address is contained in six bits of the instruction word. n is the destination or source register address. Data Direct Figure 13. Direct Data Addressing A 16-bit data address is contained in the 16 LSBs of a 2-word instruction. Rd/Rr specify the destination or source register.
- Page 14 Data Indirect Figure 15. Data Indirect Addressing Operand address is the contents of the X-, Y-, or the Z-register. Data Indirect with Pre- Figure 16. Data Indirect Addressing with Pre-decrement decrement The X-, Y-, or the Z-register is decremented before the operation. Operand address is the decremented contents of the X-, Y-, or the Z-register.
- Page 15 AT90S/LS2323/2343 Constant Addressing Using Figure 18. Code Memory Constant Addressing the LPM Instruction Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 1K), the LSB selects low byte if cleared (LSB = 0) or high byte if set (LSB = Indirect Program Addressing, Figure 19.
- Page 16 Memory Access and This section describes the general access timing concepts for instruction execution and Instruction Execution internal memory access. Timing The AVR CPU is driven by the System Clock Ø, directly generated from the external clock signal applied to the CLOCK pin. No internal clock division is used. Figure 21.
- Page 17 AT90S/LS2323/2343 Figure 23. On-chip Data SRAM Access Cycles System Clock Ø Address Prev. Address Address Data Data I/O Memory The I/O space definition of the AT90S2323/2343 is shown in Table 2. Table 2. AT90S2323/2343 I/O Space Address Hex Name Function $3F ($5F) SREG Status REGister...
- Page 18 and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O registers as SRAM, $20 must be added to these addresses. All I/O register addresses throughout this document are shown with the SRAM address in parentheses. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.
- Page 19 AT90S/LS2323/2343 • Bit 0 – C: Carry Flag The carry flag C indicates a carry in an arithmetical or logical operation. See the Instruc- tion Set description for detailed information. Note that the Status Register is not automatically stored when entering an interrupt rou- tine and restored when returning from an interrupt routine.
- Page 20 The most typical program setup for the Reset and Interrupt vector addresses are: Address Labels Code Comments $000 rjmp RESET ; Reset Handler $001 rjmp EXT_INT0 ; IRQ0 Handler $002 rjmp TIM_OVF0 ; Timer0 Overflow ; Handler; $003 MAIN: ldi r16, low(RAMEND) ;...
- Page 21 AT90S/LS2323/2343 Table 4. Reset Characteristics (V = 5.0V) Symbol Parameter Units Power-on Reset Threshold Voltage, rising Power-on Reset Threshold Voltage, falling RESET Pin Threshold Voltage 0.6 V Reset Delay Time-out Period AT90S/LS2323 TOUT FSTRT Programmed Reset Delay Time-out Period AT90S/LS2323 11.0 16.0 21.0...
- Page 22 Figure 25. MCU Start-up, RESET Tied to V RESET TOUT TIME-OUT INTERNAL RESET Figure 26. MCU Start-up, RESET Controlled Externally RESET TOUT TIME-OUT INTERNAL RESET External Reset An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running.
- Page 23 AT90S/LS2323/2343 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of 1 CPU clock cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t . Refer to page 30 for details on operation of the Watchdog. TOUT Figure 28.
- Page 24 Table 8. Reset Source Identification PORF EXTRF Reset Source Watchdog Reset External Reset Power-on Reset Power-on Reset Interrupt Handling The AT90S2323/2343 has two 8-bit interrupt mask control registers; GIMSK (General Interrupt Mask register) and TIMSK (Timer/Counter Interrupt Mask register). When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all inter- rupts are disabled.
- Page 25 AT90S/LS2323/2343 General Interrupt Flag Register – GIFR $3A ($5A) – INTF0 – – – – – – GIFR Read/Write Initial Value • Bit 7 – Res: Reserved Bit This bit is a reserved bit in the AT90S2323/2343 and always reads as zero. •...
- Page 26 • Bit 0 – Res: Reserved Bit This bit is a reserved bit in the AT90S2323/2343 and always reads zero. External Interrupt The external interrupt is triggered by the INT0 pin. Observe that, if enabled, the interrupt will trigger even if the INT0 pin is configured as an output. This feature provides a way of generating a software interrupt.
- Page 27 AT90S/LS2323/2343 activate the interrupt are defined in Table 9. The value on the INT01 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt.
- Page 28 Timer/Counter The AT90S2323/2343 provides one general-purpose 8-bit Timer/Counter – Timer/Counter0. The Timer/Counter has prescaling selection from the 10-bit prescaling timer. The Timer/Counter can be used either as a timer with an internal clock time base or as a counter with an external pin connection that triggers the counting. Timer/Counter Prescaler Figure 29 shows the Timer/Counter prescaler.
- Page 29 AT90S/LS2323/2343 Figure 30. Timer/Counter 0 Block Diagram Timer/Counter0 Control Register – TCCR0 $33 ($53) – – – – – CS02 CS01 CS00 TCCR0 Read/Write Initial Value • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the AT90S2323/2343 and always read zero. •...
- Page 30 The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from the CK oscillator clock. If the external pin modes are used for Timer/Counter0, transitions on PB2/(T0) will clock the counter even if the pin is configured as an output.
- Page 31 AT90S/LS2323/2343 Watchdog Timer Control Register – WDTCR $21 ($41) – – – WDTOE WDP2 WDP1 WDP0 WDTCR Read/Write Initial Value • Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the AT90S2323/2343 and will always read as zero. •...
- Page 32 EEPROM Read/Write The EEPROM access registers are accessible in the I/O space. Access The write access time is in the range of 2.5 - 4 ms, depending on the V voltages. A self-timing function, however, lets the user software detect when the next byte can be written.
- Page 33 AT90S/LS2323/2343 EEPROM Control Register – EECR $1C ($3C) – – – – – EEMWE EEWE EERE EECR Read/Write Initial Value • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the AT90S2323/2343 and will always read as zero. •...
- Page 34 Prevent EEPROM During periods of low V , the EEPROM data can be corrupted because the supply volt- Corruption age is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using the EEPROM and the same design solutions should be applied.
- Page 35 AT90S/LS2323/2343 I/O Port B All AVR ports have true read-modify-write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintention- ally changing the direction of any other pin with the SBI and CBI instructions. The same applies for changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
- Page 36 Port B Input Pins Address – PINB $16 ($36) – – – PINB4 PINB3 PINB2 PINB1 PINB0 PINB Read/Write Initial Value The Port B Input Pins address (PINB) is not a register and this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read and when reading PINB, the logical values present on the pins are read.
- Page 37 RC oscillator as the MCU source. The status of the Fuse bits is not affected by Chip Erase. Signature Bytes All Atmel microcontrollers have a three-byte signature code that identifies the device. The three bytes reside in a separate address space. (Note:)
- Page 38 Serial mode. Reading the signature bytes will return: $00, $01 and $02. Programming the Flash Atmel’s AT90S2323/2343 offers 2K bytes of In-System Programmable Flash program memory and 128 bytes of EEPROM data memory. and EEPROM The AT90S2323/2343 is shipped with the On-chip Flash program and EEPROM data memory arrays in the erased state (i.e., contents = $FF) and ready to be programmed.
- Page 39 AT90S/LS2323/2343 High-voltage Serial To program and verify the AT90S/LS2323 and AT90S/LS234 in the high-voltage Serial Programming Algorithm Programming mode, the following sequence is recommended (see instruction formats in Table 16): 1. Power-up sequence: Apply 4.5 - 5.5V between V and GND. Set RESET and PB0 to “0”...
- Page 40 Table 16. High-voltage Serial Programming Instruction Set Instruction Format Instruction Instr.1 Instr.2 Instr.3 Instr.4 Operation Remarks 0_1000_0000_00 0_0000_0000_00 0_0000_0000_00 0_0000_0000_00 Wait t after Instr.3 for WLWH_CE 0_0110_0100_00 0_0110_1100_00 0_0100_1100_00 Chip Erase 0_0100_1100_00 the Chip Erase cycle to finish. x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxxx_xxxx_xx 0_0001_0000_00...
- Page 41 AT90S/LS2323/2343 Table 16. High-voltage Serial Programming Instruction Set (Continued) Instruction Format Instruction Instr.1 Instr.2 Instr.3 Instr.4 Operation Remarks Read Fuse 0_0000_0100_00 0_0000_0000_00 0_0000_0000_00 Reading 1, 2, S, R = “0” means and Lock Bits 0_0100_1100_00 0_0111_1000_00 0_0111_1100_00 the Fuse/Lock bit is (AT90S/ programmed.
- Page 42 High-voltage Serial Programming Characteristics Figure 34. High-voltage Serial Programming Timing SDI (PB0), SII (PB1) SLSH IVSH SHIX SCI (XTAL1/PB3) SHSL SDO (PB2) SHOV = 25 ° C ± 10%, V Table 17. High-voltage Serial Programming Characteristics, T 5.0V ± 10% (unless otherwise noted) Symbol Parameter Units...
- Page 43 AT90S/LS2323/2343 For the EEPROM, an auto-erase cycle is provided within the self-timed Write instruction and there is no need to first execute the Chip Erase instruction. The Chip Erase instruc- tion turns the content of every memory location in both the program and EEPROM arrays into $FF.
- Page 44 7. At the end of the programming session, RESET can be set high to commence normal operation. 8. Power-off sequence (if needed): Set CLOCK/XTAL1 to “0”. Set RESET to “1”. Turn V power off. Data Polling EEPROM When a byte is being programmed into the EEPROM, reading the address location being programmed will give the value P1 until the auto-erase is finished, and then the value P2 will be given.
- Page 45 AT90S/LS2323/2343 Table 19. Low-voltage Serial Programming Instruction Set AT90S2323/2343 Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte 4 Operation Programming Enable Serial programming while 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable RESET is low. Chip erase both Flash and 1010 1100 100x xxxx xxxx xxxx...
- Page 46 Low-voltage Serial Programming Characteristics Figure 37. Low-voltage Serial Programming Timing MOSI SLSH OVSH SHOX SHSL MISO SLIV = -40 ° C to 85 ° C, V Table 20. Low-voltage Serial Programming Characteristics, T 2.7 - 6.0V (unless otherwise noted) Symbol Parameter Units Oscillator Frequency (V...
- Page 47 AT90S/LS2323/2343 Electrical Characteristics Absolute Maximum Ratings* *NOTICE: Stresses beyond those listed under “Absolute Operating Temperature........-55°C to +125°C Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and Storage Temperature ........-65°C to +150°C functional operation of the device at these or other conditions beyond those indicated in the Voltage on Any Pin except RESET...
- Page 48 External Clock Drive Waveforms Figure 38. Waveforms VIH1 VIL1 External Clock Drive = -40 ° C to 85 ° C : 2.7V to 4.0V : 4.0V to 6.0V Symbol Parameter Units Oscillator Frequency 10.0 CLCL Clock Period 250.0 100.0 CLCL High Time 100.0 40.0...
- Page 49 AT90S/LS2323/2343 Typical The following charts show typical behavior. These figures are not tested during manu- facturing. All current consumption measurements are performed with all I/O pins Characteristics configured as inputs and with internal pull-ups enabled. A sine wave generator with rail- to-rail output is used as clock source.
- Page 50 Figure 40. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs. V FREQUENCY = 4 MHz T = 25 ˚ T = 85 ˚ Figure 41. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs. V DEVICE CLOCKED BY INTERNAL RC OSCILLATOR T = 25 ˚...
- Page 51 AT90S/LS2323/2343 Figure 42. Idle Supply Current vs. Frequency IDLE SUPPLY CURRENT vs. FREQUENCY T = 25˚C = 6V = 5.5V = 5V = 4.5V = 4V = 3.6V = 3.3V = 3.0V = 2.7V Frequency (MHz) Figure 43. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs.
- Page 52 Figure 44. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs. V DEVICE CLOCKED BY INTERNAL RC OSCILLATOR T = 25 ˚ T = 85 ˚ Figure 45. Power-down Supply Current vs. V POWER DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER DISABLED T = 85 ˚...
- Page 53 AT90S/LS2323/2343 Figure 46. Power-down Supply Current vs. V POWER DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ENABLED T = 85 ˚ T = 25 ˚ Figure 47. Watchdog Oscillator Frequency vs. V WATCHDOG OSCILLATOR FREQUENCY vs. V 1600 T = 25 ˚...
- Page 54 Note: Sink and source capabilities of I/O ports are measured on one pin at a time. Figure 48. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE V = 5V T = 25 ˚ T = 85 ˚...
- Page 55 AT90S/LS2323/2343 Figure 50. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE V = 5V T = 25 ˚ T = 85 ˚ Figure 51. I/O PIn Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE V = 5V T = 25 ˚...
- Page 56 Figure 52. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE V = 2.7V T = 25 ˚ T = 85 ˚ Figure 53. I/O Pin Source Current vs. Output voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE V = 2.7V T = 25 ˚...
- Page 57 AT90S/LS2323/2343 Figure 54. I/O Pin Input Threshold Voltage vs. V I/O PIN INPUT THRESHOLD VOLTAGE vs. V T = 25 ˚ Figure 55. I/O Pin Input Hysteresis vs. V I/O PIN INPUT HYSTERESIS vs. V T = 25 ˚ 0.18 0.16 0.14 0.12...
- Page 58 AT90S2323/2343 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page $3F ($5F) SREG page 18 $3E ($5E) Reserved $3D ($5D) page 19 $3C ($5C) Reserved $3B ($5B) GIMSK INT0 page 24 $3A ($5A)
- Page 59 AT90S/LS2323/2343 Instruction Set Summary Mnemonic Operands Description Operation Flags # Clocks ARITHMETIC AND LOGIC INSTRUCTIONS Rd ← Rd + Rr Rd, Rr Add Two Registers Z,C,N,V,H Rd ← Rd + Rr + C Rd, Rr Add with Carry Two Registers Z,C,N,V,H Rdh:Rdl ←...
- Page 60 Instruction Set Summary (Continued) Mnemonic Operands Description Operation Flags # Clocks DATA TRANSFER INSTRUCTIONS Rd ← Rr Rd, Rr Move between Registers None Rd ← K Rd, K Load Immediate None Rd ← (X) Rd, X Load Indirect None Rd ← (X), X ← X + 1 Rd, X+ Load Indirect and Post-inc.
- Page 61 2. In AT90LS2343-1xx, the internal RC oscillator is selected as default MCU clock source (RCEN fuse is programmed) when the device is shipped from Atmel. In AT90LS2343-4xx and AT90S2343-10xx, the default MCU clock source is the clock input pin (RCEN fuse is unprogrammed). The fuse settings can be changed by high voltage serial programming.
- Page 62 Packaging Information 8P3, 8-lead, Plastic Dual Inline Package (PDIP), 0.300" Wide. Dimensions in Millimeters and (Inches)* JEDEC STANDARD MS-001 BA 10.16(0.400) 9.017(0.355) 7.11(0.280) 6.10(0.240) .300 (7.62) REF 254(0.100) BSC 5.33(0.210) MAX Seating Plane 4.95(0.195) 3.81(0.150) 2.92(0.115) 0.381(0.015)MIN 2.92(0.115) 0.559(0.022) 0.356(0.014) 1.78(0.070) 1.14(0.045) 8.26(0.325)
- Page 63 AT90S/LS2323/2343 .020 (.508) .012 (.305) .213 (5.41) .330 (8.38) .205 (5.21) .300 (7.62) PIN 1 .050 (1.27) BSC .212 (5.38) .203 (5.16) .080 (2.03) .070 (1.78) .013 (.330) .004 (.102) .010 (.254) .007 (.178) .035 (.889) .020 (.508) 1004D–09/01...
- Page 64 No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems.