Atmel AT90PWM2 Manual page 122

15.10 16-bit Timer/Counter Register Description
15.10.1 Timer/Counter1 Control Register A – TCCR1A
4317I–AVR–01/08
Figure 15-12. Timer/Counter Timing Diagram, no Prescaling
clk
I/O
clk
Tn
(clk /1)
I/O
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOVn
(FPWM)
and ICFn
(if used
as TOP)
OCRnx
(Update at TOP)
Figure 15-13 shows the same timing data, but with the prescaler enabled.
Figure 15-13. Timer/Counter Timing Diagram, with Prescaler (f
clk
I/O
clk
Tn
(clk /8)
I/O
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOVn
(FPWM)
and ICF n
(if used
as TOP)
OCRnx
(Update at TOP)
Bit 7
COM1A1 COM1A0
Read/Write R/W
Initial Value 0
• Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A
• Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B
The COMnA1:0 and COMnB1:0 control the Output Compare pins (OCnA and OCnB respec-
tively) behavior. If one or both of the COMnA1:0 bits are written to one, the OCnA output
overrides the normal port functionality of the I/O pin it is connected to. If one or both of the
COMnB1:0 bit are written to one, the OCnB output overrides the normal port functionality of the
TOP - 1 TOP
TOP - 1 TOP
Old OCRnx Value
TOP - 1 TOP
TOP - 1
TOP
Old OCRnx Value
6 5 4
COM1B1 COM1B0
R/W R/W R/W
0 0 0
AT90PWM2/3/2B/3B
BOTTOM BOTTOM + 1
TOP - 1
New OCRnx Value
/8)
clk_I/O
BOTTOM BOTTOM + 1
TOP - 1 TOP - 2
New OCRnx Value
3 2 1
– – WGM11
R R R/W
0 0 0
TOP - 2
0
WGM10 TCCR1A
R/W
0
123