Atmel AT90PWM2 Manual page 133

16.4.2 Output Description
AT90PWM2/3/2B/3B
134
Description
Name
OCRnRB[1 Frequency Resolution Enhancement value
5:12] (Flank Width Modulation)
CLK I/O Clock Input from I/O clock
CLK PLL Clock Input from PLL
SYnIn Synchronization In (from adjacent PSC)
StopIn Stop Input (for synchronized mode)
Note: 1. See Figure 16-38 on page 159
Table 16-2. Block Inputs
Description
Name
PSCINn Input 0 used for Retrigger or Fault functions
from A C Input 1 used for Retrigger or Fault functions
Table 16-3. Block Outputs
Description
Name
PSCOUTn0 PSC n Output 0 (from part A of PSC)
PSCOUTn1 PSC n Output 1 (from part B of PSC)
PSCOUTn2
PSC n Output 2 (from part A or part B of PSC)
(PSC2 only)
PSCOUTn3(
PSC n Output 3 (from part A or part B of PSC)
PSC2 only)
Table 16-4. Internal Outputs
Description
Name
SYnOut Synchronization Output
PICRn PSC n Input Capture Register
[11:0] Counter value at retriggering event
PSC Interrupt Request : three souces, overflow, fault, and input
IRQPSCn
capture
PSCnASY ADC Synchronization (+ Amplifier Syncho. )
StopOut Stop Output (for synchronized mode)
Note: 1. See Figure 16-38 on page 159
2. See "Analog Synchronization" on page 158.
(1)
(1)
(2)
Type
Width
Register
4 bits
Signal
Signal
Signal
Signal
Type
Width
Signal
Signal
Type
Width
Signal
Signal
Signal
Signal
Type
Width
Signal
Register
12 bits
Signal
Signal
4317I–AVR–01/08