Atmel AT90PWM2 Manual page 98

14.8.2 Timer/Counter Control Register B – TCCR0B
4317I–AVR–01/08
Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see
unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of
Pulse Width Modulation (PWM) modes (see
Table 14-8. Waveform Generation Mode Bit Description
Mode WGM02 WGM01
0 0 0
1 0 0
2 0 1
3 0 1
4 1 0
5 1 0
6 1 1
7 1 1
Notes: 1. MAX = 0xFF
2. BOTTOM = 0x00
Bit 7
FOC0A
Read/Write W
Initial Value 0
• Bit 7 – FOC0A: Force Output Compare A
The FOC0A bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when
TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0A bit,
an immediate Compare Match is forced on the Waveform Generation unit. The OC0A output is
changed according to its COM0A1:0 bits setting. Note that the FOC0A bit is implemented as a
strobe. Therefore it is the value present in the COM0A1:0 bits that determines the effect of the
forced compare.
A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR0A as TOP.
The FOC0A bit is always read as zero.
• Bit 6 – FOC0B: Force Output Compare B
The FOC0B bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when
TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0B bit,
an immediate Compare Match is forced on the Waveform Generation unit. The OC0B output is
changed according to its COM0B1:0 bits setting. Note that the FOC0B bit is implemented as a
Table 14-8. Modes of operation supported by the Timer/Counter
"Modes of Operation" on page
Timer/Count
er Mode of
WGM00 Operation
0 Normal
PWM, Phase
1
Correct
0 CTC
1 Fast PWM
0 Reserved
PWM, Phase
1
Correct
0 Reserved
1 Fast PWM
6 5 4
FOC0B – –
W R R
0 0 0
AT90PWM2/3/2B/3B
91).
Update of
TOP OCRx at
0xFF Immediate
0xFF TOP
OCRA Immediate
0xFF TOP
– –
OCRA TOP
– –
OCRA TOP
3 2 1
WGM02 CS02 CS01
R R R/W
0 0 0
TOV Flag
(1)(2)
Set on
MAX
BOTTOM
MAX
MAX
–
BOTTOM
–
TOP
0
CS00 TCCR0B
R/W
0
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