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Atmel AVR AT90CAN32 Manual

Atmel AVR AT90CAN32 Manual

8-bit microcontroller with 32k/64k/128k bytes of isp flash and can controller

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Features

•

High-performance, Low-power AVR

•

Advanced RISC Architecture

– 133 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers + Peripheral Control Registers

– Fully Static Operation

– Up to 16 MIPS Throughput at 16 MHz

– On-chip 2-cycle Multiplier

•

Non volatile Program and Data Memories

– 32K/64K/128K Bytes of In-System Reprogrammable Flash (AT90CAN32/64/128)

• Endurance: 10,000 Write/Erase Cycles

– Optional Boot Code Section with Independent Lock Bits

• Selectable Boot Size: 1K Bytes, 2K Bytes, 4K Bytes or 8K Bytes

• In-System Programming by On-Chip Boot Program (CAN, UART, ...)

• True Read-While-Write Operation

– 1K/2K/4K Bytes EEPROM (Endurance: 100,000 Write/Erase Cycles) (AT90CAN32/64/128)

– 2K/4K/4K Bytes Internal SRAM (AT90CAN32/64/128)

– Up to 64K Bytes Optional External Memory Space

– Programming Lock for Software Security

•

JTAG (IEEE std. 1149.1 Compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard

– Programming Flash (Hardware ISP), EEPROM, Lock & Fuse Bits

– Extensive On-chip Debug Support

•

CAN Controller 2.0A & 2.0B - ISO 16845 Certified

– 15 Full Message Objects with Separate Identifier Tags and Masks

– Transmit, Receive, Automatic Reply and Frame Buffer Receive Modes

– 1Mbits/s Maximum Transfer Rate at 8 MHz

– Time stamping, TTC & Listening Mode (Spying or Autobaud)

•

Peripheral Features

– Programmable Watchdog Timer with On-chip Oscillator

– 8-bit Synchronous Timer/Counter-0

• 10-bit Prescaler

• External Event Counter

• Output Compare or 8-bit PWM Output

– 8-bit Asynchronous Timer/Counter-2

• 10-bit Prescaler

• External Event Counter

• Output Compare or 8-Bit PWM Output

• 32Khz Oscillator for RTC Operation

– Dual 16-bit Synchronous Timer/Counters-1 & 3

• 10-bit Prescaler

• Input Capture with Noise Canceler

• External Event Counter

• 3-Output Compare or 16-Bit PWM Output

• Output Compare Modulation

– 8-channel, 10-bit SAR ADC

• 8 Single-ended Channels

• 7 Differential Channels

• 2 Differential Channels With Programmable Gain at 1x, 10x, or 200x

– On-chip Analog Comparator

– Byte-oriented Two-wire Serial Interface

– Dual Programmable Serial USART

– Master/Slave SPI Serial Interface

• Programming Flash (Hardware ISP)

•

Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated RC Oscillator

– 8 External Interrupt Sources

– 5 Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down & Standby

– Software Selectable Clock Frequency

– Global Pull-up Disable

•

I/O and Packages

– 53 Programmable I/O Lines

– 64-lead TQFP and 64-lead QFN

•

Operating Voltages: 2.7 - 5.5V

•

Operating temperature: Industrial (-40°C to +85°C)

•

Maximum Frequency: 8 MHz at 2.7V, 16 MHz at 4.5V

Note:

1. Details on

section 19.4.3 on page

®

8-bit Microcontroller

(1)

242.

8-bit

Microcontroller

with

32K/64K/128K

Bytes of

ISP Flash

and

CAN Controller

AT90CAN32

AT90CAN64

AT90CAN128

Rev. 7679H–CAN–08/08

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Summary of Contents for Atmel AVR AT90CAN32

Page 1 Features ® • High-performance, Low-power AVR 8-bit Microcontroller • Advanced RISC Architecture – 133 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers + Peripheral Control Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz –...
Page 2: Part Description
This allows very fast start-up combined with low power consumption. The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On- chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core.
Page 3 AT90CAN32/64/128 combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel AT90CAN32/64/128 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The AT90CAN32/64/128 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emula- tors, and evaluation kits.
Page 4: Block Diagram
Block Diagram Figure 1-1. Block Diagram PF7 - PF0 PA7 - PA0 PC7 - PC0 PORTA DRIVERS PORTF DRIVERS PORTC DRIVERS DATA REGISTER DATA DIR. DATA REGISTER DATA DIR. DATA REGISTER DATA DIR. PORTF REG. PORTF PORTA REG. PORTA PORTC REG.
Page 5: Pin Configurations
AT90CAN32/64/128 Pin Configurations Figure 1-2. Pinout AT90CAN32/64/128 - TQFP PA3 (AD3) (RXD0 / PDI) PE0 PA4 (AD4) INDEX CORNER (TXD0 / PDO) PE1 PA5 (AD5) PA6 (AD6) (XCK0 / AIN0) PE2 (OC3A / AIN1) PE3 PA7 (AD7) PG2 (ALE) (OC3B / INT4) PE4 PC7 (A15 / CLKO) (OC3C / INT5) PE5 (T3 / INT6) PE6...
Page 6: Pin Descriptions
Figure 1-3. Pinout AT90CAN32/64/128 - QFN PA3 (AD3) (RXD0 / PDI) PE0 PA4 (AD4) (TXD0 / PDO) PE1 PA5 (AD5) INDEX CORNER (XCK0 / AIN0) PE2 PA6 (AD6) (OC3A / AIN1) PE3 PA7 (AD7) (OC3B / INT4) PE4 PG2 (ALE) (OC3C / INT5) PE5 PC7 (A15 / CLKO) (T3 / INT6) PE6...
Page 7 AT90CAN32/64/128 1.6.3 Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated.
Page 8: About Code Examples
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have sym- metrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated.
Page 9: Avr Cpu Core
AT90CAN32/64/128 3. AVR CPU Core Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Architectural Overview Figure 3-1.
Page 10: Alu - Arithmetic Logic Unit
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ- ical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File –...
Page 11: Status Register
AT90CAN32/64/128 Status Register The Status Register contains information about the result of the most recently executed arith- metic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference.
Page 12: General Purpose Register File
• Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: •...
Page 13 AT90CAN32/64/128 Figure 3-3. The X-, Y-, and Z-registers X-register R27 (0x1B) R26 (0x1A) Y-register R29 (0x1D) R28 (0x1C) Z-register R31 (0x1F) R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 3.5.2 Extended Z-pointer Register for ELPM/SPM –...
Page 14: Stack Pointer
Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory loca- tions to lower memory locations.
Page 15: Reset And Interrupt Handling
AT90CAN32/64/128 Figure 3-6 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destina- tion register. Figure 3-6. Single Cycle ALU Operation Total Execution T i me Register Operands Fetch ALU Operation Execute...
Page 16 The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have interrupt flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.
Page 17 AT90CAN32/64/128 3.8.2 Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles mini- mum. After four clock cycles the program vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles.
Page 18 4. Memories This section describes the different memories in the AT90CAN32/64/128. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the AT90CAN32/64/128 features an EEPROM Memory for data storage. All three memory spaces are linear and regular.
Page 19: Sram Data Memory
AT90CAN32/64/128 Constant tables can be allocated within the entire program memory address space (see the LPM – Load Program Memory and ELPM – Extended Load Program Memory instruction description). Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim- ing”...
Page 20 4.2.1 SRAM Data Access When the addresses accessing the SRAM memory space exceeds the internal data memory locations, the external data SRAM is accessed using the same instructions as for the internal data memory access. When the internal data memories are accessed, the read and write strobe pins (PG0 and PG1) are inactive during the whole access cycle.
Page 21: Data Memory
AT90CAN32/64/128 Figure 4-2. Data Memory Map Data Memory 0x0000 - 0x001F 32 Registers 0x0020 - 0x005F 64 I/O Registers 0x0060 - 0x00FF 160 Ext I/O Reg. ISRAM start Internal SRAM (ISRAM size) ISRAM end XMem start External SRAM (XMem size) 0xFFFF 4.2.2 SRAM Data Access Times...
Page 22: Eeprom Data Memory
EEPROM Data Memory The AT90CAN32/64/128 contains EEPROM memory (see “E2 size”). It is organized as a sepa- rate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Reg- ister, and the EEPROM Control Register.
Page 23 AT90CAN32/64/128 4.3.3 The EEPROM Data Register – EEDR EEDR7 EEDR6 EEDR5 EEDR4 EEDR3 EEDR2 EEDR1 EEDR0 EEDR Read/Write Initial Value • Bits 7..0 – EEDR7.0: EEPROM Data For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register.
Page 24 Support – Read-While-Write Self-Programming” on page 321 for details about Boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail.
Page 25 AT90CAN32/64/128 The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts glo- bally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash Boot Loader is present in the software.
Page 26 The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: ; Wait for completion of previous write sbic EECR,EEWE rjmp...
Page 27: External Memory Interface
AT90CAN32/64/128 I/O Memory The I/O space definition of the AT90CAN32/64/128 is shown in “Register Summary” on page 405. All AT90CAN32/64/128 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space.
Page 28 Figure 4-4. External Memory with Sector Select 0x0000 Internal memory ISRAM end XMem start Lower sector SRW01 SRW00 SRL[2..0] External Memory Upper sector (0-64K x 8) SRW11 SRW10 0xFFFF 4.5.2 Using the External Memory Interface The interface consists of: • AD7:0: Multiplexed low-order address bus and data bus. •...
Page 29 AT90CAN32/64/128 4.5.3 Address Latch Requirements Due to the high-speed operation of the XRAM interface, the address latch must be selected with care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V. When operating at condi- tions above these frequencies, the typical old style 74HC series latch becomes inadequate. The External Memory Interface is designed in compliance to the 74AHC series latch.
Page 30 address actually is driven on the bus. The access time cannot exceed the time from the ALE pulse must be asserted low until data is stable during a read sequence (see t LLRL RLRH DVRH Table 26-7 through Table 26-14). The different wait-states are set up in software. As an addi- tional feature, it is possible to divide the external memory space in two sectors with individual wait-state settings.
Page 31 AT90CAN32/64/128 Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector). The ALE pulse in period T5 is only present if the next instruction accesses the RAM (internal or external). Figure 4-8.
Page 32 4.5.6 External Memory Control Register A – XMCRA SRL2 SRL1 SRL0 SRW11 SRW10 SRW01 SRW00 XMCRA Read/Write Initial Value • Bit 7 – SRE: External SRAM/XMEM Enable Writing SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8, ALE, WR, and RD are activated as the alternate pin functions.
Page 33 AT90CAN32/64/128 • Bit 3..2 – SRW11, SRW10: Wait-state Select Bits for Upper Sector The SRW11 and SRW10 bits control the number of wait-states for the upper sector of the exter- nal memory address space, see Table 4-4. • Bit 1..0 – SRW01, SRW00: Wait-state Select Bits for Lower Sector The SRW01 and SRW00 bits control the number of wait-states for the lower sector of the exter- nal memory address space, see Table...
Page 34 Table 4-5. Port C Pins Released as Normal Port Pins when the External Memory is Enabled XMM2 XMM1 XMM0 # Bits for External Memory Address Released Port Pins 8 (Full External Memory Space) None PC7 .. PC6 PC7 .. PC5 PC7 ..
Page 35 AT90CAN32/64/128 4.5.9 Using all 64KB Locations of External Memory Since the External Memory is mapped after the Internal Memory as shown in Figure 4-4, only (64K-(“ISRAM size”+256)) bytes of External Memory is available by default (address space 0x0000 to “ISRAM end” is reserved for internal memory). However, it is possible to take advan- tage of the entire External Memory by masking the higher address bits to zero.
Page 36: General Purpose I/O Registers
General Purpose I/O Registers The AT90CAN32/64/128 contains three General Purpose I/O Registers. These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags. The General Purpose I/O Register 0, within the address range 0x00 - 0x1F, is directly bit-acces- sible using the SBI, CBI, SBIS, and SBIC instructions.
Page 37: Clock Systems And Their Distribution
AT90CAN32/64/128 5. System Clock Clock Systems and their Distribution Figure 5-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to unused modules can be halted by using different sleep modes, as described in “Power Management and Sleep Modes”...
Page 38: Default Clock Source
5.1.4 Asynchronous Timer Clock – clk The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external clock or an external 32 kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode. 5.1.5 ADC Clock –...
Page 39: Crystal Oscillator
AT90CAN32/64/128 Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be con- figured for use as an On-chip Oscillator, as shown in Figure 5-2. Either a quartz crystal or a ceramic resonator may be used. C1 and C2 should always be equal for both crystals and resonators.
Page 40: Low-Frequency Crystal Oscillator
Table 5-4. Start-up Times for the Oscillator Clock Selection Start-up Time from Additional Delay CKSEL0 SUT1..0 Power-down and from Reset Recommended Usage Power-save = 5.0V) Ceramic resonator, fast 258 CK 14 CK + 4.1 ms rising power Ceramic resonator, slowly 258 CK 14 CK + 65 ms rising power...
Page 41: Calibrated Internal Rc Oscillator
RC Oscillator. At 5V and 25°C, this calibration gives a fre- quency within ± 10% of the nominal frequency. Using calibration methods as described in application notes available at www.atmel.com/avr it is possible to achieve ± 2% accuracy at any given V and temperature.
Page 42: External Clock
When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 5-8. Table 5-8. Start-up times for the internal calibrated RC Oscillator clock selection Start-up Time from Power- Additional Delay from SUT1..0 Recommended Usage down and Power-save Reset (V = 5.0V)
Page 43: Clock Output Buffer
AT90CAN32/64/128 Figure 5-4. External Clock Drive Configuration XTAL2 External XTAL1 Clock Signal Table 5-10. External Clock Frequency CKSEL3..0 Frequency Range 0000 0 - 16 MHz When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 5-11.
Page 44: System Clock Prescaler
AT90CAN32/64/128 share the Timer/Counter2 Oscillator Pins (TOSC1 and TOSC2) with PG4 and PG3. This means that both PG4 and PG3 can only be used when the Timer/Counter2 Oscil- lator is not enable. Applying an external clock source to TOSC1 can be done in asynchronous operation if EXTCLK in the ASSR Register is written to logic one.
Page 45 AT90CAN32/64/128 “0011”, giving a division factor of 8 at start up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operat- ing conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting.
Page 46: Power Management And Sleep Modes
6. Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- tion to the application’s requirements. To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP instruction must be executed.
Page 47: Idle Mode
AT90CAN32/64/128 purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up. Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, CAN, USART, Analog Comparator, ADC, Two-wire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating.
Page 48: Standby Mode
If Timer/Counter2 is clocked asynchronously, i.e., the AS2 bit in ASSR is set, Timer/Counter2 will run during sleep. The device can wake up from either Timer Overflow or Output Compare event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in TIMSK2, and the global interrupt enable bit in SREG is set.
Page 49 AT90CAN32/64/128 6.6.2 Analog Comparator When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In other sleep modes, the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all sleep modes.
Page 50 this will contribute significantly to the total current consumption. There are three alternative ways to avoid this: • Disable OCDEN Fuse. • Disable JTAGEN Fuse. • Write one to the JTD bit in MCUCR. The TDO pin is left floating when the JTAG interface is enabled while the JTAG TAP controller is not shifting data.
Page 51: System Control And Reset
AT90CAN32/64/128 7. System Control and Reset Reset 7.1.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute Jump –...
Page 52 Figure 7-1. Reset Logic DATA BUS MCU Status Register (MCUSR) Power-on Reset Circuit Brown-out Reset Circuit BODLEVEL [2..0] Pull-up Resistor Spike Filter JTAG Reset Register Watchdog Oscillator Delay Counters Clock TIMEOUT Generator CKSEL[3:0] SUT[1:0] Table 7-1. Reset Characteristics Symbol Parameter Condition Min.
Page 53 AT90CAN32/64/128 rise. The RESET signal is activated again, without any delay, when V decreases below the detection level. Figure 7-2. MCU Start-up, RESET Tied to V CCRR RESET CCRR TIME-OUT TOUT INTERNAL RESET Figure 7-3. MCU Start-up, RESET Extended Externally CCRR RESET TIME-OUT...
Page 54 Figure 7-4. External Reset During Operation 7.1.5 Brown-out Detection AT90CAN32/64/128 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection.
Page 55 AT90CAN32/64/128 Figure 7-5), the delay counter starts the MCU after the Time-out period t BOT+ TOUT expired. The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level for longer than t given in Table 7-3.
Page 56: Internal Voltage Reference
7.1.7 MCU Status Register – MCUSR The MCU Status Register provides information on which reset source caused an MCU reset. – – – JTRF WDRF BORF EXTRF PORF MCUSR Read/Write Initial Value See Bit Description • Bit 7..5 – Reserved Bits These bits are reserved for future use.
Page 57: Watchdog Timer
AT90CAN32/64/128 ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode. 7.2.2 Voltage Reference Characteristics Table 7-4. Internal Voltage Reference Characteristics Symbol Parameter Condition...
Page 58 7.3.1 Watchdog Timer Control Register – WDTCR – – – WDCE WDP2 WDP1 WDP0 WDTCR Read/Write Initial Value • Bits 7..5 – Reserved Bits These bits are reserved bits for future use. • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero.
Page 59: Timed Sequences For Changing The Configuration Of The Watchdog Timer
AT90CAN32/64/128 The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. Assembly Code Example WDT_off: ;...
Page 60 8. Interrupts T h i s s e c t i o n d e s c r i b e s t h e s p e c i f i c s o f t h e i n t e r r u p t h a n d l i n g a s p e r f o r m e d i n AT90CAN32/64/128.
Page 61 AT90CAN32/64/128 Table 8-1. Reset and Interrupt Vectors (Continued) Vector Program Source Interrupt Definition Address 0x0038 TIMER3 COMPA Timer/Counter3 Compare Match A 0x003A TIMER3 COMPB Timer/Counter3 Compare Match B 0x003C TIMER3 COMPC Timer/Counter3 Compare Match C 0x003E TIMER3 OVF Timer/Counter3 Overflow 0x0040 USART1, RX USART1, Rx Complete...
Page 62 0x0012 TIM2_COMP ; Timer2 Compare Handler 0x0014 TIM2_OVF ; Timer2 Overflow Handler 0x0016 TIM1_CAPT ; Timer1 Capture Handler 0x0018 TIM1_COMPA; Timer1 CompareA Handler 0x001A TIM1_COMPB; Timer1 CompareB Handler 0x001C TIM1_OVF ; Timer1 CompareC Handler 0x001E TIM1_OVF ; Timer1 Overflow Handler 0x0020 TIM0_COMP ;...
Page 63 AT90CAN32/64/128 0x0004 ; Enable interrupts 0x0005 <instr> .org (BootResetAdd + 0x0002) 0x..02 EXT_INT0 ; IRQ0 Handler 0x..04 PCINT0 ; PCINT0 Handler 0x..0C SPM_RDY ; Store Program Memory Ready Handler When the BOOTRST Fuse is programmed and the Boot section size set to 8K bytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: ;Address Labels Code...
Page 64: Moving Interrupts Between Application And Boot Space
Moving Interrupts Between Application and Boot Space The General Interrupt Control Register controls the placement of the Interrupt Vector table. 8.2.1 MCU Control Register – MCUCR – – – – IVSEL IVCE MCUCR Read/Write Initial Value • Bit 1 – IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory.
Page 65 AT90CAN32/64/128 • Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above.
Page 66 9. I/O-Ports Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when chang- ing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
Page 67: Ports As General Digital I/O
AT90CAN32/64/128 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 9-2 shows a func- tional description of one I/O-port pin, here generically called Pxn. Figure 9-2. General Digital I/O DDxn RESET PORTxn RESET SLEEP SYNCHRONIZER PINxn...
Page 68 If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 9.2.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.
Page 69 AT90CAN32/64/128 Figure 9-3. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS in r17, PINx SYNC LATCH PINxn 0x00 0xFF pd, max pd, min Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH”...
Page 70 The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins.
Page 71: Alternate Port Functions
AT90CAN32/64/128 above mentioned sleep modes, as the clamping in these sleep modes produces the requested logic change. 9.2.6 Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, float- ing inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode).
Page 72 Figure 9-5. Alternate Port Functions PUOExn PUOVxn DDOExn DDOVxn DDxn PVOExn RESET PVOVxn PORTxn PTOExn DIEOExn DIEOVxn RESET SLEEP SYNCHRONIZER PINxn DIxn AIOxn PUOExn: Pxn PULL-UP OVERRIDE ENABLE PUD: PULLUP DISABLE PUOVxn: Pxn PULL-UP OVERRIDE VALUE WDx: WRITE DDRx DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE RDx: READ DDRx DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE RRx: READ PORTx REGISTER...
Page 73 AT90CAN32/64/128 Table 9-2. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description If this signal is set, the pull-up enable is controlled by the PUOV Pull-up Override PUOE signal. If this signal is cleared, the pull-up is enabled when Enable {DDxn, PORTxn, PUD} = 0b010.
Page 74 • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Con- figuring the Pin”...
Page 75 AT90CAN32/64/128 Table 9-4 Table 9-5 relates the alternate functions of Port A to the overriding signals shown Figure 9-5 on page Table 9-4. Overriding Signals for Alternate Functions in PA7..PA4 Signal Name PA7/AD7 PA6/AD6 PA5/AD5 PA4/AD4 SRE • SRE • SRE •...
Page 76 9.3.3 Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 9-6. Table 9-6. Port B Pins Alternate Functions Port Pin Alternate Functions OC0A/OC1C (Output Compare and PWM Output A for Timer/Counter0 or Output Compare and PWM Output C for Timer/Counter1) OC1B (Output Compare and PWM Output B for Timer/Counter1) OC1A (Output Compare and PWM Output A for Timer/Counter1)
Page 77 AT90CAN32/64/128 MOSI, SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB2. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB2. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB2 bit.
Page 78 Table 9-8. Overriding Signals for Alternate Functions in PB3..PB0 Signal Name PB3/MISO PB2/MOSI PB1/SCK PB0/SS PUOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR PUOV PORTB3 • PUD PORTB2 • PUD PORTB1 • PUD PORTB0 • PUD DDOE SPE •...
Page 79 AT90CAN32/64/128 • A14 – Port C, Bit 6 A14, External memory interface address 14. • A13 – Port C, Bit 5 A13, External memory interface address 13. • A12 – Port C, Bit 4 A12, External memory interface address 12. •...
Page 80 Table 9-11. Overriding Signals for Alternate Functions in PC3..PC0 Signal Name PC3/A11 PC2/A10 PC1/A9 PC0/A8 PUOE SRE • (XMM<5) SRE • (XMM<6) SRE • (XMM<7) SRE • (XMM<7) PUOV DDOE SRE • (XMM<5) SRE • (XMM<6) SRE • (XMM<7) SRE • (XMM<7) DDOV PVOE SRE •...
Page 81 AT90CAN32/64/128 TXCAN, CAN Transmit Data (Data output pin for the CAN). When the CAN is enabled, this pin is configured as an output regardless of the value of DDD5. XCK1, USART1 External clock. The Data Direction Register (DDD5) controls whether the clock is output (DDD5 set) or input (DDD45 cleared).
Page 82 Table 9-13 Table 9-14 relates the alternate functions of Port D to the overriding signals shown in Figure 9-5 on page Table 9-13. Overriding Signals for Alternate Functions PD7..PD4 Signal Name PD7/T0 PD6/T1/RXCAN PD5/XCK1/TXCAN PD4/ICP1 PUOE RXCANEN TXCANEN + PUOV PORTD6 •...
Page 83 AT90CAN32/64/128 9.3.6 Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 9-15. Table 9-15. Port E Pins Alternate Functions Port Pin Alternate Function INT7/ICP3 (External Interrupt 7 Input or Timer/Counter3 Input Capture Trigger) INT6/ T3 (External Interrupt 6 Input or Timer/Counter3 Clock Input) INT5/OC3C (External Interrupt 5 Input or Output Compare and PWM Output C for Timer/Counter3)
Page 84 • AIN0/XCK0 – Port E, Bit 2 AIN0 – Analog Comparator Positive input. This pin is directly connected to the positive input of the Analog Comparator. XCK0, USART0 External clock. The Data Direction Register (DDE2) controls whether the clock is output (DDE2 set) or input (DDE2 cleared). The XCK0 pin is active only when the USART0 operates in Synchronous mode.
Page 85 AT90CAN32/64/128 Table 9-17. Overriding Signals for Alternate Functions in PE3..PE0 Signal Name PE3/AIN1/OC3A PE2/AIN0/XCK0 PE1/PDO/TXD0 PE0/PDI/RXD0 PUOE TXEN0 RXEN0 PUOV PORTE0 • PUD DDOE TXEN0 RXEN0 DDOV PVOE OC3A ENABLE UMSEL0 TXEN0 PVOV OC3A XCK0 OUTPUT TXD0 PTOE DIEOE AIN1D AIN0D DIEOV XCK0 INPUT...
Page 86 TDI, JTAG Test Data In. Serial input data to be shifted in to the Instruction Register or Data Reg- ister (scan chains). When the JTAG interface is enabled, this pin can not be used as an I/O pin. • TCK, ADC6 – Port F, Bit 6 ADC6, Analog to Digital Converter, input channel 6 TDO, JTAG Test Data Out.
Page 87 AT90CAN32/64/128 Table 9-19 Table 9-20 relates the alternate functions of Port F to the overriding signals shown in Figure 9-5 on page Table 9-19. Overriding Signals for Alternate Functions in PF7..PF4 Signal Name PF7/ADC7/TDI PF6/ADC6/TDO PF5/ADC5/TMS PF4/ADC4/TCK PUOE JTAGEN JTAGEN JTAGEN JTAGEN PUOV...
Page 88 9.3.8 Alternate Functions of Port G The alternate pin configuration is as follows: Table 9-21. Port G Pins Alternate Functions Port Pin Alternate Function TOSC1 (RTC Oscillator Timer/Counter2) TOSC2 (RTC Oscillator Timer/Counter2) ALE (Address Latch Enable to external memory) RD (Read strobe to external memory) WR (Write strobe to external memory) The alternate pin configuration is as follows: •...
Page 89 AT90CAN32/64/128 Table 9-21 Table 9-22 relates the alternate functions of Port G to the overriding signals shown in Figure 9-5 on page Table 9-22. Overriding Signals for Alternate Function in PG4 Signal Name PG4/TOSC1 PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV...
Page 90 9.4.2 Port A Data Direction Register – DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRA Read/Write Initial Value 9.4.3 Port A Input Pins Address – PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 PINA Read/Write Initial Value 9.4.4 Port B Data Register –...
Page 91 AT90CAN32/64/128 9.4.10 Port D Data Register – PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 PORTD Read/Write Initial Value 9.4.11 Port D Data Direction Register – DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 DDRD Read/Write Initial Value 9.4.12 Port D Input Pins Address –...
Page 92 9.4.18 Port F Input Pins Address – PINF PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 PINF Read/Write Initial Value 9.4.19 Port G Data Register – PORTG – – – PORTG4 PORTG3 PORTG2 PORTG1 PORTG0 PORTG Read/Write Initial Value 9.4.20 Port G Data Direction Register –...
Page 93: External Interrupts
AT90CAN32/64/128 10. External Interrupts The External Interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of gen- erating a software interrupt. The External Interrupts can be triggered by a falling or rising edge or a low level.
Page 94 Table 10-1. Asynchronous External Interrupt Sense Control ISCn1 ISCn0 Description The low level of INTn generates an interrupt request. Any logical change on INTn generates an interrupt request The falling edge of INTn generates asynchronously an interrupt request. The rising edge of INTn generates asynchronously an interrupt request. Note: 1.
Page 95 AT90CAN32/64/128 10.1.3 External Interrupt Mask Register – EIMSK INT7 INT6 INT5 INT4 INT3 INT2 INT1 IINT0 EIMSK Read/Write Initial Value • Bits 7..0 – INT7 – INT0: External Interrupt Request 7 - 0 Enable When an INT7 – INT0 bit is written to one and the I-bit in the Status Register (SREG) is set (one), the corresponding external pin interrupt is enabled.
Page 96 11. Timer/Counter3/1/0 Prescalers Timer/Counter3, Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter3, Timer/Counter1 and Timer/Counter0. 11.1 Overview Most bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number.
Page 97 AT90CAN32/64/128 Figure 11-1. T3/T1/T0 Pin Sampling Tn_sync (To Clock Select Logic) Synchronization Edge Detector The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T3/T1/T0 pin to the counter is updated. Enabling and disabling of the clock input must be done when T3/T1/T0 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Page 98 11.2 Timer/Counter0/1/3 Prescalers Register Description 11.2.1 General Timer/Counter Control Register – GTCCR – – – – – PSR2 PSR310 GTCCR Read/Write Initial Value • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR2 and PSR310 bits is kept, hence keeping the corresponding prescaler reset signals asserted.
Page 99 AT90CAN32/64/128 12. 8-bit Timer/Counter0 with PWM Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: 12.1 Features • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) •...
Page 100: Timer/Counter Clock Sources
12.2.1 Registers The Timer/Counter (TCNT0) and Output Compare Register (OCR0A) are 8-bit registers. Inter- rupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked with the Timer Interrupt Mask Reg- ister (TIMSK0).
Page 101: Output Compare Unit
AT90CAN32/64/128 Signal description (internal signals): count Increment or decrement TCNT0 by 1. direction Select between increment and decrement. clear Clear TCNT0 (set all bits to zero). Timer/Counter clock, referred to as clk in the following. Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero).
Page 102 Figure 12-3 shows a block diagram of the Output Compare unit. Figure 12-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn (8-bit Comparator ) OCFnx (Int.Req.) bottom Waveform Generator OCnx FOCn WGMn1:0 COMnX1:0 The OCR0A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes.
Page 103: Compare Match Output Unit
AT90CAN32/64/128 generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is downcounting. The setup of the OC0A should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0A value is to use the Force Output Com- pare (FOC0A) strobe bits in Normal mode.
Page 104: Modes Of Operation
12.6.2 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0A1:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM0A1:0 = 0 tells the Waveform Generator that no action on the OC0A Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 12-2 on page 110.
Page 105 AT90CAN32/64/128 Figure 12-5. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn OCnx (COMnx1:0 = 1) (Toggle) Period An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
Page 106 inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0A and TCNT0. Figure 12-6. Fast PWM Mode, Timing Diagram OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period...
Page 107 AT90CAN32/64/128 12.7.4 Phase Correct PWM Mode The phase correct PWM mode (WGM01:0 = 1) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non- inverting Compare Output mode, the Output Compare (OC0A) is cleared on the compare match between TCNT0 and OCR0A while upcounting, and set on the compare match while down- counting.
Page 108: Timer/Counter Timing Diagrams
decrements. The PWM frequency for the output when using phase correct PWM can be calcu- lated by the following equation: clk_I/O ----------------- - ⋅ OCnxPCPWM N 510 The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0A Register represent special cases when generating a PWM waveform output in the phase correct PWM mode.
Page 109: 8-Bit Timer/Counter Register Description
AT90CAN32/64/128 Figure 12-10 shows the setting of OCF0A in all modes except CTC mode. Figure 12-10. Timer/Counter Timing Diagram, Setting of OCF0A, with Prescaler (f clk_I/O (clk TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx OCRnx Value OCFnx Figure 12-11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode.
Page 110 • Bit 6, 3 – WGM01:0: Waveform Generation Mode These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes.
Page 111 AT90CAN32/64/128 Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the com- pare match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 105 for more details.
Page 112 12.9.3 Output Compare Register A – OCR0A OCR0A[7:0] OCR0 Read/Write Initial Value The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0A pin.
Page 113 AT90CAN32/64/128 13. 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3) The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: 13.1 Features • True 16-bit Design (i.e., Allows 16-bit PWM) • Three independent Output Compare Units •...
Page 114 Figure 13-1. 16-bit Timer/Counter Block Diagram Count TOVn (Int.Req.) Clear Control Logic Direction Clock Select Edge Detector BOTTOM ( From Prescaler ) Timer/Counter TCNTn OCFnA (Int.Req.) Waveform OCnA Generation OCRnA OCFnB Fixed (Int.Req.) Values Waveform OCnB Generation OCRnB OCFnC (Int.Req.) Waveform OCnC Generation...
Page 115 AT90CAN32/64/128 uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk The double buffered Output Compare Registers (OCRnx) are compared with the Timer/Counter value at all time.
Page 116: Accessing 16-Bit Registers
The 16-bit Timer/Counter has improvements that will affect the compatibility in some special cases. The following bits are added to the 16-bit Timer/Counter Control Registers: • COMnC1:0 are added to TCCRnA. • FOCnA, FOCnB and FOCnC are added to TCCRnC. •...
Page 117 AT90CAN32/64/128 13.3.1 Code Examples The following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the OCRnx and ICRn Registers. Note that when using “C”, the compiler handles the 16-bit access.
Page 118: C Code Example
The following code examples show how to do an atomic read of the TCNTn Register contents. Reading any of the OCRnx or ICRn Registers can be done by using the same principle. Assembly Code Example TIM16_ReadTCNTn: ; Save global interrupt flag r18,SREG ;...
Page 119: Timer/Counter Clock Sources
AT90CAN32/64/128 The following code examples show how to do an atomic write of the TCNTn Register contents. Writing any of the OCRnx or ICRn Registers can be done by using the same principle. Assembly Code Example TIM16_WriteTCNTn: ; Save global interrupt flag r18,SREG ;...
Page 120: Counter Unit
13.5 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 13-2 shows a block diagram of the counter and its surroundings. Figure 13-2. Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int.Req.) TEMP (8-bit) Clock Select Count...
Page 121: Input Capture Unit
AT90CAN32/64/128 The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt. 13.6 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence.
Page 122 cleared when the interrupt is executed. Alternatively the ICFn flag can be cleared by software by writing a logical one to its I/O bit location. Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading the low byte (ICRnL) and then the high byte (ICRnH).
Page 123: Output Compare Units
AT90CAN32/64/128 priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively changed during operation, is not recommended.
Page 124 Figure 13-4. Output Compare Unit, Block Diagram DATA BUS (8-bit) TEMP (8-bit) OCRnxH Buf.(8-bit) OCRnxL Buf.(8-bit) TCNTnH (8-bit) TCNTnL (8-bit) OCRnx Buffer (16-bit Register) TCNTn (16-bit Counter) OCRnxH (8-bit) OCRnxL (8-bit) OCRnx (16-bit Register) (16-bit Comparator ) OCFnx (Int.Req.) Waveform Generator OCnx BOTTOM WGMn3:0...
Page 125: Compare Match Output Unit
AT90CAN32/64/128 match had occurred (the COMnx1:0 bits settings define whether the OCnx pin is set, cleared or toggled). 13.7.2 Compare Match Blocking by TCNTn Write All CPU writes to the TCNTn Register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped.
Page 126: Modes Of Operation
Figure 13-5. Compare Match Output Unit, Schematic COMnx1 Waveform COMnx0 Generator FOCnx OCnx OCnx PORT 13.8.1 Compare Output Function The general I/O port function is overridden by the Output Compare (OCnx) from the Waveform Generator if either of the COMnx1:0 bits are set. However, the OCnx pin direction (input or out- put) is still controlled by the Data Direction Register (DDR) for the port pin.
Page 127 AT90CAN32/64/128 while the Waveform Generation mode bits do. The COMnx1:0 bits control whether the PWM out- put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COMnx1:0 bits control whether the output should be set, cleared or toggle at a compare match (See “Compare Match Output Unit”...
Page 128 An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or ICFn flag according to the register used to define the TOP value. If the inter- rupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature.
Page 129 AT90CAN32/64/128 shows fast PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare matches between OCRnx and TCNTn.
Page 130 In fast PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COMnx1:0 to three (see Table on page 136).
Page 131 AT90CAN32/64/128 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx inter- rupt flag will be set when a compare match occurs.
Page 132 output (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Regis- ter at the compare match between OCRnx and TCNTn when the counter increments, and clearing (or setting) the OCnx Register at compare match between OCRnx and TCNTn when the counter decrements.
Page 133 AT90CAN32/64/128 Figure 13-9. Phase and Frequency Correct PWM Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Update and TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period The Timer/Counter Overflow Flag (TOVn) is set at the same timer clock cycle as the OCRnx Registers are updated with the double buffer value (at BOTTOM).
Page 134: Timer/Counter Timing Diagrams
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx Register represents special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be set to high for non- inverted PWM mode.
Page 135 AT90CAN32/64/128 Figure 13-12. Timer/Counter Timing Diagram, no Prescaling (clk TCNTn TOP - 1 BOTTOM BOTTOM + 1 (CTC and FPWM) TCNTn TOP - 1 TOP - 1 TOP - 2 (PC and PFC PWM) TOVn (FPWM) and ICFn (if used as TOP) OCRnx New OCRnx Value...
Page 136 • Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A • Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B • Bit 3:2 – COMnC1:0: Compare Output Mode for Channel C The COMnA1:0, COMnB1:0 and COMnC1:0 control the Output Compare pins (OCnA, OCnB and OCnC respectively) behavior.
Page 137 AT90CAN32/64/128 Table 13-3 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase correct or the phase and frequency correct, PWM mode. Table 13-3. Compare Output Mode, Phase Correct and Phase and Frequency Correct COMnA1/COMnB1/ COMnA0/COMnB0/ Description COMnC1 COMnC0...
Page 138 Table 13-4. Waveform Generation Mode Bit Description WGMn2 WGMn1 WGMn0 Timer/Counter Update of TOVn Flag Mode WGMn3 (CTCn) (PWMn1) (PWMn0) Mode of Operation OCRnx at Set on Normal 0xFFFF Immediate PWM, Phase Correct, 8-bit 0x00FF BOTTOM PWM, Phase Correct, 9-bit 0x01FF BOTTOM PWM, Phase Correct, 10-...
Page 139 AT90CAN32/64/128 This bit selects which edge on the Input Capture pin (ICPn) that is used to trigger a capture event. When the ICESn bit is written to zero, a falling (negative) edge is used as trigger, and when the ICESn bit is written to one, a rising (positive) edge will trigger the capture. When a capture is triggered according to the ICESn setting, the counter value is copied into the Input Capture Register (ICRn).
Page 140 13.11.6 Timer/Counter3 Control Register C – TCCR3C FOC3A FOC3B FOC3C – – – – – TCCR3C Read/Write Initial Value • Bit 7 – FOCnA: Force Output Compare for Channel A • Bit 6 – FOCnB: Force Output Compare for Channel B •...
Page 141 AT90CAN32/64/128 13.11.9 Output Compare Register A – OCR1AH and OCR1AL OCR1A[15:8] OCR1AH OCR1A[7:0] OCR1AL Read/Write Initial Value 13.11.10 Output Compare Register B – OCR1BH and OCR1BL OCR1B[15:8] OCR1BH OCR1B[7:0] OCR1BL Read/Write Initial Value 13.11.11 Output Compare Register C – OCR1CH and OCR1CL OCR1C[15:8] OCR1CH OCR1C[7:0]...
Page 142 13.11.15 Input Capture Register – ICR1H and ICR1L ICR1[15:8] ICR1H ICR1[7:0] ICR1L Read/Write Initial Value 13.11.16 Input Capture Register – ICR3H and ICR3L ICR3[15:8] ICR3H ICR3[7:0] ICR3L Read/Write Initial Value The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the ICPn pin (or optionally on the Analog Comparator output for Timer/Counter1).
Page 143 AT90CAN32/64/128 • Bit 2 – OCIEnB: Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts”...
Page 144 • Bit 2 – OCFnB: Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output Compare Register B (OCRnB). Note that a Forced Output Compare (FOCnB) strobe will not set the OCFnB flag. OCFnB is automatically cleared when the Output Compare Match B Interrupt Vector is exe- cuted.
Page 145 AT90CAN32/64/128 14. 8-bit Timer/Counter2 with PWM and Asynchronous Operation Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: 14.1 Features • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) •...
Page 146 Figure 14-1. 8-bit Timer/Counter2 Block Diagram TCCRnx count TOVn (Int.Req.) clear Control Logic direction TOSC2 BOTTOM Oscillator Prescaler TOSC1 Timer/Counter TCNTn 0xFF OCnx (Int.Req.) Waveform OCnx Generation OCRnx Synchronized Status flags Synchronization Unit Status flags ASSRn asynchronous mode select (ASn) The Timer/Counter (TCNT2) and Output Compare Register (OCR2A) are 8-bit registers.
Page 147 AT90CAN32/64/128 14.2.1 Definitions The following definitions are used extensively throughout the section: BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00). The counter reaches its MAXimum when it becomes 0xFF (decimal 255). The counter reaches the TOP when it becomes equal to the highest value in the count sequence.
Page 148 Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk ). clk can be generated from an external or internal clock source, selected by the Clock Select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the timer is stopped.
Page 149 AT90CAN32/64/128 Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR2A Register access may seem complex, but this is not case. When the double buffer- ing is enabled, the CPU has access to the OCR2A Buffer Register, and if double buffering is disabled the CPU will access the OCR2A directly.
Page 150 Figure 14-5. Compare Match Output Unit, Schematic COMnx1 Waveform COMnx0 Generator FOCnx OCnx OCnx PORT 14.6.1 Compare Output Function The general I/O port function is overridden by the Output Compare (OC2A) from the Waveform Generator if either of the COM2A1:0 bits are set. However, the OC2A pin direction (input or out- put) is still controlled by the Data Direction Register (DDR) for the port pin.
Page 151 AT90CAN32/64/128 For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 155. 14.7.1 Normal Mode The simplest mode of operation is the Normal mode (WGM21:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot- tom (0x00).
Page 152 For generating a waveform output in CTC mode, the OC2A output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COM2A1:0 = 1). The OC2A value will not be visible on the port pin unless the data direction for the pin is set to output.
Page 153 AT90CAN32/64/128 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the inter- rupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2A pin. Setting the COM2A1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM2A1:0 to three (See Table 14-3 on page...
Page 154 Figure 14-8. Phase Correct PWM Mode, Timing Diagram OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The interrupt flag can be used to generate an interrupt each time the counter reaches the BOTTOM value.
Page 155 AT90CAN32/64/128 match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-counting Compare Match. • The timer starts counting from a value higher than the one in OCR2A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up.
Page 156 Figure 14-11. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (f clk_I/O (clk TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx OCRnx Value OCFnx AT90CAN32/64/128 7679H–CAN–08/08...
Page 157 AT90CAN32/64/128 Figure 14-12 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. Figure 14-12. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- caler (f clk_I/O (clk TCNTn TOP - 1 BOTTOM BOTTOM + 1 (CTC) OCRnx OCFnx...
Page 158 two types of Pulse Width Modulation (PWM) modes. See Table 14-1 “Modes of Operation” on page 150. Table 14-1. Waveform Generation Mode Bit Description WGM21 WGM20 Timer/Counter Update of TOV2 Flag Mode (CTC2) (PWM2) Mode of Operation OCR2A at Set on Normal 0xFF Immediate...
Page 159 AT90CAN32/64/128 Table 14-4 shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase cor- rect PWM mode. Table 14-4. Compare Output Mode, Phase Correct PWM Mode COM2A1 COM2A0 Description Normal port operation, OC2A disconnected. Reserved Clear OC2A on compare match when up-counting. Set OC2A on compare match when downcounting.
Page 160 The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC2A pin. 14.10 Asynchronous operation of the Timer/Counter2 14.10.1 Asynchronous Status Register –...
Page 161 AT90CAN32/64/128 14.10.2 Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the timer registers TCNT2, OCR2A, and TCCR2A might be corrupted. A safe procedure for switching clock source is: a.
Page 162 • Description of wake up from Power-save mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value.
Page 163 AT90CAN32/64/128 • Bit 7..2 – Reserved Bits These bits are reserved for future use. • Bit 1 – OCF2A: Output Compare Flag 2 A The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2A –...
Page 164 Figure 14-14. Timer/Counter2 Crystal Oscillator Connections 12 - 22 pF TOSC2 32.768 KHz TOSC1 12 - 22 pF A external clock can also be used using TOSC1 as input. Setting AS2 and EXCLK enables this configuration. Figure 14-15. Timer/Counter2 External Clock Connections TOSC2 External TOSC1...
Page 165 AT90CAN32/64/128 15. Output Compare Modulator - OCM 15.1 Overview Many register and bit references in this section are written in general form. • A lower case “n” replaces the Timer/Counter number, in this case 0 and 1. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing Timer/Counter0 counter value and so on.
Page 166 Figure 15-2. Output Compare Modulator, Schematic COM0A1 COM0A0 COM1C1 Modulator COM1C0 (From T/C1 Waveform Generator) OC1C OC0A / OC1C / PB7 (From T/C0 Waveform Generator) OC0A PORTB7 DDRB7 DATABUS 15.2.1 Timing Example Figure 15-3 illustrates the modulator in action. In this example the Timer/Counter1 is set to oper- ate in fast PWM mode (non-inverted) and Timer/Counter0 uses CTC waveform mode with toggle Compare Output mode (COMnx1:0 = 1).
Page 167 AT90CAN32/64/128 15.2.2 Resolution of the PWM Signal The resolution of the PWM signal (OC1C) is reduced by the modulation. The reduction factor is equal to the number of system clock cycles of one period of the carrier (OC0A). In this example the resolution is reduced by a factor of two.
Page 168: Serial Peripheral Interface (Spi)
16. Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT90CAN32/64/128 and peripheral devices or between several AVR devices. The AT90CAN32/64/128 SPI includes the following features: 16.1 Features • Full-duplex, Three-wire Synchronous Data Transfer •...
Page 169 AT90CAN32/64/128 The interconnection between Master and Slave CPUs with SPI is shown in Figure 16-2. The sys- tem consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data.
Page 170 When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 16-1. For more details on automatic port overrides, refer to “Alternate Port Functions” on page Table 16-1. SPI Pin Overrides Direction, Master SPI Direction, Slave SPI MOSI...
Page 171 AT90CAN32/64/128 The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins.
Page 172: Ss Pin Functionality
The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example SPI_SlaveInit: ; Set MISO output, all others input r17,(1<<DD_MISO) DDR_SPI,r17 ; Enable SPI r17,(1<<SPE) SPCR,r17 SPI_SlaveReceive: ; Wait for reception complete sbis SPSR,SPIF rjmp...
Page 173 AT90CAN32/64/128 means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high. The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous with the master clock generator. When the SS pin is driven high, the SPI slave will immediately reset the send and receive logic, and drop any partially received data in the Shift Register.
Page 174 and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas- ter mode. • Bit 3 – CPOL: Clock Polarity When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle.
Page 175: Data Modes
AT90CAN32/64/128 16.2.4 SPI Status Register – SPSR SPIF WCOL – – – – – SPI2X SPSR Read/Write Initial Value • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled.
Page 176 nal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing Table 16-2 Table 16-3, as done below: Table 16-5. CPOL Functionality Leading Edge Trailing Edge SPI Mode CPOL=0, CPHA=0 Sample (Rising) Setup (Falling) CPOL=0, CPHA=1 Setup (Rising) Sample (Falling) CPOL=1, CPHA=0...
Page 177: Dual Usart
AT90CAN32/64/128 17. USART (USART0 and USART1) The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: 17.1 Features • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation •...
Page 178 Figure 17-1. USARTn Block Diagram Clock Generator UBRRn[H:L] CLKio BAUD RATE GENERATOR SYNC LOGIC XCKn CONTROL Transmitter UDRn (Transmit) CONTROL PARITY GENERATOR TRANSMIT SHIFT REGISTER TxDn CONTROL Receiver CLOCK RECOVERY CONTROL DATA RECEIVE SHIFT REGISTER RxDn RECOVERY CONTROL PARITY UDRn (Receive) CHECKER UCSRAn UCSRBn...
Page 179: Clock Generation
AT90CAN32/64/128 17.4 Clock Generation The Clock Generation logic generates the base clock for the Transmitter and Receiver. The USARTn supports four modes of clock operation: Normal asynchronous, Double Speed asyn- chronous, Master synchronous and Slave synchronous mode. The UMSELn bit in USARTn Control and Status Register C (UCSRnC) selects between asynchronous and synchronous operation.
Page 180 units use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the UMSELn, U2Xn and DDR_XCKn bits. Table 17-1 contains equations for calculating the baud rate (in bits per second) and for calculat- ing the UBRRn value for each mode of operation using an internally generated clock source.
Page 181 AT90CAN32/64/128 Note that depends on the stability of the system clock source. It is therefore recommended to add some margin to avoid possible loss of data due to frequency variations. 17.4.4 Synchronous Clock Operation When synchronous mode is used (UMSELn = 1), the XCKn pin will be used as either clock input (Slave) or clock output (Master).
Page 182: Usart Initialization
Figure 17-4. Frame Formats FRAME (IDLE) Sp1 [Sp2] (St / IDLE) Start bit, always low. Data bits (0 to 8). Parity bit. Can be odd or even. Stop bit, always high. IDLE No transfers on the communication line (RxDn or TxDn). An IDLE line must be high.
Page 183 AT90CAN32/64/128 check that there are no unread data in the receive buffer. Note that the TXCn flag must be cleared before each transmission (before UDRn is written) if it is used for this purpose. The following simple USART0 initialization code examples show one assembly and one C func- tion that are equal in functionality.
Page 184 chronous operation is used, the clock on the XCKn pin will be overridden and used as transmission clock. 17.7.1 Sending Frames with 5 to 8 Data Bit A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The CPU can load the transmit buffer by writing to the UDRn I/O location.
Page 185 AT90CAN32/64/128 17.7.2 Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZn = 7), the ninth bit must be written to the TXB8n bit in UCS- RnB before the low byte of the character is written to UDRn. The following code examples show a transmit function that handles 9-bit characters.
Page 186 The Data Register Empty (UDREn) flag indicates whether the transmit buffer is ready to receive new data. This bit is set when the transmit buffer is empty, and cleared when the transmit buffer contains data to be transmitted that has not yet been moved into the Shift Register. For compat- ibility with future devices, always write this bit to zero when writing the UCSRnA Register.
Page 187 AT90CAN32/64/128 The following code example shows a simple USART0 receive function based on polling of the Receive Complete (RXC0) flag. When using frames with less than eight bits the most significant bits of the data read from the UDR0 will be masked to zero. The USART0 has to be initialized before the function can be used.
Page 188 The following code example shows a simple USART0 receive function that handles both nine bit characters and the status bits. Assembly Code Example USART0_Receive: ; Wait for data to be received r18, UCSR0A sbrs r18, RXC0 rjmp USART0_Receive ; Get status and 9th bit, then data from buffer r17, UCSR0B r16, UDR0 ;...
Page 189 AT90CAN32/64/128 17.8.3 Receive Complete Flag and Interrupt The USARTn Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data).
Page 190: Asynchronous Data Reception
The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer (UDRn) is read. 17.8.6 Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate.
Page 191 AT90CAN32/64/128 izontal arrows illustrate the synchronization variation due to the sampling process. Note the larger time variation when using the Double Speed mode (U2Xn = 1) of operation. Samples denoted zero are samples done when the RxDn line is idle (i.e., no communication activity). Figure 17-5.
Page 192 Figure 17-7 shows the sampling of the stop bit and the earliest possible beginning of the start bit of the next frame. Figure 17-7. Stop Bit Sampling and Next Start Bit Sampling RxDn STOP 1 Sample (U2Xn = 0) Sample (U2Xn = 1) The same majority voting is done to the stop bit as done for the other bits in the frame.
Page 193: Multi-Processor Communication Mode
AT90CAN32/64/128 Table 17-2. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2Xn = 0) Recommended Max Max Total Error (%) slow fast # (Data + Parity Bit) Receiver Error (%) 93.20 106.67 +6.67/-6.8 ± 3.0 94.12 105.79 +5.79/-5.88 ±...
Page 194 17.10.1 MPCM Protocol If the Receiver is set up to receive frames that contain 5 to 8 data bits, then the first stop bit indi- cates if the frame contains data or address information. If the Receiver is set up for frames with nine data bits, then the ninth bit (RXB8n) is used for identifying address and data frames.
Page 195: Usart Register Description
AT90CAN32/64/128 17.11 USART Register Description 17.11.1 USART0 I/O Data Register – UDR0 RXB0[7:0] UDR0 (Read) TXB0[7:0] UDR0 (Write) Read/Write Initial Value 17.11.2 USART1 I/O Data Register – UDR1 RXB1[7:0] UDR1 (Read) TXB1[7:0] UDR1 (Write) Read/Write Initial Value • Bit 7:0 – RxBn7:0: Receive Data Buffer (read access) •...
Page 196 • Bit 6 – TXCn: USARTn Transmit Complete This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer (UDRn). The TXCn flag bit is auto- matically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location.
Page 197 AT90CAN32/64/128 17.11.6 USART1 Control and Status Register B – UCSR1B RXCIE1 TXCIE1 UDRIE1 RXEN1 TXEN1 UCSZ12 RXB81 TXB81 UCSR1B Read/Write Initial Value • Bit 7 – RXCIEn: RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXCn flag. A USARTn Receive Complete inter- rupt will be generated only if the RXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the RXCn bit in UCSRnA is set.
Page 198 17.11.8 USART1 Control and Status Register C – UCSR1C – UMSEL1 UPM11 UPM10 USBS1 UCSZ11 UCSZ10 UCPO1L UCSR1C Read/Write Initial Value • Bit 7 – Reserved Bit This bit is reserved for future use. For compatibility with future devices, these bit must be written to zero when UCSRnC is written.
Page 199 AT90CAN32/64/128 • Bit 2:1 – UCSZn1:0: Character Size The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits (Character SiZe) in a frame the Receiver and Transmitter use. Table 17-7. UCSZn Bits Settings UCSZn2 UCSZn1 UCSZn0 Character Size...
Page 200: Examples Of Baud Rate Setting
• Bit 15:12 – Reserved Bits These bits are reserved for future use. For compatibility with future devices, these bit must be written to zero when UBRRnH is written. • Bit 11:0 – UBRRn11:0: USARTn Baud Rate Register This is a 12-bit register which contains the USARTn baud rate. The UBRRnH contains the four most significant bits, and the UBRRnL contains the eight least significant bits of the USARTn baud rate.
Page 201 AT90CAN32/64/128 Table 17-10. Examples of UBRRn Settings for Commonly Frequencies (Continued) = 3.6864 MHz = 4.0000 MHz = 7.3728 MHz Baud Rate U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 (bps) UBRRn Error...
Page 202 Table 17-11. Examples of UBRRn Settings for Commonly Frequencies (Continued) 10.000 11.0592 = 8.0000 MHz Baud Rate U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 (bps) UBRRn Error UBRRn Error UBRRn Error UBRRn...
Page 203 AT90CAN32/64/128 Table 17-12. Examples of UBRRn Settings for Commonly Frequencies (Continued) = 12.0000 MHz = 14.7456 MHz = 16.0000 MHz Baud Rate U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 (bps) UBRRn Error...
Page 204: Two-Wire Serial Interface
18. Two-wire Serial Interface 18.1 Features • Simple yet Powerful and Flexible Communication Interface, only Two Bus Lines Needed • Both Master and Slave Operation Supported • Device can Operate as Transmitter or Receiver • 7-bit Address Space allows up to 128 Different Slave Addresses •...
Page 205: Data Transfer And Frame Format
AT90CAN32/64/128 18.2.2 Electrical Interconnection As depicted in Figure 18-1, both bus lines are connected to the positive supply voltage through pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector. This implements a wired-AND function which is essential to the operation of the interface. A low level on a TWI bus line is generated when one or more TWI devices output a zero.
Page 206 Figure 18-3. START, REPEATED START and STOP Conditions START STOP START REPEATED START STOP 18.3.3 Address Packet Format All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 address bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read opera- tion is to be performed, otherwise a write operation should be performed.
Page 207: Multi-Master Bus Systems, Arbitration And Synchronization
AT90CAN32/64/128 Acknowledge (ACK) is signalled by the receiver pulling the SDA line low during the ninth SCL cycle. If the receiver leaves the SDA line high, a NACK is signalled. When the receiver has received the last byte, or for some reason cannot receive any more bytes, it should inform the transmitter by sending a NACK after the final byte.
Page 208 • An algorithm must be implemented allowing only one of the masters to complete the transmission. All other masters should cease transmission when they discover that they have lost the selection process. This selection process is called arbitration. When a contending master discovers that it has lost the arbitration process, it should immediately switch to slave mode to check whether it is being addressed by the winning master.
Page 209: Overview Of The Twi Module
AT90CAN32/64/128 Figure 18-8. Arbitration Between two Masters START Master A loses Arbitration, SDA SDA from Master A SDA from Master B SDA Line Synchronized SCL Line Note that arbitration is not allowed between: • A REPEATED START condition and a data bit •...
Page 210 Figure 18-9. Overview of the TWI Module Slew-rate Spike Slew-rate Spike Control Filter Control Filter Bus Interface Unit Bit Rate Generator START / STOP Spike Suppression Prescaler Control Address/Data Shift Bit Rate Register Arbitration detection Register (TWDR) (TWBR) Address Match Unit Control Unit Address Register Status Register...
Page 211 AT90CAN32/64/128 18.5.3 Bus Interface Unit This unit contains the Data and Address Shift Register (TWDR), a START/STOP Controller and Arbitration detection hardware. The TWDR contains the address or data bytes to be transmitted, or the address or data bytes received. In addition to the 8-bit TWDR, the Bus Interface Unit also contains a register containing the (N)ACK bit to be transmitted or received.
Page 212: Twi Register Description
• When a bus error has occurred due to an illegal START or STOP condition 18.6 TWI Register Description 18.6.1 TWI Bit Rate Register – TWBR TWBR7 TWBR6 TWBR5 TWBR4 TWBR3 TWBR2 TWBR1 TWBR0 TWBR Read/Write Initial Value • Bits 7.0 – TWI Bit Rate Register TWBR selects the division factor for the bit rate generator.
Page 213 AT90CAN32/64/128 The application writes the TWSTA bit to one when it desires to become a master on the Two- wire Serial Bus. The TWI hardware checks if the bus is available, and generates a START con- dition on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP condition is detected, and then generates a new START condition to claim the bus Master status.
Page 214 • Bits 1.0 – TWPS: TWI Prescaler Bits These bits can be read and written, and control the bit rate prescaler. Table 18-2. TWI Bit Rate Prescaler TWPS1 TWPS0 Prescaler Value To calculate bit rates, see “Bit Rate Generator Unit” on page 210.
Page 215: Using The Twi
AT90CAN32/64/128 TWGCE is used to enable recognition of the general call address (0x00). There is an associated address comparator that looks for the slave address (or general call address if enabled) in the received serial address. If a match is found, an interrupt request is generated. If set, this bit enables the recognition of a General Call given over the TWI Serial Bus.
Page 216 the application has cleared TWINT, the TWI will initiate transmission of the START condition. 2. When the START condition has been transmitted, the TWINT flag in TWCR is set, and TWSR is updated with a status code indicating that the START condition has success- fully been sent.
Page 217 AT90CAN32/64/128 • When the TWINT flag is set, the user must update all TWI Registers with the value relevant for the next TWI bus cycle. As an example, TWDR must be loaded with the value to be transmitted in the next bus cycle. •...
Page 218: Transmission Modes
18.8 Transmission Modes The TWI can operate in one of four major modes. These are named Master Transmitter (MT), Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these modes can be used in the same application. As an example, the TWI can use MT mode to write data into a TWI EEPROM, MR mode to read the data back from the EEPROM.
Page 219 AT90CAN32/64/128 Figure 18-11. Data Transfer in Master Transmitter Mode Device 1 Device 2 ..Device 3 Device n MASTER SLAVE TRANSMITTER RECEIVER A START condition is sent by writing the following value to TWCR: TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN –...
Page 220 After a repeated START condition (state 0x10) the Two-wire Serial Interface can access the same slave again, or a new slave without transmitting a STOP condition. Repeated START enables the master to switch between slaves, Master Transmitter mode and Master Receiver mode without losing control of the bus.
Page 221 AT90CAN32/64/128 Figure 18-12. Formats and States in the Master Transmitter Mode Successfull DATA transmission to a slave receiver 0x08 0x18 0x28 Next transfer started with a repeated start condition 0x10 Not acknowledge received after the slave address 0x20 Not acknowledge received after a data byte 0x30...
Page 222 18.8.2 Master Receiver Mode In the Master Receiver Mode, a number of data bytes are received from a slave transmitter (see Figure 18-13). In order to enter a Master mode, a START condition must be transmitted. The for- mat of the following address packet determines whether Master Transmitter or Master Receiver mode is to be entered.
Page 223 AT90CAN32/64/128 A REPEATED START condition is generated by writing the following value to TWCR: TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE value After a repeated START condition (state 0x10) the Two-wire Serial Interface can access the same slave again, or a new slave without transmitting a STOP condition. Repeated START enables the master to switch between slaves, Master Transmitter mode and Master Receiver mode without losing control over the bus.
Page 224: Slave Receiver Mode
Table 18-4. Status Codes for Master Receiver Mode Status Code Application Software Response Status of the Two-wire Serial Bus (TWSR) To TWCR and Two-wire Serial Interface Next Action Taken by TWI Hardware Prescaler Bits To/from TWDR Hardware TWINT TWEA are 0 0x08 A START condition has been Load SLA+R...
Page 225 AT90CAN32/64/128 To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows: TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE value Device’s Own Slave Address The upper seven bits are the address to which the Two-wire Serial Interface will respond when addressed by a master.
Page 226 Table 18-5. Status Codes for Slave Receiver Mode Status Code Application Software Response Status of the Two-wire Serial Bus (TWSR) To TWCR and Two-wire Serial Interface Hard- Next Action Taken by TWI Hardware Prescaler Bits To/from TWDR ware TWINT TWEA are 0 0x60 Own SLA+W has been received;...
Page 227 AT90CAN32/64/128 Figure 18-16. Formats and States in the Slave Receiver Mode Reception of the DATA DATA P or S own slave address and one or more data bytes. All are acknowledged 0x60 0x80 0x80 0xA0 Last data byte received P or S is not acknowledged 0x88 Arbitration lost as master...
Page 228 18.8.4 Slave Transmitter Mode In the Slave Transmitter mode, a number of data bytes are transmitted to a master receiver (see Figure 18-17). All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. Figure 18-17.
Page 229 AT90CAN32/64/128 While TWEA is zero, the TWI does not respond to its own slave address. However, the Two-wire Serial Bus is still monitored and address recognition may resume at any time by setting TWEA. This implies that the TWEA bit may be used to temporarily isolate the TWI from the Two-wire Serial Bus.
Page 230 Figure 18-18. Formats and States in the Slave Transmitter Mode Reception of the DATA DATA P or S own slave address and one or more data bytes 0xA8 0xB8 0xC0 Arbitration lost as master and addressed as slave 0xB0 Last data byte transmitted. All 1’s P or S Switched to not addressed...
Page 231 AT90CAN32/64/128 18.8.6 Combining Several TWI Modes In some cases, several TWI modes must be combined in order to complete the desired action. Consider for example reading data from a serial EEPROM. Typically, such a transfer involves the following steps: 1. The transfer must be initiated 2.
Page 232: Multi-Master Systems And Arbitration
18.9 Multi-master Systems and Arbitration If multiple masters are connected to the same bus, transmissions may be initiated simulta- neously by one or more of them. The TWI standard ensures that such situations are handled in such a way that one of the masters will be allowed to proceed with the transfer, and that no data will be lost in the process.
Page 233 AT90CAN32/64/128 This is summarized in Figure 18-21. Possible status values are given in circles. Figure 18-21. Possible Status Codes Caused by Arbitration START Data STOP Arbitration lost in SLA Arbitration lost in Data 0x38 TWI bus will be released and not addressed slave mode will be entered Address / General Call A START condition will be transmitted when the bus becomes free received...
Page 234: Controller Area Network - Can
19. Controller Area Network - CAN The Controller Area Network (CAN) protocol is a real-time, serial, broadcast protocol with a very high level of security. The AT90CAN32/64/128 CAN controller is fully compatible with the CAN Specification 2.0 Part A and Part B. It delivers the features required to implement the kernel of the CAN bus protocol according to the ISO/OSI Reference Model: •...
Page 235: Message Formats
AT90CAN32/64/128 by which the dominant state overwrites the recessive state. The competition for bus allocation is lost by all nodes with recessive transmission and dominant observation. All the "losers" automat- ically become receivers of the message with the highest priority and do not re-attempt transmission until the bus is available again.
Page 236 19.2.2.2 CAN Extended Frame Figure 19-2. CAN Extended Frames Data Frame Bus Idle 11-bit base identifier 18-bit identifier extension 4-bit DLC Intermission Bus Idle SRR IDE 15-bit CRC 7 bits 0 - 8 bytes IDT28..18 ID17..0 DLC4..0 del. del. 3 bits (Indefinite) Interframe Arbitration...
Page 237 AT90CAN32/64/128 Figure 19-3. CAN Bit Construction CAN Frame (producer) Transmission Point (producer) Nominal CAN Bit Time Time Quantum (producer) Segments SYNC_SEG PROP_SEG PHASE_SEG_1 PHASE_SEG_2 (producer) propagation delay Segments SYNC_SEG PROP_SEG PHASE_SEG_1 PHASE_SEG_2 (consumer) Sample Point 19.2.3.2 Synchronization Segment The first segment is used to synchronize the various bus nodes. On transmission, at the start of this segment, the current bit level is output.
Page 238 The IPT begins at the sample point, is measured in TQ and is fixed at 2TQ for the Atmel CAN. Since Phase Segment 2 also begins at the sample point and is the last segment in the bit time, PS2 minimum shall not be less than the IPT.
Page 239 AT90CAN32/64/128 Figure 19-4. Bus Arbitration Arbitration lost node A TXCAN Node A loses the bus Node B wins the bus node B TXCAN CAN bus ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR IDE - - - - - - - - - 19.2.5 Errors The CAN protocol signals any errors immediately as they occur.
Page 240: Can Controller
19.3 CAN Controller The CAN controller implemented into AT90CAN32/64/128 offers V2.0B Active. This full-CAN controller provides the whole hardware for convenient acceptance filtering and message management. For each message to be transmitted or received this module contains one so called message object in which all information regarding the message (e.g. identifier, data bytes etc.) are stored.
Page 241: Can Channel
AT90CAN32/64/128 19.4 CAN Channel 19.4.1 Configuration The CAN channel can be in: • Enabled mode In this mode: – the CAN channel (internal TxCAN & RxCAN) is enabled, – the input clock is enabled. • Standby mode In standby mode: –...
Page 242: Bit Timing
The total number of TQ in a bit time has to be programmed at least from 8 to 25. Figure 19-7. Sample and Transmission Point Bit Timing PRS (3-bit length) Sample PHS1 (3-bit length) Point Fcan (Tscl) Prescaler BRP Time Quantum Transmission PHS2 (3-bit length) Point...
Page 243: Message Objects
AT90CAN32/64/128 5. Tsjw = (1 to 4) x Tscl = (SJW[1..0]+ 1) x Tscl Notes: 1. The total number of Tscl (Time Quanta) in a bit time must be from 8 to 25. ≤ ≥ 2. PHS2[2..0] 2 is programmable to be PHS1[2..0] and 19.4.4 Fault Confinement...
Page 244 19.5.2 Operating Modes There is no default mode after RESET. Every MOb has its own fields to control the operating mode. Before enabling the CAN periph- eral, each MOb must be configured (ex: disabled mode - CONMOB=00). Table 19-1. MOb Configuration MOb Configuration Reply Valid RTR Tag...
Page 245 AT90CAN32/64/128 2. The MOb is ready to receive a data or a remote frame when the MOb configuration is set (CONMOB). 3. When a frame identifier is received on CAN network, the CAN channel scans all the MObs in receive mode, tries to find the MOb having the highest priority which is matching.
Page 246 19.5.3 Acceptance Filter Upon a reception hit (i.e., a good comparison between the ID + RTR + RBn + IDE received and an IDT+ RTRTAG + RBnTAG + IDE specified while taking the comparison mask into account) the IDT + RTRTAG + RBnTAG + IDE received are updated in the MOb (written over the registers). Figure 19-10.
Page 247 AT90CAN32/64/128 The data index (INDX) is the address pointer to the required data byte. The data byte can be read or write. The data index is automatically incremented after every access if the AINC* bit is reset. A roll-over is implemented, after data index=7 it is data index=0. The first byte of a CAN frame is stored at the data index=0, the second one at the data index=1, 19.6 CAN Timer...
Page 248: Error Management
19.7 Error Management 19.7.1 Fault Confinement The CAN channel may be in one of the three following states: • Error active (default): The CAN channel takes part in bus communication and can send an active error frame when the CAN macro detects an error. •...
Page 249 AT90CAN32/64/128 – end-of-frame – error delimiter – overload delimiter • AERR: Acknowledgment error (Tx only). No detection of the dominant bit in the acknowledge slot. Figure 19-13. Error Detection Procedures in a Data Frame Arbitration Bit error Stuff error Form error ACK error Identifier Control...
Page 250 Figure 19-14. CAN Controller Interrupt Structure CANGIE.4 CANGIE.5 CANGIE.3 ENTX ENRX ENERR CANSIT 1/2 SIT[i] CANSTMOB.6 TXOK[i] CANIE 1/2 CANSTMOB.5 RXOK[i] IEMOB[i] CANSTMOB.4 BERR[i] CANSTMOB.3 SERR[i] CANGIT.7 CANSTMOB.2 CERR[i] CANIT CANSTMOB.1 FERR[i] CANGIE.7 CANGIE.2 CANGIE.1 CANGIE.6 CANSTMOB.0 AERR[i] ENIT ENBX ENERG ENBOFF CANGIT.4...
Page 251 AT90CAN32/64/128 19.9 CAN Register Description Figure 19-15. Registers Organization AVR Registers Registers in Pages General Control General Status General Interrupt Bit Timing 1 Bit Timing 2 Bit Timing 3 Enable MOb 2 Enable MOb 1 Enable Interrupt Enable Interrupt MOb 2 Enable Interrupt MOb 1 Status Interrupt MOb 2 Status Interrupt MOb 1...
Page 252 19.10 General CAN Registers 19.10.1 CAN General Control Register - CANGCON ABRQ OVRQ SYNTTC LISTEN TEST ENA/STB SWRES CANGCON Read/Write Initial Value • Bit 7 – ABRQ: Abort Request This is not an auto resettable bit. – 0 - no request. –...
Page 253 AT90CAN32/64/128 – 0 - standby mode: The on-going transmission (if exists) is normally terminated and the CAN channel is frozen (the CONMOB bits of every MOb do not change). The transmitter constantly provides a recessive level. In this mode, the receiver is not enabled but all the registers and mailbox remain accessible from CPU.
Page 254 This flag does not generate an interrupt. – 0 - CAN controller disable: because an enable/standby command is not immediately effective, this status gives the true state of the chosen mode. – 1 - CAN controller enable. • Bit 1 – BOFF: Bus Off Mode BOFF gives the information of the state of the CAN channel.
Page 255 AT90CAN32/64/128 – 1 - burst receive interrupt: set when the frame buffer receive is completed. • Bit 3 – SERG: Stuff Error General Writing a logical one resets this interrupt flag. – 0 - no interrupt. – 1 - stuff error interrupt: detection of more than 5 consecutive bits with the same polarity.
Page 256 – 1- transmit interrupt enabled. • Bit 3 – ENERR: Enable MOb Errors Interrupt – 0 - interrupt disabled. – 1- MOb errors interrupt enabled. • Bit 2 – ENBX: Enable Frame Buffer Interrupt – 0 - interrupt disabled. – 1- frame buffer interrupt enabled. •...
Page 257 AT90CAN32/64/128 19.10.6 CAN Enable Interrupt MOb Registers - CANIE2 and CANIE1 IEMOB7 IEMOB6 IEMOB5 IEMOB4 IEMOB3 IEMOB2 IEMOB1 IEMOB0 CANIE2 IEMOB14 IEMOB13 IEMOB12 IEMOB11 IEMOB10 IEMOB9 IEMOB8 CANIE1 Read/Write Initial Value Read/Write Initial Value • Bits 14:0 - IEMOB14:0: Interrupt Enable by MOb –...
Page 258 The period of the CAN controller system clock Tscl is programmable and determines the individ- ual bit timing. BRP[5:0] + 1 Tscl = frequency If BRP[5..0]=0, see Section 19.4.3 ”Baud Rate” on page 242 Section • ”Bit 0 – SMP: Sample Point(s)”...
Page 259 AT90CAN32/64/128 • Bit 7– Reserved Bit This bit is reserved for future use. For compatibility with future devices, it must be written to zero when CANBT3 is written. • Bit 6:4 – PHS22:0: Phase Segment 2 This phase is used to compensate for phase edge errors. This segment may be shortened by the re-synchronization jump width.
Page 260 19.10.13 CAN TTC Timer Registers - CANTTCL and CANTTCH TIMTTC7 TIMTTC6 TIMTTC5 TIMTTC4 TIMTTC3 TIMTTC2 TIMTTC1 TIMTTC0 CANTTCL TIMTTC15 TIMTTC14 TIMTTC13 TIMTTC12 TIMTTC11 TIMTTC10 TIMTTC9 TIMTTC8 CANTTCH Read/Write Initial Value • Bits 15:0 - TIMTTC15:0: TTC Timer Count CAN TTC timer counter range 0 to 65,535. 19.10.14 CAN Transmit Error Counter Register - CANTEC TEC7 TEC6...
Page 261 AT90CAN32/64/128 • Bit 7:4 – MOBNB3:0: MOb Number Selection of the MOb number, the available numbers are from 0 to 14. • Bit 3 – AINC: Auto Increment of the FIFO CAN Data Buffer Index (Active Low) – 0 - auto increment of the index (default value). –...
Page 262 The rising of this flag does not disable the MOb (the corresponding ENMOB-bit of CANEN regis- ters is not cleared). The next matching frame will update the BERR flag. • Bit 3 – SERR: Stuff Error This flag can generate an interrupt. It must be cleared using a read-modify-write software routine on the whole CANSTMOB register.
Page 263 AT90CAN32/64/128 – 00 - disable. – 01 - enable transmission. – 10 - enable reception. – 11 - enable frame buffer reception These bits are not cleared once the communication is performed. The user must re-write the configuration to enable a new communication. •...
Page 264 31/23 30/22 29/21 28/20 27/19 26/18 25/17 24/16 Read/Write Initial Value V2.0 part A • Bit 31:21 – IDT10:0: Identifier Tag Identifier field of the remote or data frame to send. This field is updated with the corresponding value of the remote or data frame received. •...
Page 265 AT90CAN32/64/128 • Bit 0 – RB0TAG: Reserved Bit 0 Tag RB0 bit of the remote or data frame to send. This tag is updated with the corresponding value of the remote or data frame received. 19.11.4 CAN Identifier Mask Registers - CANIDM1, CANIDM2, CANIDM3, and CANIDM4 V2.0 part A 15/7...
Page 266 • Bit 31:3 – IDMSK28:0: Identifier Mask – 0 - comparison true forced - See “Acceptance Filter” on page 246. – 1 - bit comparison enabled - See “Acceptance Filter” on page 246. • Bit 2 – RTRMSK: Remote Transmission Request Mask –...
Page 267 AT90CAN32/64/128 Table 19-2. Examples of CAN Baud Rate Settings for Commonly Frequencies Description Segments Registers Baudrate Sampling Tbit Tprs Tph1 Tph2 Tsjw (MHz) (Kbps) Point (µs) (TQ) (TQ) (TQ) (TQ) (TQ) CANBT1 CANBT2 CANBT3 69 % 0.0625 0x00 0x0C 0x36 1000 75 % 0.125...
Page 268 Table 19-2. Examples of CAN Baud Rate Settings for Commonly Frequencies (Continued) Description Segments Registers Baudrate Sampling Tbit Tprs Tph1 Tph2 Tsjw (MHz) (Kbps) Point (µs) (TQ) (TQ) (TQ) (TQ) (TQ) CANBT1 CANBT2 CANBT3 - - - n o d a t a - - - 1000 63 % 0.125...
Page 269: Analog Comparator Register Description
AT90CAN32/64/128 20. Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. 20.1 Overview When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set.
Page 270 20.2.2 Analog Comparator Control and Status Register – ACSR ACBG ACIE ACIC ACIS1 ACIS0 ACSR Read/Write Initial Value • Bit 7 – ACD: Analog Comparator Disable When this bit is written logic one, the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the Analog Comparator.
Page 271: Analog Comparator Multiplexed Input
AT90CAN32/64/128 • Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in Table 20-1. Table 20-1. ACIS1/ACIS0 Settings ACIS1 ACIS0 Interrupt Mode Comparator Interrupt on Output Toggle.
Page 272 20.3.1 Digital Input Disable Register 1 – DIDR1 – – – – – – AIN1D AIN0D DIDR1 Read/Write Initial Value • Bit 1, 0 – AIN1D, AIN0D: AIN1, AIN0 Digital Input Disable When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corre- sponding PIN Register bit will always read as zero when this bit is set.
Page 273: Analog To Digital Converter - Adc
AT90CAN32/64/128 21. Analog to Digital Converter - ADC 21.1 Features • 10-bit Resolution • 0.5 LSB Integral Non-linearity • ± 2 LSB Absolute Accuracy • 65 - 260 µs Conversion Time • Up to 15 kSPS at Maximum Resolution • Eight Multiplexed Single Ended Input Channels •...
Page 274: Operation
Figure 21-1. Analog to Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[2:0] 8-BIT DATA BUS ADC MULTIPLEXER ADC CTRL. & ST ATUS ADC DATA REGISTER SELECT (ADMUX) REGISTER (ADCSRA) (ADCH/ADCL) TRIGGER SELECT MUX DECODER PRESCALER CONVERSION LOGIC AVCC INTERNAL REFERENCE...
Page 275: Starting A Conversion
AT90CAN32/64/128 the AREF pin minus 1 LSB. Optionally, AV or an internal 2.56V reference voltage may be con- nected to the AREF pin by writing to the REFSn bits in the ADMUX Register. The internal voltage reference may thus be decoupled by an external capacitor at the AREF pin to improve noise immunity.
Page 276: Prescaling And Conversion Timing
Figure 21-2. ADC Auto Trigger Logic ADTS[2:0] PRESCALER START ADIF ADATE SOURCE 1 CONVERSION LOGIC EDGE DETECTOR SOURCE n ADSC Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, con- stantly sampling and updating the ADC Data Register.
Page 277 AT90CAN32/64/128 When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle. See “Differential Channels” on page for details on differential conversion timing. A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry.
Page 278 Figure 21-6. ADC Timing Diagram, Auto Triggered Conversion One Conversion Next Conversion Cycle Number ADC Clock Trigger Source ADATE ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample & Prescaler Conversion Prescaler Hold Reset Complete Reset MUX and REFS Update Figure 21-7.
Page 279: Changing Channel Or Reference Selection
AT90CAN32/64/128 initiated immediately after the previous conversion completes, and since CK is high at this ADC2 time, all automatically started (i.e., all but the first) Free Running conversions will take 14 ADC clock cycles. If differential channels are used and conversions are started by Auto Triggering, the ADC must be switched off between conversions.
Page 280: Adc Noise Canceler
21.5.1 ADC Input Channels When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: • In Single Conversion mode, always select the channel before starting the conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the conversion to complete before changing the channel selection.
Page 281 AT90CAN32/64/128 another interrupt wakes up the CPU before the ADC conversion is complete, that inter- rupt will be executed, and an ADC Conversion Complete interrupt request will be generated when the ADC conversion completes. The CPU will remain in active mode until a new sleep command is executed.
Page 282 1. Keep analog signal paths as short as possible. Make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digital tracks. 2. The AV pin on the device should be connected to the digital V supply voltage via an LC network as shown in Figure...
Page 283 AT90CAN32/64/128 Figure 21-10. Offset Error Output Code Ideal ADC Actual ADC Offset Error Input Voltage • Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 21-11.
Page 284: Adc Conversion Result
Figure 21-12. Integral Non-linearity (INL) Output Code Ideal ADC Actual ADC Input Voltage • Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 21-13.
Page 285 AT90CAN32/64/128 For single ended conversion, the result is: ⋅ 1023 -------------------------- where V is the voltage on the selected input pin and V the selected voltage reference (see Table 21-3 on page 287 Table 21-4 on page 288). 0x000 represents analog ground, and 0x3FF represents the selected reference voltage minus one LSB.
Page 286 Table 21-2. Correlation Between Input Voltage and Output Codes Read code Corresponding decimal value ADCn /GAIN 0x1FF ADCm + 0.999 V /GAIN 0x1FF ADCm + 0.998 V /GAIN 0x1FE ADCm + 0.001 V /GAIN 0x001 ADCm 0x000 ADCm - 0.001 V /GAIN 0x3FF ADCm...
Page 287: Adc Register Description
AT90CAN32/64/128 21.8 ADC Register Description 21.8.1 ADC Multiplexer Selection Register – ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 ADMUX Read/Write Initial Value • Bit 7:6 – REFS1:0: Reference Selection Bits These bits select the voltage reference for the ADC, as shown in Table 21-3.
Page 288 Table 21-4. Input Channel and Gain Selections Single Ended Positive Differential Negative Differential MUX4..0 Gain Input Input Input 00000 ADC0 00001 ADC1 00010 ADC2 00011 ADC3 00100 ADC4 00101 ADC5 00110 ADC6 00111 ADC7 01000 (ADC0 / ADC0 / 10x) 01001 ADC1 ADC0...
Page 289 AT90CAN32/64/128 21.8.2 ADC Control and Status Register A – ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 ADCSRA Read/Write Initial Value • Bit 7 – ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.
Page 290 • Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. Table 21-5. ADC Prescaler Selections ADPS2 ADPS1 ADPS0 Division Factor 21.8.3 The ADC Data Register – ADCL and ADCH ADLAR = 0 –...
Page 291 AT90CAN32/64/128 • ADC9:0: ADC Conversion Result These bits represent the result from the conversion, as detailed in “ADC Conversion Result” on page 284. 21.8.4 ADC Control and Status Register B – ADCSRB – ACME – – – ADTS2 ADTS1 ADTS0 ADCSRB Read/Write Initial Value...
Page 292 21.8.5 Digital Input Disable Register 0 – DIDR0 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D DIDR0 Read/Write Initial Value • Bit 7:0 – ADC7D..ADC0D: ADC7:0 Digital Input Disable When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis- abled.
Page 293: Jtag Interface And On-Chip Debug System
300, respectively. The On-chip Debug support is considered being private JTAG instructions, and dis- tributed within ATMEL and to selected third party vendors only. Figure 22-1 shows a block diagram of the JTAG interface and the On-chip Debug system. The TAP Controller is a state machine controlled by the TCK and TMS signals.
Page 294 • TCK: Test Clock. JTAG operation is synchronous to TCK. • TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register (Scan Chains). • TDO: Test Data Out. Serial output data from Instruction Register or Data Register (Scan Chains).
Page 295 AT90CAN32/64/128 Figure 22-1. Block Diagram I/O PORT 0 DEVICE BOUNDARY BOUNDARY SCAN CHAIN JTAG PROGRAMMING INTERFACE CONTROLLER INTERNAL FLASH Address SCAN INSTRUCTION MEMORY Data Instruction CHAIN REGISTER AVR CPU REGISTER BREAKPOINT UNIT FLOW CONTROL BYPASS UNIT REGISTER DIGITAL ANALOG PERIPHERAL PERIPHERIAL UNITS UNITS...
Page 296: Tap Controller
Figure 22-2. TAP Controller State Diagram Test-Logic-Reset Run-Test/Idle Select-DR Scan Select-IR Scan Capture-DR Capture-IR Shift-DR Shift-IR Exit1-DR Exit1-IR Pause-DR Pause-IR Exit2-DR Exit2-IR Update-DR Update-IR 22.4 TAP Controller The TAP controller is a 16-state finite state machine that controls the operation of the Boundary- scan circuitry, JTAG programming circuitry, or On-chip Debug system.
Page 297: Using The Boundary-Scan Chain
AT90CAN32/64/128 • Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched onto the parallel output from the Shift Register path in the Update-IR state. The Exit-IR, Pause-IR, and Exit2-IR states are only used for navigating the state machine. •...
Page 298: On-Chip Debug Specific Jtag Instructions
22.7 On-chip Debug Specific JTAG Instructions The On-chip debug support is considered being private JTAG instructions, and distributed within ATMEL and to selected third party vendors only. Instruction opcodes are listed for reference. 22.7.1 PRIVATE0 (0x8) Private JTAG instruction for accessing On-chip debug system.
Page 299: On-Chip Debug Related Register In I/O Memory
AT90CAN32/64/128 22.8 On-chip Debug Related Register in I/O Memory 22.8.1 On-chip Debug Register – OCDR IDRD/OCDR7 OCDR6 OCDR5 OCDR4 OCDR3 OCDR2 OCDR1 OCDR0 OCDR Read/Write Initial Value The OCDR Register provides a communication channel from the running program in the micro- controller to the debugger.
Page 300: System Overview
23. Boundary-scan IEEE 1149.1 (JTAG) 23.1 Features • JTAG (IEEE std. 1149.1 compliant) Interface • Boundary-scan Capabilities According to the JTAG Standard • Full Scan of all Port Functions as well as Analog Circuitry having Off-chip Connections • Supports the Optional IDCODE Instruction •...
Page 301 0x9581 AT90CAN64 0x9681 AT90CAN128 0x9781 23.3.2.3 Manufacturer ID The Manufacturer ID is a 11-bit code identifying the manufacturer. The JTAG manufacturer ID for ATMEL is listed in Table 23-3. Table 23-3. Manufacturer ID Manufacturer JTAG Manufacturer ID (Hex) ATMEL 0x01F...
Page 302: Boundary-Scan Specific Jtag Instructions
23.3.2.4 Device ID The full Device ID is listed in Table 23-4 following the AT90CAN32/64/128 version. Table 23-4. Device ID Version JTAG Device ID (Hex) AT90CAN32 revision A 0x0958103F AT90CAN64 revision A 0x0968103F AT90CAN128 revision A 0x0978103F 23.3.3 Reset Register The Reset Register is a test data register used to reset the part.
Page 303 AT90CAN32/64/128 23.4.1 EXTEST (0x0) Mandatory JTAG instruction for selecting the Boundary-scan Chain as data register for testing circuitry external to the AVR package. For port-pins, Pull-up Disable, Output Control, Output Data, and Input Data are all accessible in the scan chain. For Analog circuits having off-chip connections, the interface between the analog and the digital logic is in the scan chain.
Page 304: Boundary-Scan Related Register In I/O Memory
• Shift-DR: The Bypass Register cell between TDI and TDO is shifted. 23.5 Boundary-scan Related Register in I/O Memory 23.5.1 MCU Control Register – MCUCR The MCU Control Register contains control bits for general MCU functions. – – – – IVSEL IVCE MCUCR...
Page 305 AT90CAN32/64/128 When no alternate port function is present, the Input Data – ID – corresponds to the PINxn Reg- ister value (but ID has no synchronizer), Output Data corresponds to the PORT Register, Output Control corresponds to the Data Direction – DD Register, and the Pull-up Enable – PUExn – cor- responds to logic expression PUD ·...
Page 306 Figure 23-4. General Port Pin Schematic Diagram See Boundary-scan Description for Details! PUExn DDxn RESET OCxn ODxn PORTxn IDxn RESET SLEEP SYNCHRONIZER PINxn PUD: PULLUP DISABLE WDx: WRITE DDRx PUExn: PULLUP ENABLE for pin Pxn RDx: READ DDRx OCxn: OUTPUT CONTROL for pin Pxn WPx: WRITE PORTx ODxn:...
Page 307 AT90CAN32/64/128 Figure 23-5. Additional Scan Signal for the Two-wire Interface PUExn OCxn ODxn TWIEN Slew-rate limited IDxn 23.6.3 Scanning the RESET Pin The RESET pin accepts 3V or 5V active low logic for standard reset operation, and 12V active high logic for High Voltage Parallel programming. An observe-only cell as shown in Figure 23-6 is inserted both for the 3V or 5V reset signal - RSTT, and the 12V reset signal - RSTHV.
Page 308 Figure 23-7. Boundary-scan Cells for Oscillators and Clock Options XTAL1 / TOSC1 XTAL2 / TOSC2 Next Oscillator ShiftDR Cell EXTEST Next ShiftDR Cell From Digital Logic ENABLE OUTPUT To System Logic From ClockDR UpdateDR Previous From ClockDR Cell Previous Cell Table 23-5 summaries the scan registers for the external clock pin XTAL1, oscillators with XTAL1/XTAL2 connections as well as external Timer2 clock pin TOSC1 and 32kHz Timer2...
Page 309 AT90CAN32/64/128 Figure 23-8. Analog Comparator BANDGAP REFERENCE ACBG AC_IDLE ACME ADCEN ADC MULTIPLEXER OUTPUT Figure 23-9. General Boundary-scan cell Used for Signals for Comparator and ADC Next ShiftDR Cell EXTEST From Digital Logic/ From Analog Ciruitry To Analog Circuitry/ To Digital Logic From ClockDR UpdateDR...
Page 310: Scanning The Adc
23.6.6 Scanning the ADC Figure 23-10 shows a block diagram of the ADC with all relevant control and observe signals. The Boundary-scan cell from Figure 23-9 is attached to each of these signals. The ADC need not be used for pure connectivity testing, since all analog inputs are shared with a digital port pin as well.
Page 311 AT90CAN32/64/128 Table 23-7. Boundary-scan Signals for the ADC Direction Output Values when Recommended Signal as Seen Recommended Inputs Description Input Name from the are Used, and CPU is when not in use not Using the ADC COMP Output Comparator Output Clock signal to gain ACLK Input...
Page 312 Table 23-7. Boundary-scan Signals for the ADC (Continued) Direction Output Values when Recommended Signal as Seen Recommended Inputs Description Input Name from the are Used, and CPU is when not in use not Using the ADC Ground the negative GNDEN Input input to comparator when true...
Page 313 AT90CAN32/64/128 Table 23-7. Boundary-scan Signals for the ADC (Continued) Direction Output Values when Recommended Signal as Seen Recommended Inputs Description Input Name from the are Used, and CPU is when not in use not Using the ADC Switch-cap TEST enable. Output from x10 SCTEST Input gain stage send out to...
Page 314 The recommended values from Table 23-7 are used unless other values are given in the algo- rithm in Table 23-8. Only the DAC and port pin values of the Scan Chain are shown. The column “Actions” describes what JTAG instruction to be used before filling the Boundary-scan Register with the succeeding columns.
Page 315 AT90CAN32/64/128 corresponds to FF1, and PXn. Pullup_enable corresponds to FF2. Bit 2, 3, 4, and 5 of Port C is not in the scan chain, since these pins constitute the TAP pins when the JTAG is enabled. Table 23-9. AT90CAN32/64/128 Boundary-scan Order Bit Number Signal Name Comment...
Page 316 Table 23-9. AT90CAN32/64/128 Boundary-scan Order (Continued) Bit Number Signal Name Comment Module NEGSEL_1 NEGSEL_0 PASSEN PRECH SCTEST VCCREN PE0.Data Port E PE0.Control PE0.Pullup_Enable PE1.Data PE1.Control PE1.Pullup_Enable PE2.Data PE2.Control PE2.Pullup_Enable PE3.Data PE3.Control PE3.Pullup_Enable PE4.Data PE4.Control PE4.Pullup_Enable PE5.Data PE5.Control PE5.Pullup_Enable PE6.Data PE6.Control PE6.Pullup_Enable PE7.Data PE7.Control...
Page 317 AT90CAN32/64/128 Table 23-9. AT90CAN32/64/128 Boundary-scan Order (Continued) Bit Number Signal Name Comment Module PB2.Control Port B PB2.Pullup_Enable PB3.Data PB3.Control PB3.Pullup_Enable PB4.Data PB4.Control PB4.Pullup_Enable PB5.Data PB5.Control PB5.Pullup_Enable PB6.Data PB6.Control PB6.Pullup_Enable PB7.Data PB7.Control PB7.Pullup_Enable PG3.Data Port G PG3.Control PG3.Pullup_Enable PG4.Data PG4.Control PG4.Pullup_Enable PRIVATE_SIGNAL –...
Page 318 Table 23-9. AT90CAN32/64/128 Boundary-scan Order (Continued) Bit Number Signal Name Comment Module PD1.Control Port D PD1.Pullup_Enable PD2.Data PD2.Control PD2.Pullup_Enable PD3.Data PD3.Control PD3.Pullup_Enable PD4.Data PD4.Control PD4.Pullup_Enable PD5.Data PD5.Control PD5.Pullup_Enable PD6.Data PD6.Control PD6.Pullup_Enable PD7.Data PD7.Control PD7.Pullup_Enable PG0.Data Port G PG0.Control PG0.Pullup_Enable PG1.Data PG1.Control PG1.Pullup_Enable PC0.Data...
Page 319 AT90CAN32/64/128 Table 23-9. AT90CAN32/64/128 Boundary-scan Order (Continued) Bit Number Signal Name Comment Module PC4.Data Port C PC4.Control PC4.Pullup_Enable PC5.Data PC5.Control PC5.Pullup_Enable PC6.Data PC6.Control PC6.Pullup_Enable PC7.Data PC7.Control PC7.Pullup_Enable PG2.Data Port G PG2.Control PG2.Pullup_Enable PA7.Data Port A PA7.Control PA7.Pullup_Enable PA6.Data PA6.Control PA6.Pullup_Enable PA5.Data PA5.Control PA5.Pullup_Enable...
Page 320: Boundary-Scan Description Language Files
Table 23-9. AT90CAN32/64/128 Boundary-scan Order (Continued) Bit Number Signal Name Comment Module PA0.Pullup_Enable Port A PF3.Data Port F PF3.Control PF3.Pullup_Enable PF2.Data PF2.Control PF2.Pullup_Enable PF1.Data PF1.Control PF1.Pullup_Enable PF0.Data PF0.Control PF0.Pullup_Enable Notes: 1. PRIVATE_SIGNAL should always be scanned-in as zero. 23.8 Boundary-scan Description Language Files Boundary-scan Description Language (BSDL) files describe Boundary-scan capable devices in a standard format used by automated test-generation software.
Page 321: Boot Loader Support - Read-While-Write Self-Programming
AT90CAN32/64/128 24. Boot Loader Support – Read-While-Write Self-Programming The Boot Loader Support provides a real Read-While-Write Self-Programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible applica- tion software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data interface and associated protocol to read code and write (program) that code into the Flash memory, or read the code from the program mem- ory.
Page 322 sections that are configurable by the BOOTSZ Fuses as described above, the Flash is also divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-While- Write (NRWW) section. The limit between the RWW- and NRWW sections is given in Table 24- 7 on page 334 Figure 24-2 on page...
Page 323 AT90CAN32/64/128 Figure 24-1. Read-While-Write vs. No Read-While-Write Read-While-Write (RWW) Section Z-pointer Addresses NRWW Section Z-pointer Addresses RWW No Read-While-Write (NRWW) Section Section CPU is Halted During the Operation Code Located in NRWW Section Can be Read During the Operation 7679H–CAN–08/08...
Page 324: Boot Loader Lock Bits
Figure 24-2. Memory Sections Program Memory Program Memory BOOTSZ = ’10’ BOOTSZ = ’11’ 0x0000 0x0000 Application Flash Section Application Flash Section End RWW End RWW Start NRWW Start NRWW Application Flash Section Application Flash Section End Application End Application Start Boot Loader Boot Loader Flash Section Start Boot Loader...
Page 325: Entering The Boot Loader Program
AT90CAN32/64/128 • Allow software update in the entire Flash. Table 24-2 Table 24-3 for further details. The Boot Lock bits can be set in software and in Serial or Parallel Programming mode, but they can be cleared by a Chip Erase command only.
Page 326 grammed, the Reset Vector will always point to the Boot Loader Reset and the fuse can only be changed through the serial or parallel programming interface. Table 24-4. Boot Reset Fuse BOOTRST Reset Address Reset Vector = Application Reset (address 0x0000) Reset Vector = Boot Loader Reset (see Table 24-6 on page 334)
Page 327: Addressing The Flash During Self-Programming
AT90CAN32/64/128 An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCSR Reg- ister, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destination register. See “Reading the Fuse and Lock Bits from Software” on page 330 details.
Page 328: Self-Programming The Flash
same page in both the page erase and page write operation. Once a programming operation is initiated, the address is latched and the Z-pointer can be used for other operations. The (E)LPM instruction use the Z-pointer to store the address. Since this instruction addresses the Flash byte-by-byte, also bit Z0 of the Z-pointer is used.
Page 329 AT90CAN32/64/128 If only a part of the page needs to be changed, the rest of the page must be stored (for example in the temporary page buffer) before the erase, and then be rewritten. When using alternative 1, the Boot Loader provides an effective Read-Modify-Write feature which allows the user software to first read the page, do the necessary changes, and then write back the modified data.
Page 330 change the Boot Loader software itself, it is recommended to program the Boot Lock bit11 to protect the Boot Loader software from any internal software changes. 24.7.6 Prevent Reading the RWW Section During Self-Programming During Self-Programming (either Page Erase or Page Write), the RWW section is always blocked for reading.
Page 331 AT90CAN32/64/128 The algorithm for reading the Fuse Low byte is similar to the one described above for reading the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET and SPMEN bits in SPMCSR. When an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse Low byte (FLB) will be loaded in the destination register as shown below.
Page 332: Simple Assembly Code Example For A Boot Loader
3. Keep the AVR core in Power-down sleep mode during periods of low V . This will pre- vent the CPU from attempting to decode and execute instructions, effectively protecting the SPMCSR Register and thus the Flash from unintentional writes. 24.7.11 Programming Time for Flash when Using SPM The calibrated RC Oscillator is used to time Flash accesses.
Page 333 AT90CAN32/64/128 sbci ZH, high(PAGESIZEB) ;not required for PAGESIZEB<=256 spmcsrval, (1<<PGWRT) | (1<<SPMEN) call Do_spm ; re-enable the RWW section spmcsrval, (1<<RWWSRE) | (1<<SPMEN) call Do_spm ; read back and check, optional looplo, low(PAGESIZEB) ;init loop variable loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256 subi YL, low(PAGESIZEB) ;restore pointer sbci YH, high(PAGESIZEB)
Page 334 24.7.13 Boot Loader Parameters Table 24-6 through Table 24-8, the parameters used in the description of the Self-Program- ming are given. Table 24-6. Boot Size Configuration (Word Addresses) 512 words 0x0000 - 0x3DFF 0x3E00 - 0x3FFF 0x3DFF 0x3E00 1024 words 0x0000 - 0x3BFF 0x3C00 - 0x3FFF 0x3BFF...
Page 335 AT90CAN32/64/128 Table 24-8. Explanation of Different Variables Used in Figure 24-3 on page 328 and the Mapping to the Z-Pointer Corresponding Description Z-value PCMSB Most significant bit in the program counter. (The program counter is 14 bits PC[13:0]) Most significant bit which is used to address the words within one page (128 words in a page PAGEMSB requires 7 bits PC [6:0]).
Page 336: Memory Programming
25. Memory Programming 25.1 Program and Data Memory Lock Bits The AT90CAN32/64/128 provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 25-2. The Lock bits can only be erased to “1”...
Page 337 AT90CAN32/64/128 (1)(2) Table 25-2. Lock Bit Protection Modes (Continued) Memory Lock Bits Protection Type SPM is not allowed to write to the Boot Loader section. SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader section.
Page 338 Table 25-4. Fuse High Byte (Continued) Fuse High Byte Bit No Description Default Value Select Boot Size BOOTSZ1 0 (programmed) (see Table 24-6 for details) Select Boot Size BOOTSZ0 0 (programmed) (see Table 24-6 for details) Select Reset Vector BOOTRST 1 (unprogrammed) (see Table 24-6...
Page 339: Signature Bytes
25.3 Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and parallel mode, also when the device is locked. The three bytes reside in a separate address space.
Page 340 Figure 25-1. Parallel Programming +2.7 - +5.5V RDY/BSY +2.7 - +5.5V AVCC PB7 - PB0 DATA PAGEL +12 V RESET XTAL1 25.5.2 Pin Mapping Table 25-7. Pin Name Mapping Signal Name in Pin Name Function Programming Mode 0: Device is busy programming, RDY/BSY 1: Device is ready for new command.
Page 341 AT90CAN32/64/128 Table 25-9. XA1 and XA0 Coding Action when XTAL1 is Pulsed Load Flash or EEPROM Address (High or low address byte determined by BS1). Load Data (High or Low data byte for Flash determined by BS1). Load Command No Action, Idle Table 25-10.
Page 342: Parallel Programming
25.6 Parallel Programming 25.6.1 Enter Programming Mode The following algorithm puts the device in parallel programming mode: 1. Apply power between V and GND. 2. Set RESET to “0” and toggle XTAL1 at least six times. 3. Set the Prog_enable pins listed in Table 25-8 on page 340 to “0000”...
Page 343 AT90CAN32/64/128 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. 3. Set DATA to “0001 0000”. This is the command for Write Flash. 4. Give XTAL1 a positive pulse. This loads the command. B: Load Address Low byte 1.
Page 344 1. 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set DATA to “0000 0000”. This is the command for No Operation. 3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset. Figure 25-2.
Page 345 AT90CAN32/64/128 25.6.5 Programming the EEPROM The EEPROM is organized in pages, see Table 25-12 on page 341. When programming the EEPROM, the program data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM data memory is as follows (refer to “Programming the Flash”...
Page 346 25.6.7 Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to “Programming the Flash” on page 342 for details on Command and Address loading): 1. A: Load Command “0000 0011”. 2. G: Load Address High Byte (0x00 - 0xFF). 3.
Page 347 AT90CAN32/64/128 Figure 25-5. Programming the FUSES Waveforms Write Fuse Low byte Write Fuse high byte Write Extended Fuse byte 0x40 DATA 0x40 DATA 0x40 DATA DATA XTAL1 RDY/BSY RESET +12V PAGEL 25.6.11 Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to “Programming the Flash”...
Page 348 Figure 25-6. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read Fuse Low Byte Extended Fuse Byte DATA Lock Bits Fuse High Byte 25.6.13 Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to “Programming the Flash”...
Page 349 AT90CAN32/64/128 Figure 25-7. Serial Programming and Verify +2.7 - +5.5V +2.7 - +5.5V AVCC XTAL1 RESET Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the XTAL1 pin. When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase instruction.
Page 350 1. Power-up sequence: Apply power between V and GND while RESET and SCK are set to “0”. In some sys- tems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to “0”.
Page 351 AT90CAN32/64/128 are meant to contain 0xFF, can be skipped. This does not apply if the EEPROM is re-pro- grammed without chip erasing the device. In this case, data polling cannot be used for the value 0xFF, and the user will have to wait at least t before programming the next byte.
Page 352 Table 25-15. Serial Programming Instruction Set (Continued) a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction Format Instruction Operation Byte 1...
Page 353 AT90CAN32/64/128 the JTAG pins for Boundary-scan or On-chip Debug. In these cases the JTAG pins must be ded- icated for this purpose. During programming the clock frequency of the TCK Input must be less than the maximum fre- quency of the chip. The System Clock Prescaler can not be used to divide the TCK Clock Input into a sufficiently low frequency.
Page 354 25.9.1.1 AVR_RESET (0xC) The AVR specific public JTAG instruction for setting the AVR device in the Reset mode or taking the device out from the Reset mode. The TAP controller is not reset by this instruction. The one bit Reset Register is selected as data register. Note that the reset will be active as long as there is a logic “one”...
Page 355 AT90CAN32/64/128 • Capture-DR: The content of the selected Flash byte is captured into the Flash Data Byte Register. The AVR automatically alternates between reading the low and the high byte for each new Capture-DR state, starting with the low byte for the first Capture-DR encountered after entering the PROG_PAGEREAD command.
Page 356 25.9.2.3 Programming Command Register The Programming Command Register is a 15-bit register. This register is used to serially shift in programming commands, and to serially shift out the result of the previous command, if any. The JTAG Programming Instruction Set is shown in Table 25-16.
Page 357 AT90CAN32/64/128 Table 25-16. JTAG Programming Instruction (Continued) a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care (1)(2) (1)(2) Instruction TDI Sequence...
Page 358 Table 25-16. JTAG Programming Instruction (Continued) a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care (1)(2) (1)(2) Instruction TDI Sequence TDO Sequence...
Page 359 AT90CAN32/64/128 Table 25-16. JTAG Programming Instruction (Continued) a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care (1)(2) (1)(2) Instruction TDI Sequence...
Page 360 Figure 25-12. State Machine Sequence for Changing/Reading the Data Word Test-Logic-Reset Run-Test/Idle Select-DR Scan Select-IR Scan Capture-DR Capture-IR Shift-DR Shift-IR Exit1-DR Exit1-IR Pause-DR Pause-IR Exit2-DR Exit2-IR Update-DR Update-IR 25.9.2.4 Flash Data Byte Register The Flash Data Byte Register provides an efficient way to load the entire Flash page buffer before executing Page Write, or to read out/verify the content of the Flash.
Page 361 AT90CAN32/64/128 ture-DR encountered after entering the PROG_PAGEREAD command. The Program Counter is post-incremented after reading each high byte, including the first read byte. This ensures that the first data is captured from the first address set up by PROG_COMMANDS, and reading the last location in the page makes the program counter increment into the next page.
Page 362 25.9.3.3 Performing Chip Erase 1. Enter JTAG instruction PROG_COMMANDS. 2. Start Chip Erase using programming instruction 1a. 3. Poll for Chip Erase complete using programming instruction 1b, or wait for t WLRH_CE (refer to Table 26-15 on page 382). 25.9.3.4 Programming the Flash 1.
Page 363 AT90CAN32/64/128 4. Enter JTAG instruction PROG_PAGEREAD. 5. Read the entire page (or Flash) by shifting out all instruction words in the page (or Flash), starting with the LSB of the first instruction in the page (Flash) and ending with the MSB of the last instruction in the page (Flash). The Capture-DR state both captures the data from the Flash, and also auto-increments the program counter after each word is read.
Page 364 25.9.3.9 Programming the Lock Bits 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Lock bit write using programming instruction 7a. 3. Load data using programming instructions 7b. A bit value of “0” will program the corre- sponding lock bit, a “1” will leave the lock bit unchanged. 4.
Page 365: Electrical Characteristics
AT90CAN32/64/128 26. Electrical Characteristics 26.1 Absolute Maximum Ratings* *NOTICE: Stresses beyond those listed under “Absolute Industrial Operating Temperature ....– 40°C to +85°C Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and Storage Temperature ........– 65°C to +150°C functional operation of the device at these or Voltage on any Pin except RESET other conditions beyond those indicated in the...
Page 366 26.2 DC Characteristics = -40°C to +85°C, V = 2.7V to 5.5V (unless otherwise noted) Symbol Parameter Condition Min. Typ. Max. Units Except XTAL1 and Input Low Voltage – 0.5 0.2 Vcc RESET pins XTAL1 pin - External Input Low Voltage –...
Page 367 AT90CAN32/64/128 = -40°C to +85°C, V = 2.7V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Condition Min. Typ. Max. Units Analog Comparator = 5V – 50 ACLK Input Leakage Current Analog Comparator = 2.7V Propagation Delay ACID = 5.0V Common Mode Vcc/2 Notes: 1.
Page 368: Maximum Speed
Table 26-1. External Clock Drive (Continued) = 2.7 - 5.5V = 4.5 - 5.5V Symbol Parameter Units Min. Max. Min. Max. Low Time CLCX μs Rise Time CLCH μs Fall Time CHCL Change in period from one clock cycle Δ CLCL to the next 26.4...
Page 369: Two-Wire Serial Interface Characteristics
AT90CAN32/64/128 26.5 Two-wire Serial Interface Characteristics Table 26-3 describes the requirements for devices connected to the Two-wire Serial Bus. The AT90CAN32/64/128 Two-wire Serial Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 26-3. Table 26-3. Two-wire Serial Bus Requirements Symbol Parameter...
Page 370: Spi Timing Characteristics
2. Required only for f > 100 kHz. 3. C = capacitance of one bus line in pF. 4. f = CPU clock frequency 5. This requirement applies to all AT90CAN32/64/128 Two-wire Serial Interface operation. Other devices connected to the Two-wire Serial Bus need only obey the general f requirement.
Page 371 AT90CAN32/64/128 Table 26-4. SPI Timing Parameters (Continued) Description Mode Min. Typ. Max. Setup Slave Hold Slave SCK to out Slave SCK to SS high Slave SS high to tri-state Slave SS low to SCK Slave 2 • t Note: In SPI Programming mode the minimum SCK high/low period is: - 2 t for f <...
Page 372 26.7 CAN Physical Layer Characteristics Only pads dedicated to the CAN communication belong to the physical layer. Table : CAN Physical Layer Characteristics Parameter Condition Min. Max. Units Vcc=2.7 V Load=20 pF TxCAN output delay Vcc=4.5 V Load=20 pF Vcc=2.7 V RxCAN input delay Vcc=4.5 V 7.2 +...
Page 373: Adc Characteristics
AT90CAN32/64/128 26.8 ADC Characteristics Table 26-5. ADC Characteristics, Single Ended Channels Symbol Parameter Condition Units Resolution Single Ended Conversion Bits Single Ended Conversion = 4V, Vcc = 4V ADC clock = 200 kHz Single Ended Conversion = 4V, Vcc = 4V ADC clock = 1 MHz Absolute accuracy (Included INL, DNL,...
Page 374 Table 26-6. ADC Characteristics, Differential Channels Symbol Parameter Condition Units Differential Conversion Bits Gain = 1x or 10x Resolution Differential Conversion Bits Gain = 200x Gain = 1x, 10x or 200x Absolute accuracy = 4V, Vcc = 5V ADC clock = 50 - 200 kHz Integral Non-linearity (INL) Gain = 1x, 10x or 200x (Accuracy after Calibration...
Page 375 AT90CAN32/64/128 26.9 External Data Memory Characteristics Table 26-7. External Data Memory Characteristics, V = 4.5 - 5.5 Volts, No Wait-state 8 MHz Oscillator Variable Oscillator Symbol Parameter Unit Min. Max. Min. Max. Oscillator Frequency CLCL ALE Pulse Width 1.0 t –...
Page 376 Table 26-9. External Data Memory Characteristics, V = 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0 8 MHz Oscillator Variable Oscillator Symbol Parameter Unit Min. Max. Min. Max. Oscillator Frequency CLCL Read Low to Data Valid 3.0 t –...
Page 377 AT90CAN32/64/128 Table 26-11. External Data Memory Characteristics, V = 2.7 - 5.5 Volts, No Wait-state (Continued) 4 MHz Oscillator Variable Oscillator Symbol Parameter Unit Min. Max. Min. Max. Data Hold After RD High RHDX RD Pulse Width 1.0 t – 15 RLRH CLCL Data Setup to WR Low...
Page 378 Table 26-14. External Data Memory Characteristics, V = 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1 (Continued) 4 MHz Oscillator Variable Oscillator Symbol Parameter Unit Min. Max. Min. Max. Data Hold After WR High 2.0 t – 15 WHDX CLCL Data Valid to WR High...
Page 379 AT90CAN32/64/128 Figure 26-7. External Memory Timing (SRWn1 = 0, SRWn0 = 1) System Clock (CLK A15:8 Prev. addr. Address Data DA7:0 Prev. data Address DA7:0 (XMBK = 0) Address Data Figure 26-8. External Memory Timing (SRWn1 = 1, SRWn0 = 0) System Clock (CLK A15:8 Prev.
Page 380: Parallel Programming Characteristics
Figure 26-9. External Memory Timing (SRWn1 = 1, SRWn0 = 1) System Clock (CLK Address A15:8 Prev. addr. DA7:0 Prev. data Address Data DA7:0 (XMBK = 0) Address Data Note: 1. The ALE pulse in the last period (T4-T7) is only present if the next instruction accesses the RAM (internal or external).
Page 381: Timing Requirements
AT90CAN32/64/128 Figure 26-11. Parallel Programming Timing, Loading Sequence with Timing Requirements LOAD DATA LOAD ADDRESS LOAD DATA LOAD DATA LOAD ADDRESS (LOW BYTE) (LOW BYTE) (HIGH BYTE) (LOW BYTE) XLPH XLXH PLXH XTAL1 PAGEL DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) Note:...
Page 382 Note: 1. The timing requirements shown in Figure 26-10 (i.e., t , and t ) also apply to DVXH XHXL XLDX reading operation. Table 26-15. Parallel Programming Characteristics, V = 5V ± 10% Symbol Parameter Min. Typ. Max. Units Programming Enable Voltage 11.5 12.5 μA...
Page 383: Decoupling Capacitors
Nevertheless, a bulk capacitor of 10-47 µF is also needed on the power distribution network of the PCB, near the power source. For further information, please refer to Application Notes AVR040 “EMC Design Considerations“ and AVR042 “Hardware Design Considerations“ on the Atmel web site. 7679H–CAN–08/08...
Page 384: Active Supply Current
28. AT90CAN32/64/128 Typical Characteristics • The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source.
Page 385 AT90CAN32/64/128 Figure 28-2. Active Supply Current vs. Frequency (1 - 16 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY (25°C, 1 - 16 MHz) 5.50V 5.00V 4.50V 4.00V 3.30V 3.00V 2.70V Frequency (MHz) Figure 28-3. Active Supply Current vs. Vcc (Internal RC Oscillator 8 MHz) ACTIVE SUPPLY CURRENT vs.
Page 386 Figure 28-4. Active Supply Current vs. Vcc (Internal RC Oscillator 1 MHz) ACTIVE SUPPLY CURRENT vs. Vcc (Internal RC Oscillator 1 MHz) 85°C 25°C -40°C Vcc (V) Figure 28-5. Active Supply Current vs. Vcc (32 kHz Watch Crystal) ACTIVE SUPPLY CURRENT vs. Vcc (32 kHz Watch Crystal) 25°C Vcc (V) AT90CAN32/64/128...
Page 387: Idle Supply Current
AT90CAN32/64/128 28.2 Idle Supply Current Figure 28-6. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY (25°C, 0.1 - 1 MHz) 5.50V 5.00V 4.50V 4.00V 3.30V 3.00V 2.70V Frequency (MHz) Figure 28-7. Idle Supply Current vs. Frequency (1 - 16 MHz) IDLE SUPPLY CURRENT vs.
Page 388 Figure 28-8. Idle Supply Current vs. Vcc (Internal RC Oscillator 8 MHz) IDLE SUPPLY CURRENT vs. Vcc (Internal RC Oscillator 8 MHz) 85°C 25°C -40°C Vcc (V) Figure 28-9. Idle Supply Current vs. Vcc (Internal RC Oscillator 1 MHz) IDLE SUPPLY CURRENT vs. Vcc (Internal RC Oscillator 1 MHz) 85°C 25°C -40°C...
Page 389: Power-Down Supply Current
AT90CAN32/64/128 Figure 28-10. Idle Supply Current vs. Vcc (32 kHz Watch Crystal) IDLE SUPPLY CURRENT vs. Vcc (32 KHz Watch Crystal) 25°C Vcc (V) 28.3 Power-down Supply Current Figure 28-11. Power-down Supply Current vs. Vcc (Watchdog Timer Disabled) POWER-DOWN SUPPLY CURRENT vs. Vcc (Watchdog Timer Disabled) 85°C 25°C -40°C...
Page 390: Power-Save Supply Current
Figure 28-12. Power-down Supply Current vs. Vcc (Watchdog Timer Enabled) POWER-DOWN SUPPLY CURRENT vs. Vcc (Watchdog Timer Enabled) 22.5 17.5 85°C 12.5 25°C -40°C Vcc (V) 28.4 Power-save Supply Current Figure 28-13. Power-save Supply Current vs. Vcc (Watchdog Timer Disabled) POWER-SAVE SUPPLY CURRENT vs.
Page 391: Standby Supply Current
AT90CAN32/64/128 28.5 Standby Supply Current Figure 28-14. Power-save Supply Current vs. Vcc (25°C, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. Vcc (25°C, Watchdog Timer Disabled) 0.18 0.16 0.14 6 MHZ Xtal 0.12 4 MHZ Res 2 MHZ Xtal 0.08 2 MHZ Res 0.06 0.04 0.02...
Page 392 Figure 28-16. I/O Pin Pull-up Resistor Current vs. Input Voltage (Vcc = 2.7V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE (Vcc = 2.7V) 85°C 25°C -40°C Figure 28-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (Vcc = 5V) RESET PULL-UP RESISTOR CURRENT vs.
Page 393: Pin Driver Strength
AT90CAN32/64/128 Figure 28-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (Vcc = 2.7V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE (Vcc = 2.7V) 85°C 25°C -40°C RESET 28.7 Pin Driver Strength Figure 28-19. I/O Pin Source Current vs. Output Voltage (Vcc = 5V) I/O PIN SOURCE CURRENT vs.
Page 394 Figure 28-20. I/O Pin Source Current vs. Output Voltage (Vcc = 2.7V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE (Vcc = 2.7V) 85°C 25°C -40°C Figure 28-21. I/O Pin Sink Current vs. Output Voltage (Vcc = 5V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE (Vcc = 5V) 85°C 25°C -40°C...
Page 395: Pin Thresholds And Hysteresis
AT90CAN32/64/128 Figure 28-22. I/O Pin Sink Current vs. Output Voltage (Vcc = 2.7V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE (Vcc = 2.7V) 85°C 25°C -40°C 28.8 Pin Thresholds and Hysteresis Figure 28-23. I/O Input Threshold Voltage vs. Vcc (V , I/O Pin Read as “1”) I/O PIN INPUT THRESHOLD VOLTAGE vs.
Page 396 Figure 1. I/O Input Threshold Voltage vs. Vcc (V , I/O Pin Read as “0”) I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC (VIL, I/O PIN READ AS "0") 1.75 85°C 1.25 25°C -40°C 0.75 Vcc (V) Figure 2. I/O Input Hysteresis vs. Vcc I/O PIN INPUT HYSTERESIS vs.
Page 397: Bod Thresholds And Analog Comparator Offset
AT90CAN32/64/128 28.9 BOD Thresholds and Analog Comparator Offset Figure 28-24. BOD Thresholds vs. Temperature (BOD level is 4.1V) BOD THRESHOLDS vs. TEMPERATURE (BOD level is 4.1V) Rising Vcc Falling Vcc Temp (°C) Figure 28-25. BOD Thresholds vs. Temperature (BOD level is 2.7V) BOD THRESHOLDS vs.
Page 398 Figure 28-26. Bandgap Voltage vs. Operating Voltage BANDGAP VOLTAGE vs. OPERATING VOLTAGE 1.14 1.13 1.12 85°C 1.11 25°C -40°C 1.09 1.08 Vcc (V) Figure 28-27. Analog Comparator Offset vs. Common Mode Voltage (Vcc = 5V) ANALOG COMPARATOR OFFSET vs. COMMON MODE VOLTAGE (Vcc = 5V) 0.012 0.01 0.008...
Page 399: Internal Oscillator Speed
AT90CAN32/64/128 28.10 Internal Oscillator Speed Figure 28-28. Watchdog Oscillator Frequency vs. Operating Voltage WATCHDOG OSCILLATOR FREQUENCY vs. VCC 1200 1150 1100 1050 85°C 1000 25°C -40°C Vcc (V) Figure 28-29. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 2.7V 4.0V 5.5V...
Page 400 Figure 28-30. Calibrated 8 MHz RC Oscillator Frequency vs. Operating Voltage CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. VCC 85°C 25°C -40°C Vcc (V) Figure 28-31. Calibrated 8 MHz RC Oscillator Frequency vs. OSCCAL Value CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 85°C 25°C -40°C...
Page 401: Current Consumption Of Peripheral Units
AT90CAN32/64/128 28.11 Current Consumption of Peripheral Units Figure 28-32. Brownout Detector Current vs. Operating Voltage BROWNOUT DETECTOR CURRENT vs. Vcc 85°C 25°C -40°C Vcc (V) Figure 28-33. ADC Current vs. Operating Voltage (ADC at 1 MHz) ADC CURRENT vs. Vcc (ADC at 1 MHz) 85°C 25°C -40°C...
Page 402 Figure 28-34. AREF External Reference Current vs. Operating Voltage AREF EXTERNAL REFERENCE CURRENT vs. Vcc 85°C 25°C -40°C Vcc (V) Figure 28-35. Analog Comparator Current vs. Operating Voltage ANALOG COMPARATOR CURRENT vs. Vcc 85°C 25°C -40°C Vcc (V) AT90CAN32/64/128 7679H–CAN–08/08...
Page 403: Current Consumption In Reset And Reset Pulse Width
AT90CAN32/64/128 Figure 28-36. Programming Current vs. Operating Voltage PROGRAMMING CURRENT vs. Vcc 85°C 25°C -40°C Vcc (V) 28.12 Current Consumption in Reset and Reset Pulse Width Figure 28-37. Reset Supply Current vs. Operating Voltage (0.1 - 1.0 MHz) (Excluding Current Through the Reset Pull-up) RESET SUPPLY CURRENT vs.
Page 404 Figure 28-38. Reset Supply Current vs. Operating Voltage (1 - 16 MHz) (Excluding Current Through the Reset Pull-up) RESET SUPPLY CURRENT vs. FREQUENCY (1 - 16 MHz) (EXCLUDING CURRENT THROUGH THE RESET PULL-UP) 5.50V 5.00V 4.50V 4.00V 3.30V 3.00V 2.70V Frequency (MHz) Figure 28-39.
Page 405: Register Summary
AT90CAN32/64/128 29. Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0xFF) Reserved (0xFE) Reserved (0xFD) Reserved (0xFC) Reserved (0xFB) Reserved (0xFA) CANMSG MSG 7 MSG 6 MSG 5 MSG 4 MSG 3 MSG 2...
Page 406 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0xBE) Reserved (0xBD) Reserved (0xBC) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE page 212 (0xBB) TWDR TWDR7 TWDR6 TWDR5 TWDR4 TWDR3 TWDR2...
Page 407 AT90CAN32/64/128 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0x7C) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 page 287 (0x7B) ADCSRB – ACME – – – ADTS2 ADTS1 ADTS0 page...
Page 408 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x1A (0x3A) Reserved 0x19 (0x39) Reserved 0x18 (0x38) TIFR3 – – ICF3 – OCF3C OCF3B OCF3A TOV3 page 143 0x17 (0x37) TIFR2 –...
Page 409: Instruction Set Summary
AT90CAN32/64/128 30. Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS Rd ← Rd + Rr Rd, Rr Add two Registers Z,C,N,V,H Rd ← Rd + Rr + C Rd, Rr Add with Carry two Registers Z,C,N,V,H Rdh:Rdl ←...
Page 410 Mnemonics Operands Description Operation Flags #Clocks if ( I = 1) then PC ← PC + k + 1 BRIE Branch if Interrupt Enabled None if ( I = 0) then PC ← PC + k + 1 BRID Branch if Interrupt Disabled None BIT AND BIT-TEST INSTRUCTIONS I/O(P,b) ←...
Page 411 AT90CAN32/64/128 Mnemonics Operands Description Operation Flags #Clocks Rd ← P Rd, P In Port None P ← Rr P, Rr Out Port None STACK ← Rr PUSH Push Register on Stack None Rd ← STACK Pop Register from Stack None MCU CONTROL INSTRUCTIONS No Operation None...
Page 412: Ordering Information
2.7 - 5.5 Z64-2 AT90CAN128-16MU Green Notes: 1. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering informa- tion and minimum quantities. 32. Packaging Information Package Type A2 64 64-Lead, Thin (1.0 mm / 0.03937 in) Plastic Gull Wing Quad Flat Package.
Page 413 AT90CAN32/64/128 32.1 TQFP64 64 PINS THIN QUAD FLAT PACK to 7 / 13 TOP VIEW SIDE VIEW DRAWINGS 0.100 mm NOT SCALED LEAD COPLANARITY INCH - - - - 1.20 - - - - 0.047 0.95 1.05 0.037 0.041 0.09 0.20 0.004 0.008...
Page 414 32.2 QFN64 AT90CAN32/64/128 7679H–CAN–08/08...
Page 415 AT90CAN32/64/128 7679H–CAN–08/08...
Page 416: Errata Summary
33. Errata 33.1 Errata Summary AT90CAN32 RevB (Date code ≥ 0107) 33.1.1 • CAN acknowledge error in 3-sample mode with prescaler =1 • CAN transmission after 3-bit intermission • Asynchronous Timer-2 wakes up without interrupt 33.1.2 AT90CAN32 RevA (Date code < 0107) •...
Page 417 AT90CAN32/64/128 Let’s consider 4 sections in the Flash, described below: Table 33-1. Flash memory sections M e m o r y M e m o r y M e m o r y M e m o r y s p a c e s p a c e s p a c e s p a c e...
Page 418 minimum delay will be 39-bit time in CAN2.0B. See CAN2.0A CAN2.0B frame timings below. CAN 2.0A 19-bit time minimum (RXOK) 11-bit identifier 4-bit DLC 15-bit CRC RTR IDE del. del. ID10..0 DLC4..0 7 bits 3 bits Inter- Arbitration Control End of Frame Field Field mission...
Page 419 AT90CAN32/64/128 4. Reset of Timer-2 flags in asynchronous mode In asynchronous mode, a writing in any register of the TIMER-2 (TCCR2A, TCNT2 & OCR2A) automatically clears TOV2 and OCF2A flags in TFIR register. Problem fix / workaround – TOV2: Do not write in Timer-2 registers if TCNT2 is equal to 0xFF, 0x00 or 0x01. –...
Page 420: Document Creation
34. Datasheet Revision History for AT90CAN32/64/128 Please note that the page numbers in this section refer to this document. The revision noted in this section refer to the document revision. 34.1 Changes from 7679G - 03/08 to 7679H - 08/08 1.
Page 421 AT90CAN32/64/128 Features ..................... 1 Description ....................2 Comparison Between AT90CAN32, AT90CAN64 and AT90CAN128 ....2 Part Description ....................2 Disclaimer ......................3 Block Diagram ....................4 Pin Configurations ....................5 Pin Descriptions ....................6 About Code Examples ................8 AVR CPU Core ..................9 Introduction ......................9 Architectural Overview ..................9 ALU –...
Page 422 Timer/Counter2 Oscillator .................43 5.10 System Clock Prescaler ..................44 Power Management and Sleep Modes ..........46 Idle Mode ......................47 ADC Noise Reduction Mode ................47 Power-down Mode ....................47 Power-save Mode .....................47 Standby Mode ....................48 Minimizing Power Consumption ...............48 System Control and Reset ..............51 Reset ........................51 Internal Voltage Reference ................56 Watchdog Timer ....................57...
Page 423 AT90CAN32/64/128 12.7 Modes of Operation ..................104 12.8 Timer/Counter Timing Diagrams ..............108 12.9 8-bit Timer/Counter Register Description ............109 13 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3) ... 113 13.1 Features ......................113 13.2 Overview ......................113 13.3 Accessing 16-bit Registers ................116 13.4 Timer/Counter Clock Sources .................119 13.5 Counter Unit ....................120 13.6...
Page 424 17 USART (USART0 and USART1) ............177 17.1 Features ......................177 17.2 Overview ......................177 17.3 Dual USART ....................177 17.4 Clock Generation ....................179 17.5 Serial Frame ....................181 17.6 USART Initialization ..................182 17.7 Data Transmission – USART Transmitter ............183 17.8 Data Reception – USART Receiver ..............186 17.9 Asynchronous Data Reception ...............190 17.10 Multi-processor Communication Mode ............193...
Page 425 AT90CAN32/64/128 19.12 Examples of CAN Baud Rate Setting .............266 20 Analog Comparator ................269 20.1 Overview ......................269 20.2 Analog Comparator Register Description ............269 20.3 Analog Comparator Multiplexed Input ............271 21 Analog to Digital Converter - ADC ............. 273 21.1 Features ......................273 21.2 Operation ......................274 21.3...
Page 426 24 Boot Loader Support – Read-While-Write Self-Programming ..321 24.1 Features ......................321 24.2 Application and Boot Loader Flash Sections ..........321 24.3 Read-While-Write and No Read-While-Write Flash Sections ......321 24.4 Boot Loader Lock Bits ..................324 24.5 Entering the Boot Loader Program ..............325 24.6 Addressing the Flash During Self-Programming ..........327 24.7...
Page 427 AT90CAN32/64/128 28.5 Standby Supply Current ..................391 28.6 Pin Pull-up ......................391 28.7 Pin Driver Strength ..................393 28.8 Pin Thresholds and Hysteresis ...............395 28.9 BOD Thresholds and Analog Comparator Offset ...........397 28.10 Internal Oscillator Speed ................399 28.11 Current Consumption of Peripheral Units ............401 28.12 Current Consumption in Reset and Reset Pulse Width ........403 29 Register Summary ................
Page 428 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY...

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