Atmel AT90S1200 Datasheet
Atmel AT90S1200 Datasheet

Atmel AT90S1200 Datasheet

8-bit avr microcontroller with 1k bytes in-system programmable flash
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Features
®
Utilizes the AVR
RISC Architecture
AVR - High-performance and Low-power RISC Architecture
– 89 Powerful Instructions - Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Up to 12 MIPS Throughput at 12 MHz
Data and Nonvolatile Program Memory
– 1K Bytes of In-System Programmable Flash
Endurance: 1,000 Write/Erase Cycles
– 64 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
– SPI Serial Interface for In System Programming
Special Microcontroller Features
– Low-power Idle and Power Down Modes
– External and Internal Interrupt Sources
– Selectable On-chip RC Oscillator for Zero External Components
Specifications
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation
Power Consumption at 4 MHz, 3V, 25°C
– Active: 2.0 mA
– Idle Mode: 0.4 mA
– Power Down Mode: <1 µA
I/O and Packages
– 15 Programmable I/O Lines
– 20-pin PDIP and SOIC
Operating Voltages
– 2.7 - 6.0V (AT90S1200-4)
– 4.0 - 6.0V (AT90S1200-12)
Speed Grades
– 0 - 4 MHz, (AT90S1200-4)
– 0 - 12 MHz, (AT90S1200-12)
Description
The AT90S1200 is a low-power CMOS 8-bit microcontroller based on the AVR RISC
architecture. By executing powerful instructions in a single clock cycle, the
Pin Configuration
8-bit
Microcontroller
with 1K bytes
In-System
Programmable
Flash
AT90S1200
(continued)
Rev. 0838E–04/99
1

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Summary of Contents for Atmel AT90S1200

  • Page 1 – 0 - 4 MHz, (AT90S1200-4) – 0 - 12 MHz, (AT90S1200-12) Description The AT90S1200 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the (continued) Pin Configuration...
  • Page 2: Block Diagram

    AT90S1200 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consump- tion versus processing speed. The AVR core combines a rich instruction set with the 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle.
  • Page 3: Pin Descriptions

    By combining an enhanced RISC 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT90S1200 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.
  • Page 4: On-Chip Rc Oscillator

    An on-chip RC oscillator running at a fixed frequency of 1 MHz can be selected as the MCU clock source. If enabled, the AT90S1200 can operate with no external components. A control bit - RCEN in the Flash Memory selects the on-chip RC oscillator as the clock source when programmed (“0”).
  • Page 5 The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register operations are also executed in the ALU. Figure 4 shows the AT90S1200 AVR RISC microcontroller architecture. The AVR uses a Harvard architecture concept - with separate memories and buses for program and data memories. The program memory is accessed with a two stage pipeline.
  • Page 6 The AT90S1200 AVR RISC Microcontroller supports powerful and efficient addressing modes. This section describes the different addressing modes supported in the AT90S1200. In the figures, OP means the operation code part of the instruc- tion word. To simplify, not all figures show the exact location of the addressing bits.
  • Page 7 AT90S1200 Register Direct, Single Register Rd Figure 6. Direct Single Register Addressing The operand is contained in register d (Rd). Register Indirect Figure 7. Indirect Register Addressing The register accessed is the one pointed to by the Z-register (R30).
  • Page 8 Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd). I/O Direct Figure 9. I/O Direct Addressing Operand address is contained in 6 bits of the instruction word. n is the destination or source register address. AT90S1200...
  • Page 9: Subroutine And Interrupt Hardware Stack

    Subroutine and Interrupt Hardware Stack The AT90S1200 uses a 3 level deep hardware stack for subroutines and interrupts. The hardware stack is 9 bit wide and stores the Program Counter - PC - return address while subroutines and interrupts are executed.
  • Page 10 Figure 12 shows the internal timing concept for the register file. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 12. Single Cycle ALU Operation System Clock Ø Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back AT90S1200...
  • Page 11 Reserved and unused locations are not shown in the table. All AT90S1200 I/Os and peripherals are placed in the I/O space. The different I/O locations are accessed by the IN and OUT instructions transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions.
  • Page 12: Reset And Interrupt Handling

    Reset and Interrupt Handling The AT90S1200 provides 3 different interrupt sources. These interrupts and the separate reset vector, each have a sepa- rate program vector in the program memory space. All the interrupts are assigned individual enable bits which must be set (one) together with the I-bit in the status register in order to enable the interrupt.
  • Page 13 … Reset Sources The AT90S1200 has three sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the power-on reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for more than 50 ns.
  • Page 14 If the build-in start-up delay is sufficient, RESET can be connected to V directly or via an external pull-up resistor. By holding the RESET pin low for a period after V has been applied, the Power-on Reset period can be extended. Refer to Figure 15 for a timing example on this. AT90S1200...
  • Page 15 AT90S1200 Figure 15. MCU Start-up, RESET Controlled Externally RESET TOUT TIME-OUT INTERNAL RESET External Reset An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the...
  • Page 16 Figure 17. Watchdog Reset During Operation Interrupt Handling The AT90S1200 has two Interrupt Mask control registers GIMSK - General Interrupt MASK register - at I/O space address $3B and the TIMSK - Timer/Counter Interrupt MaSK register at I/O address $39.
  • Page 17 TOV0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. • Bit 0 - Res: Reserved bit This bits is a reserved bit in the AT90S1200 and always read as zero. Timer/Counter Interrupt FLAG Register - TIFR TOV0...
  • Page 18 Initial value • Bits 7, 6 - Res: Reserved bits These bits are reserved bits in the AT90S1200 and always read as zero. • Bit 5 - SE: Sleep Enable The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction.
  • Page 19: Sleep Modes

    TOUT Timer/Counter0 The AT90S1200 provides one general purpose 8-bit Timer/Counter. The Timer/Counter0 gets the prescaled clock from the 10-bit prescaling timer. The Timer/Counter0 can either be used as a timer with an internal clock timebase or as a counter with an external pin connection which triggers the counting.
  • Page 20 The four different prescaled selections are: CK/8, CK/64, CK/256 and CK/1024 where CK is the oscillator clock. For the Timer/Counter0, added selections as CK, external clock source and stop, can be selected as clock sources. Figure 19 shows the block diagram for Timer/Counter0. Figure 19. Timer/Counter 0 Block Diagram AT90S1200...
  • Page 21 Initial value • Bits 7..3 - Res: Reserved bits These bits are reserved bits in the AT90S1200 and always read as zero. • Bits 2,1,0 - CS02, CS01, CS00: Clock Select0, bit 2,1 and 0 The Clock Select0 bits 2,1 and 0 define the prescaling source of Timer/Counter0.
  • Page 22: Watchdog Timer

    Watchdog Timer resets the MCU. If the reset period expires without another WDR instruction, the AT90S1200 resets and executes from the reset vector. For timing details on the Watchdog reset, refer to page 15. Figure 20. Watchdog Timer...
  • Page 23: Eeprom Read/Write Access

    Initial value • Bit 7,6 - Res: Reserved bits These bits are reserved bit in the AT90S1200 and will always read as zero. • Bits 5..0 - EEAR5..0: EEPROM Address The EEPROM Address Register - EEAR5..0 - specifies the EEPROM address in the 64-byte EEPROM space. The...
  • Page 24: Prevent Eeprom Corruption

    Initial value • Bits 7..2 - Res: Reserved bits These bits are reserved bits in the AT90S1200 and will always be read as zero. • Bit 1 - EEWE: EEPROM Write Enable The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM.
  • Page 25: Analog Comparator

    Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. • Bit 6 - Res: Reserved bit This bit is a reserved bit in the AT90S1200 and will always read as zero. • Bit 5 - ACO: Analog Comparator Output ACO is directly connected to the comparator output.
  • Page 26 MOSI (Data input line for memory downloading) MISO (Data output line for memory uploading) SCK (Serial clock input) When the pins are used for the alternate function, the DDRB and PORTB register has to be set according to the alternate function description. AT90S1200...
  • Page 27 AT90S1200 Port B Data Register - PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 PORTB Read/Write Initial value Port B Data Direction Register - DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRB Read/Write Initial value Port B Input Pin Address - PINB...
  • Page 28 [PB0 is cleared (zero)], this pin also serves as the positive input of the on-chip analog comparator. Port B Schematics Note that all port pins are synchronized. The synchronization latches are however, not shown in the figures. Figure 22. Port B Schematic Diagram (pins PB0 and PB1) AT90S1200...
  • Page 29 AT90S1200 Figure 23. Port B Schematic Diagram (Pins PB2, PB3 and PB4) Figure 24. Port B Schematic Diagram, Pin PB5...
  • Page 30 Figure 25. Port B Schematic Diagram, Pin PB6 Figure 26. Port B Schematic Diagram, Pin PB7 AT90S1200...
  • Page 31 AT90S1200 Port D Three I/O memory address locations are allocated for the Port D, one each for the Data Register - PORTD ($12), Data Direction Register - DDRD ($11) and the Port D Input Pins - PIND ($10). The Port D Input Pins address is read only, while the Data Register and the Data Direction Register are read/write.
  • Page 32 INT0, External Interrupt source 0. See the interrupt description for further details. Port D Schematics Note that all port pins are synchronized. The synchronization latches are however, not shown in the figures. Figure 27. Port D Schematic Diagram (Pins PD0, PD1, PD3, PD5 and PD6) AT90S1200...
  • Page 33 AT90S1200 Figure 28. Port D Schematic Diagram (Pin PD2) Figure 29. Port D Schematic Diagram (Pin PD4) PULL- RESET DDD4 RESET PORTD4 WRITE PORTD TIMER0 CLOCK WRITE DDRD SENSE CONTROL SOURCE MUX READ PORTD LATCH READ PORTD PIN READ DDRD...
  • Page 34: Memory Programming

    Program and Data Memory Lock Bits The AT90S1200 MCU provides two Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 12. The Lock bits can only be erased with the Chip Erase command.
  • Page 35: Parallel Programming

    Signal Names In this section, some pins of the AT90S1200 are referenced by signal names describing their function during parallel programming rather than their pin names, see Figure 30 and Table 14. Pins not described in Table 14 are referenced by pin names.
  • Page 36 Chip Erase 0100 0000 Write Fuse Bits 0010 0000 Write Lock Bits 0001 0000 Write Flash 0001 0001 Write EEPROM 0000 1000 Read Signature Bytes 0000 0100 Read Fuse and Lock Bits 0000 0010 Read Flash 0000 0011 Read EEPROM AT90S1200...
  • Page 37 AT90S1200 Enter Programming Mode The following algorithm puts the device in parallel programming mode: 1. Apply supply voltage according to Table 13, between V and GND. 2. Set the RESET and BS pin to “0” and wait at least 100 ns.
  • Page 38 • Skip writing the data value $FF, that is the contents of the entire Flash and EEPROM after a Chip Erase. These considerations also applies to EEPROM programming, and Flash, EEPROM and Signature bytes reading. Figure 31. Programming the Flash Waveforms DATA ADDR. HIGH ADDR.LOW DATA LOW XTAL1 RDY/BSY RESET AT90S1200...
  • Page 39 AT90S1200 Figure 32. Programming the Flash Waveforms (Continued) DATA DATA HIGH XTAL1 RDY/BSY RESET +12V Reading the Flash The algorithm for reading the Flash memory is as follows (refer to Programming the Flash for details on Command and Address loading): 1.
  • Page 40 Address loading): 1. A: Load Command “0000 1000”. 2. C: Load Address Low Byte ($00 - $02). Set OE to “0”, and BS to “0”. The selected Signature byte can now be read at DATA. 3. Set OE to “1”. AT90S1200...
  • Page 41: Parallel Programming Characteristics

    AT90S1200 Parallel Programming Characteristics Figure 33. Parallel Programming Timing XLWL XTAL1 XHXL DVXH XLDX BVWL Data & Contol (DATA, XA0/1, BS) WLWH RHBX WHRL RDY/BSY WLRH XLOL OHDZ OLDV DATA Table 17. Parallel Programming Characteristics, T = 25°C ± 10%, V =5V ±...
  • Page 42: Serial Downloading

    When writing serial data to the AT90S1200, data is clocked on the rising edge of SCK. When reading data from the AT90S1200, data is clocked on the falling edge of SCK. See Figure 35, Figure 36 and Table 20 for timing details.
  • Page 43 AT90S1200 4. The Flash or EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. Wait t after transmitting the instruction.
  • Page 44 Table 19. Serial Programming Instruction Set for AT90S1200 Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte4 Operation Programming Enable Serial Programming while RESET is low. 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Chip Erase Chip Erase both Flash and EEPROM memory...
  • Page 45: Serial Programming Characteristics

    AT90S1200 Serial Programming Characteristics Figure 36. Serial Programming Timing MOSI SLSH OVSH SHOX SHSL MISO SLIV Table 20. Serial Programming Characteristics, T = -40°C to 85°C, V =2.7 - 6.0V (Unless otherwise noted) Symbol Parameter Units Oscillator Frequency (V = 2.7 - 4.0V)
  • Page 46: Electrical Characteristics

    Exposure to absolute maximum rating Voltage on RESET with respect to Ground..-1.0V to +13.0V conditions for extended periods may affect device reliability. Maximum Operating Voltage ..........6.6V DC Current per I/O Pin ..........40.0 mA DC Current and GND Pins........ 200.0 mA AT90S1200...
  • Page 47 AT90S1200 DC Characteristics = -40°C to 85°C, V = 2.7V to 6.0V (unless otherwise noted) Symbol Parameter Condition Units Input Low Voltage (Except XTAL1) -0.5 Input Low Voltage (XTAL1) -0.5 Input High Voltage (Except XTAL1, RESET) 0.6 V + 0.5...
  • Page 48: External Clock Drive Waveforms

    The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequen- cies higher than the ordering code indicates. The difference between current consumption in Power Down mode with Watchdog timer enabled and Power Down mode with Watchdog timer disabled represents the differential current drawn by the watchdog timer. AT90S1200...
  • Page 49 AT90S1200 Figure 38. Active Supply Current vs. Frequency ACTIVE SUPPLY CURRENT vs. FREQUENCY T = 25˚C = 6V = 5.5V = 5V = 4.5V = 4V = 3.6V = 3.3V = 3.0V = 2.7V Frequency (MHz) Figure 39. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs.
  • Page 50 T = 85 ˚ Figure 41. Idle Supply Current vs. Frequency IDLE SUPPLY CURRENT vs. FREQUENCY T = 25˚C = 6V = 5.5V = 5V = 4.5V = 4V = 3.6V = 3.3V = 3.0V = 2.7V Frequency (MHz) AT90S1200...
  • Page 51 AT90S1200 Figure 42. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs. V FREQUENCY = 4 MHz T = -40 ˚ T = 25 ˚ T = 85 ˚ Figure 43. Idle Supply Current vs. V , Device Clocked by Internal Oscillator IDLE SUPPLY CURRENT vs.
  • Page 52 T = 70 ˚ T = 45 ˚ T = 25 ˚ Figure 45. Power Down Supply Current vs. V , Watchdog Timer Enabled POWER DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ENABLED T = 25 ˚ T = 85 ˚ AT90S1200...
  • Page 53 AT90S1200 Figure 46. Internal RC Oscillator Frequency vs. V INTERNAL RC OSCILLATOR FREQUENCY vs. V 1600 T = 25 ˚ 1400 T = 85 ˚ 1200 1000 V (V) Figure 47. Analog Comparator Current vs. V ANALOG COMPARATOR CURRENT vs. V T = -40 ˚...
  • Page 54 T = 85 ˚ Common Mode Voltage (V) Figure 49. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE V = 2.7V T = 25 ˚ T = 85 ˚ Common Mode Voltage (V) AT90S1200...
  • Page 55 AT90S1200 Figure 50. Analog Comparator Input Leakage Current ANALOG COMPARATOR INPUT LEAKAGE CURRENT V = 6V T = 25 ˚ V (V) Sink and source capabilities of I/O ports are measured on one pin at a time. Figure 51. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs.
  • Page 56 PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE V = 2.7V T = 25 ˚ T = 85 ˚ Figure 53. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE V = 5V T = 25 ˚ T = 85 ˚ AT90S1200...
  • Page 57 AT90S1200 Figure 54. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE V = 5V T = 25 ˚ T = 85 ˚ Figure 55. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE V = 2.7V...
  • Page 58 T = 25 ˚ T = 85 ˚ Input threshold is measured at the center point of the hysteresis Figure 57. I/O Pin Input Threshold Voltage vs. V I/O PIN INPUT THRESHOLD VOLTAGE vs. V T = 25 ˚ AT90S1200...
  • Page 59 AT90S1200 Figure 58. I/O Pin Input Hysteresis vs. V I/O PIN INPUT HYSTERESIS vs. V T = 25 ˚ 0.18 0.16 0.14 0.12 0.08 0.06 0.04 0.02...
  • Page 60: At90S1200 Register Summary

    AT90S1200 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page SREG Reserved Reserved Reserved GIMSK INT0 Reserved TIMSK TOIE0 TIFR TOV0 Reserved Reserved MCUCR ISC01 ISC00 Reserved TCCR0...
  • Page 61: Instruction Set Summary

    AT90S1200 Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ← Rd, Rr Add two Registers Rd + Rr Z,C,N,V,H Rd, Rr Add with Carry two Registers ← Rd + Rr + C Z,C,N,V,H Rd, Rr Subtract two Registers ←...
  • Page 62 Clear T in SREG ← Set Half Carry Flag in SREG Clear Half Carry Flag in SREG ← No Operation None SLEEP Sleep (see specific descr. for Sleep function) None Watch Dog Reset (see specific descr. for WDR/timer) None AT90S1200...
  • Page 63: Ordering Information

    AT90S1200 Ordering Information Speed (MHz) Power Supply Ordering Code Package Operation Range 2.7 - 6.0V AT90S1200-4PC 20P3 Commercial AT90S1200-4SC (0°C to 70°C) AT90S1200-4YC AT90S1200-4PI 20P3 Industrial AT90S1200-4SI (-40°C to 85°C) AT90S1200-4YI 4.0 - 6.0V AT90S1200-12PC 20P3 Commercial AT90S1200-12SC (0°C to 70°C)
  • Page 64: Packaging Information

    Dimensions in Millimeters and (Inches) 0.38 (.015) 0.25 (.010) 5.38 (.212) 7.90 (.311) 5.20 (.205) 7.65 (.301) PIN 1 ID 0.65 (.0256) BSC 7.33 (.289) 2.67 (.105) 7.07 (.278) 2.34 (.092) 0.21 (.008) 0.05 (.002) 0.20 (.008) 0.09 (.004) 0.95 (.037) 0.63 (.025) AT90S1200...
  • Page 65 No licenses to patents or other intellectual prop- erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life suppor t devices or systems.

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