Atmel AT91 Series Application Note
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Atmel AT91 Series Application Note

Atmel AT91 Series Application Note

Arm thumb microcontrollers
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Software DMA Implementation
Introduction
A DMA (Direct Memory Access) Controller allows fast data transfers between memo-
ries without using the CPU. The transfer is activated by an external event. The control
signals and the address and data buses are managed by the DMA controller.
The AT91M40400 does not feature a DMA controller as a peripheral. However, it can
be implemented by software by using the load multiple (ldm) and store multiple (stm)
instructions (refer to the "ARM Architectural Reference Manual").
This application note proposes two different ways to implement a software DMA using
the ARM Fast Interrupt (FIQ) as the external event. The code has been designed to
reduce the number of instruction fetches as much as possible.
AT91 Series
®
ARM
Thumb
Microcontrollers
Application Note
Rev. 1169A–10/98
®
1

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Summary of Contents for Atmel AT91 Series

  • Page 1 Software DMA Implementation AT91 Series Introduction A DMA (Direct Memory Access) Controller allows fast data transfers between memo- ® ® Thumb ries without using the CPU. The transfer is activated by an external event. The control signals and the address and data buses are managed by the DMA controller.

  • Page 2: Theory Of Operation

    The main advantage to this implementation is that no registers need to be saved. It is also a faster way to transfer data than the DMA Channel implementation. Table 2. Registers Used Register Parameter Link register - return address ‘dest_pt’ = Destination buffer pointer ‘src_pt’ = Source buffer pointer r8 to r11 Transfer registers AT91 Series...

  • Page 3: User Functions

    AT91 Series User Functions The functions used to manage the DMA Turbo are defined in dma_turb.c : Table 3. DMA Turbo User Functions void DmaTurboSet (int *source, int *destination) Initialize the FIQ registers for the DMA transfer void DmaTurboGet (int *source, int size)

  • Page 4: Dma Channel

    Temporary buffer address Increment mask Number of packets to copy per FIQ Block size (byte number) Destination address Source address r6 to r7 Working registers (must be saved and restored) r0 to r3 Transfer registers (must be saved and restored) AT91 Series...

  • Page 5: Type Definition

    AT91 Series Type Definition The DMA channel parameters are set through a structure named “dma_descriptor”. This type is defined in dma.h: typedef struct dma_descriptor u_char *src; // Source pointer u_char *dest; // Destination pointer u_int nb_bytes; // Total number of bytes to copy u_int nb_packets;...

  • Page 6: Required Resources

    Code Size 20 words Register Usage R8 to R14 (banked FIQ registers) Peripheral Usage FIQ Interrupt Table 7. DMA Channel Parameter Value Code Size 51 words Register Usage R8 to R14 (banked FIQ registers) Peripheral Usage FIQ Interrupt AT91 Series...

  • Page 7: Tips And Warnings For Both Types Of Dma Implementation

    AT91 Series Tips and Warnings for Both Types of DMA Implementation Pointer Alignment Source and destination pointers must always be word-aligned because of the use of load and store multiple instructions. If this is not the case, a word-alignment must be performed, using an “AND” with the existing word in the memory to copy the first non-aligned bytes.

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