Stack Pointer - Atmel AVR ATmega32 Manual

The X-register, Y-register and
Z-register

Stack Pointer

ATmega32(L)
12
The registers R26..R31 have some added functions to their general purpose usage.
These registers are 16-bit address pointers for indirect addressing of the Data Space.
The three indirect address registers X, Y, and Z are defined as described in Figure 5.
Figure 5. The X-, Y-, and Z-registers
15
X - register 7
R27 ($1B)
15
Y - register 7
R29 ($1D)
15
Z - register 7
R31 ($1F)
In the different addressing modes these address registers have functions as fixed dis-
placement, automatic increment, and automatic decrement (see the Instruction Set
Reference for details).
The Stack is mainly used for storing temporary data, for storing local variables and for
storing return addresses after interrupts and subroutine calls. The Stack Pointer Regis-
ter always points to the top of the Stack. Note that the Stack is implemented as growing
from higher memory locations to lower memory locations. This implies that a Stack
PUSH command decreases the Stack Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Inter-
rupt Stacks are located. This Stack space in the data SRAM must be defined by the
program before any subroutine calls are executed or interrupts are enabled. The Stack
Pointer must be set to point above $60. The Stack Pointer is decremented by one when
data is pushed onto the Stack with the PUSH instruction, and it is decremented by two
when the return address is pushed onto the Stack with subroutine call or interrupt. The
Stack Pointer is incremented by one when data is popped from the Stack with the POP
instruction, and it is incremented by two when data is popped from the Stack with return
from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The num-
ber of bits actually used is implementation dependent. Note that the data space in some
implementations of the AVR architecture is so small that only SPL is needed. In this
case, the SPH Register will not be present.
Bit 15 14
SP15 SP14
SP7 SP6
7 6
Read/Write R/W R/W
R/W R/W
Initial Value 0 0
0 0
XH
0 7
R26 ($1A)
YH
0 7
R28 ($1C)
ZH
0 7
R30 ($1E)
13 12 11
SP13 SP12 SP11
SP5 SP4 SP3
5 4 3
R/W R/W R/W
R/W R/W R/W
0 0 0
0 0 0
XL
YL
ZL
0
10 9 8
SP10 SP9 SP8
SP2 SP1 SP0
2 1 0
R/W R/W R/W
R/W R/W R/W
0 0 0
0 0 0
0
0
0
0
0
SPH
SPL