Table of Contents
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Features
•
High-performance and Low-power AVR
– 118 Powerful Instructions - Most Single Cycle Execution
– 32 x 8 General Purpose Working Registers
– Up to 8 MIPS Throughput at 8 MHz
•
Data and Nonvolatile Program Memory
– 2K/4K Bytes of In-System Programmable Flash
Endurance 1,000 Write/Erase Cycles
– 128 Bytes of SRAM
– 128/256 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
•
Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler
– Expanded 16-bit Timer/Counter with Separate Prescaler,
Compare, Capture Modes and 8-, 9- or 10-bit PWM
– On-chip Analog Comparator
– Programmable Watchdog Timer with Separate On-chip Oscillator
– Programmable UART
– 6-channel, 10-bit ADC
– Master/Slave SPI Serial Interface
•
Special Microcontroller Features
– Brown-Out Reset Circuit
– Enhanced Power-on Reset Circuit
– Low-Power Idle and Power Down Modes
– External and Internal Interrupt Sources
•
Specifications
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation
•
Power Consumption at 4 MHz, 3V, 25°C
– Active: 3.4 mA
– Idle Mode: 1.4 mA
– Power Down Mode: <1 µA
•
I/O and Packages
– 20 Programmable I/O Lines
– 28-pin PDIP and 32-pin TQFP
•
Operating Voltage
– 2.7V - 6.0V (AT90LS2333 and AT90LS4433)
– 4.0V - 6.0V (AT90S2333 and AT90S4433)
•
Speed Grades
– 0 - 4 MHz (AT90LS2333 and AT90LS4433)
– 0 - 8 MHz (AT90S2333 and AT90S4433)
Pin Configurations
TQFP Top View
(INT1) PD3
1
(T0) PD4
2
NC
3
VCC
4
GND
5
NC
6
XTAL1
7
XTAL2
8
®
8-bit RISC Architecture
(RXD) PD0
(TXD) PD1
(INT0) PD2
(INT1) PD3
24
PC1 (ADC1)
23
PC0 (ADC0)
22
NC
21
AGND
20
AREF
19
NC
18
AVCC
17
PB5 (SCK)
(AIN0) PD6
(AIN1) PD7
PDIP
RESET
1
28
PC5 (ADC5)
2
27
PC4 (ADC4)
3
26
PC3 (ADC3)
4
25
PC2 (ADC2)
5
24
PC1 (ADC1)
(T0) PD4
6
23
PC0 (ADC0)
VCC
7
22
AGND
GND
8
21
AREF
XTAL1
9
20
AVCC
XTAL2
10
19
PB5 (SCK)
(T1) PD5
11
18
PB4 (MISO)
12
17
PB3 (MOSI)
13
16
PB2 (SS)
(ICP) PB0
14
15
PB1 (OC1)
8-bit
Microcontroller
with 2K/4K bytes
In-System
Programmable
Flash
AT90S2333
AT90LS2333
AT90S4433
AT90LS4433
Preliminary
Rev. 1042D–04/99
1
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Summary of Contents for Atmel AVR AT90S2333
- Page 1 Features ® • High-performance and Low-power AVR 8-bit RISC Architecture – 118 Powerful Instructions - Most Single Cycle Execution – 32 x 8 General Purpose Working Registers – Up to 8 MIPS Throughput at 8 MHz • Data and Nonvolatile Program Memory –...
- Page 2 SPI serial interface or by a conventional nonvolatile memory programmer. By combining a RISC 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT90S2333/4433 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.
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Page 3: Block Diagram
AT90S/LS2333 and AT90S/LS4433 Block Diagram Figure 1. The AT90S2333/4433 Block Diagram PC0 - PC5 PORTC DRIVERS DATA REGISTER DATA DIR. PORTC REG. PORTC AVCC ANALOG MUX AGND XTAL1 AREF INTERNAL OSCILLATOR OSCILLATOR XTAL2 PROGRAM STACK WATCHDOG TIMING AND RESET COUNTER POINTER TIMER CONTROL... -
Page 4: Pin Descriptions
Pin Descriptions Supply voltage Ground Port B (PB5..PB0) Port B is a 6-bit bi-directional I/O port with internal pullup resistors. The Port B output buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. Port B also serves the functions of various special features of the AT90S2333/4433 as listed on page 60. -
Page 5: Clock Options
AT90S/LS2333 and AT90S/LS4433 Clock Options Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an on- chip oscillator, as shown in Figure 2 and Figure 3. Either a quartz crystal or a ceramic resonator may be used. External Clock If the oscillator is to be used as a clock for an external device, the clock signal from XTAL2 may be routed to one HC buffer, while reducing the load capacitor by 5 pF, as shown in Figure 3. -
Page 6: Architectural Overview
This is enabled by the fact that the register file is assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing them to be accessed as though they were ordinary memory locations. Figure 5. The AT90S2333/4433 AVR RISC Architecture AVR AT90S2333/4433 Architecture Data Bus 8-bit Program... - Page 7 AT90S/LS2333 and AT90S/LS4433 The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters, A/D- converters, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the register file, $20 - $5F. The AVR uses a Harvard architecture concept - with separate memories and buses for program and data.
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Page 8: General Purpose Register File
General Purpose Register File Figure 7 shows the structure of the 32 general purpose working registers in the CPU. Figure 7. AVR CPU General Purpose Working Registers Addr. … General Purpose Working Registers … X-register low byte X-register high byte Y-register low byte Y-register high byte Z-register low byte... -
Page 9: Alu - Arithmetic Logic Unit
AT90S/LS2333 and AT90S/LS4433 ALU - Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided into three main categories - arithmetic, logical, and bit-functions. -
Page 10: Program And Data Addressing Modes
The 32 general purpose working registers, 64 I/O registers and the 128 bytes of internal data SRAM in the AT90S2333/4433 are all accessible through all these addressing modes. See the next section for a detailed description of the different addressing modes. Program and Data Addressing Modes The AT90S2333/4433 AVR RISC microcontroller supports powerful and efficient addressing modes for access to the Flash program memory, SRAM, Register File, and I/O data memory. - Page 11 AT90S/LS2333 and AT90S/LS4433 I/O Direct Figure 12. I/O Direct Addressing Operand address is contained in 6 bits of the instruction word. n is the destination or source register address. Data Direct Figure 13. Direct Data Addressing Data Space $0000 20 19 Rr/Rd 16 LSBs $00DF...
- Page 12 Data Indirect Figure 15. Data Indirect Addressing Data Space $0000 X, Y, OR Z - REGISTER $00DF Operand address is the contents of the X, Y, or the Z-register. Data Indirect with Pre-Decrement Figure 16. Data Indirect Addressing with Pre-Decrement Data Space $0000 X, Y, OR Z - REGISTER...
- Page 13 AT90S/LS2333 and AT90S/LS4433 Constant Addressing Using the LPM Instruction Figure 18. Code Memory Constant Addressing PROGRAM MEMORY $000 $3FF/$7FF Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 1K/2K), the LSB selects low byte if cleared (LSB = 0) or high byte if set (LSB = 1). Indirect Program Addressing, IJMP and ICALL Figure 19.
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Page 14: Eeprom Data Memory
EEPROM Data Memory The AT90S2333/4433 contains 128/256 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles per location. - Page 15 AT90S/LS2333 and AT90S/LS4433 Figure 23. On-Chip Data SRAM Access Cycles System Clock Ø Address Prev. Address Address Data Data I/O Memory The I/O space definition of the AT90S2333/4433 is shown in the following table: Table 2. AT90S2333/4433 I/O Space I/O Address (SRAM Address) Name Function $3F ($5F)
- Page 16 Table 2. AT90S2333/4433 I/O Space (Continued) I/O Address (SRAM Address) Name Function $15 ($35) PORTC Data Register, Port C $14 ($34) DDRC Data Direction Register, Port C $13 ($33) PINC Input Pins, Port C $12 ($32) PORTD Data Register, Port D $11 ($31) DDRD Data Direction Register, Port D...
- Page 17 AT90S/LS2333 and AT90S/LS4433 Status Register - SREG The AVR status register - SREG - at I/O space location $3F ($5F) is defined as: $3F ($5F) SREG Read/Write Initial value • Bit 7 - I: Global Interrupt Enable The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers.
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Page 18: Reset And Interrupt Handling
instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt RETI. Reset and Interrupt Handling The AT90S2333/4433 provides 13 different interrupt sources. These interrupts and the separate reset vector, each have a separate program vector in the program memory space. - Page 19 AT90S/LS2333 and AT90S/LS4433 $00e MAIN: r16,low(RAMEND); Main program start $00f SP,r16; $010 <instr> … … … … Reset Sources The AT90S2333/4433 has four sources of reset: • Power-On Reset. The MCU is reset when the supply voltage is below the power-on reset threshold (V •...
- Page 20 Table 5. Reset Delay Selections CKSEL [2:0] Start-Up Time, t at V = 2.7V Start-Up Time, t at V = 5.0V Recommended Usage TOUT TOUT 16 ms + 6 CK 4 ms + 6 CK External Clock, slowly rising power 6 CK 6 CK External Clock, BOD enabled...
- Page 21 AT90S/LS2333 and AT90S/LS4433 Figure 26. MCU Start-Up, RESET Controlled Externally RESET TOUT TIME-OUT INTERNAL RESET External Reset An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running.
- Page 22 Figure 28. Brown-Out Reset During Operation BOT+ BOT- RESET TIME-OUT TOUT INTERNAL RESET Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t .
- Page 23 AT90S/LS2333 and AT90S/LS4433 To make use of the reset flags to identify a reset condition, the user should read and then clear the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags.
- Page 24 General Interrupt Flag Register - GIFR $3A ($5A) INTF1 INTF0 GIFR Read/Write Initial value • Bit 7 - INTF1: External Interrupt Flag1 When an event on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the I-bit in SREG and the INT1 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $002.
- Page 25 AT90S/LS2333 and AT90S/LS4433 Timer/Counter Interrupt Flag Register - TIFR $38 ($58) TOV1 OCF1 ICF1 TOV0 TIFR Read/Write Initial value • Bit 7 - TOV1: Timer/Counter1 Overflow Flag The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor- responding interrupt handling vector.
- Page 26 MCU Control Register - MCUCR The MCU Control Register contains control bits for general MCU functions. $35 ($55) ISC11 ISC10 ISC01 ISC00 MCUCR Read/Write Initial value • Bits 7, 6 - Res: Reserved bit These bits are reserved bits in the AT90S2333/4433 and always reads as zero. •...
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Page 27: Sleep Modes
AT90S/LS2333 and AT90S/LS4433 The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt Sleep Modes... -
Page 28: Timer/Counter Prescaler
Timer / Counters The AT90S2333/4433 provides two general purpose Timer/Counters - one 8-bit T/C and one 16-bit T/C. Timer/Counters 0 and 1 have individual prescaling selection from the same 10-bit prescaling timer. These Timer/Counters can either be used as a timer with an internal clock timebase or as a counter with an external pin connection which triggers the counting. Timer/Counter Prescaler Figure 30. - Page 29 AT90S/LS2333 and AT90S/LS4433 Figure 31. Timer/Counter0 Block Diagram Timer/Counter0 Control Register - TCCR0 $33 ($53) CS02 CS01 CS00 TCCR0 Read/Write Initial value • Bits 7-3 - Res: Reserved bits These bits are reserved bits in the AT90S2333/4433 and always read as zero. •...
- Page 30 Timer Counter 0 - TCNT0 $32 ($52) TCNT0 Read/Write Initial value The Timer/Counter0 is realized as an up-counter with read and write access. If the Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues counting in the clock cycle following the write operation. 16-bit Timer/Counter1 Figure 32 shows the block diagram for Timer/Counter1.
- Page 31 AT90S/LS2333 and AT90S/LS4433 When Timer/Counter1 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period.
- Page 32 • Bits 5..2 - Res: Reserved bits These bits are reserved bits in the AT90S2333/4433 and always read zero. • Bits 1,0 - PWM11, PWM10: Pulse Width Modulator Select Bits These bits select PWM operation of Timer/Counter1 as specified in Table 11. This mode is described on page 34. Table 11.
- Page 33 AT90S/LS2333 and AT90S/LS4433 Table 12. Clock 1 Prescale Select CS12 CS11 CS10 Description Stop, the Timer/Counter1 is stopped. CK / 8 CK / 64 CK / 256 CK / 1024 External Pin T1, falling edge External Pin T1, rising edge The Stop condition provides a Timer Enable/Disable function.
- Page 34 Timer/Counter1 Output Compare Register - OCR1H and OCR1L $2B ($4B) OCR1H $2A ($4A) OCR1L Read/Write Initial value The output compare register is a 16-bit read/write register. The Timer/Counter1 Output Compare Register contains the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.
- Page 35 AT90S/LS2333 and AT90S/LS4433 is set or cleared according to the settings of the COM11 and COM10 bits in the Timer/Counter1 Control Register TCCR1. Refer to Table 14 for details. Table 13. Timer TOP Values and PWM Frequency Timer TOP Resolution value Frequency 8-bit...
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Page 36: Watchdog Timer
Table 15. PWM Outputs OCR = $0000 or TOP COM11 COM10 OCR1 Output OC1 $0000 $0000 In PWM mode, the Timer Overflow Flag1, TOV1, is set when the counter changes direction at $0000. Timer Overflow Interrupt1 operates exactly as in normal Timer/Counter mode, i.e. it is executed when TOV1 is set provided that Timer Overflow Interrupt1 and global interrupts are enabled. - Page 37 AT90S/LS2333 and AT90S/LS4433 • Bit 3 - WDE: Watch Dog Enable When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1.
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Page 38: Eeprom Read/Write Access
EEPROM Read/Write Access The EEPROM access registers are accessible in the I/O space. The write access time is in the range of 2.5 - 4ms, depending on the V voltages. A self-timing function lets the user soft- ware detect when the next byte can be written. A special EEPROM Ready interrupt can be set to trigger when the EEPROM is ready to accept new data. -
Page 39: Prevent Eeprom Corruption
AT90S/LS2333 and AT90S/LS4433 • Bit 1 - EEWE: EEPROM Write Enable The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. -
Page 40: Serial Peripheral Interface (Spi)
Serial Peripheral Interface - SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT90S2333/4433 and peripheral devices or between several AVR devices. The AT90S2333/4433 SPI features include the following: • Full-Duplex, 3-Wire Synchronous Data Transfer • Master or Slave Operation •... -
Page 41: Ss Pin Functionality
AT90S/LS2333 and AT90S/LS4433 Figure 37. SPI Master-Slave Interconnection The system is single buffered in the transmit direction and double buffered in the receive direction. This means that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed. When receiving data, however, a received byte must be read from the SPI Data Register before the next byte has been completely shifted in. -
Page 42: Data Modes
Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 38 and Figure 39. Figure 38. SPI Transfer Format with CPHA = 0 and DORD = 0 Figure 39. - Page 43 AT90S/LS2333 and AT90S/LS4433 • Bits 1,0 - SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave. The relationship between SCK and the Oscillator Clock frequency f is shown in the following table: Table 18.
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Page 44: Data Transmission
UART The AT90S2333/4433 features a full duplex (separate receive and transmit registers) Universal Asynchronous Receiver and Transmitter (UART). The main features are: • Baud rate generator generates any baud rate • High baud rates at low XTAL frequencies • 8 or 9 bits data •... -
Page 45: Data Reception
AT90S/LS2333 and AT90S/LS4433 • A new character has been written to UDR before the stop bit from the previous character has been shifted out. The shift register is loaded when the stop bit of the character currently being transmitted has been shifted out. When data is transferred from UDR to the shift register, the UDRE (UART Data Register Empty) bit in the UART Status Register, USR, is set. - Page 46 The receiver front-end logic samples the signal on the RXD pin at a frequency 16 times the baud rate. While the line is idle, one single sample of logical zero will be interpreted as the falling edge of a start bit, and the start bit detection sequence is initiated.
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Page 47: Uart Control
AT90S/LS2333 and AT90S/LS4433 3. Each slave MCU reads the UDR register and determines if it has been selected. If so, it clears the MPCM bit in UCSRA, otherwise it waits for the next address byte. 4. For each received data byte, the receiving MCU will set the receive complete flag (RXC in UCSRA). In 8-bit mode, the receiving MCU will also generate a framing error (FE in UCSRA set), since the stop bit is zero. - Page 48 • Bit 3 - OR: OverRun This bit is set if an Overrun condition is detected, i.e. when a character already present in the UDR register is not read before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDRE is read.
- Page 49 AT90S/LS2333 and AT90S/LS4433 For standard crystal frequencies, the most commonly used baud rates can be generated by using the UBR settings in Table 19. UBR values which yield an actual baud rate differing less than 2% from the target baud rate, are bold in the table. However, using baud rates that have more than 1% error is not recommended.
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Page 50: Analog Comparator
UART Baud Rate Register - UBRR $03 ($23) UBRRHI $09 ($29) UBRR Read/Write Initial value This is a 12-bit register which contains the UART Baud Rate according to the equation on the previous page. The UBRRHI contains the 4 most significant bits, and the UBRR contains the 8 least significant bits of the UART Baud Rate. Analog Comparator The analog comparator compares the input values on the positive input PD6 (AIN0) and negative input PD7 (AIN1). - Page 51 AT90S/LS2333 and AT90S/LS4433 • Bit 6 - AINBG: Analog Comparator Bandgap Select When this bit is set BOD is enabled and the BODEN is programmed, a fixed bandgap voltage of 1.22 ± 0.05V replaces the normal input to the positive input (AIN0) of the comparator. When this bit is cleared, the normal input pin PD6 is applied to the positive input of the comparator.
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Page 52: Analog To Digital Converter
Analog to Digital Converter Feature list: • 10-bit Resolution • ± 2 LSB Absolute Accuracy • 0.5 LSB Integral Non-Linearity • 65 - 260 µs Conversion Time • Up to 15 kSPS • 6 Multiplexed Input Channels • Rail-to-Rail Input Range •... - Page 53 AT90S/LS2333 and AT90S/LS4433 The ADC is enabled by writing a logical one to the ADC Enable bit, ADEN in ADCSR. The first conversion that is started after enabling the ADC, will be preceded by a dummy conversion to initialize the ADC. To the user, the only difference will be that this conversion takes 12 more clock cycles than a normal conversion.
- Page 54 Figure 46. ADC Timing Diagram, First Conversion (Single Conversion Mode) Cycle number ADC clock ADEN ADSC Hold strobe ADIF ADCH MSB of result ADCL LSB of result Second Dummy Conversion Actual Conversion Conversion Table 21. ADC Conversion Time Result Ready (cycle Total Conversion Time Total Conversion Time Condition...
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Page 55: Adc Noise Canceler Function
AT90S/LS2333 and AT90S/LS4433 Figure 48. ADC Timing Diagram, Free Run Conversion Cycle number ADC clock ADSC Hold strobe ADIF ADCH MSB of result ADCL LSB of result One Conversion Next Conversion ADC Noise Canceler Function The ADC features a noise canceler that enables conversion during idle mode to reduce noise induced from the CPU core. To make use of this feature, the following procedure should be used: 1. - Page 56 ADC Control and Status Register - ADCSR $06 ($26) ADEN ADSC ADFR ADIF ADIE ADPS2 ADPS1 ADPS0 ADCSR Read/Write Initial value • Bit 7 - ADEN: ADC Enable Writing a logical ‘1’ to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.
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Page 57: Scanning Multiple Channels
AT90S/LS2333 and AT90S/LS4433 ADC Data Register - ADCL AND ADCH $05 ($25) ADC9 ADC8 ADCH $04 ($26) ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL Read/Write Initial value When an ADC conversion is complete, the result is found in these two registers. In free-run mode, it is essential that both registers are read, and that ADCL is read before ADCH. -
Page 58: Adc Characteristics
Figure 49. ADC Power Connections PC5 (ADC5) PC4 (ADC4) PC3 (ADC3) PC2 (ADC2) PC1 (ADC1) PC0 (ADC0) 100R AGND AREF AVCC 10nF Note that since AV feeds the Port C output drivers, the RC network shown should not be employed if any Port C serve as outputs. - Page 59 AT90S/LS2333 and AT90S/LS4433 I/O Ports All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direc- tion of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions.
- Page 60 The Port B Input Pins address - PINB - is not a register, and this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the pins are read.
- Page 61 AT90S/LS2333 and AT90S/LS4433 Figure 50. Port B Schematic Diagram (Pin PB0) PULL- RESET DDB6 RESET PORTB0 WRITE PORTB WRITE DDRB NOISE CANCELER EDGE SELECT ICF1 READ PORTB LATCH READ PORTB PIN READ DDRB ICNC1 ICES1 ACIC: COMPARATOR IC ENABLE ACIC ACO: COMPARATOR OUTPUT Figure 51.
- Page 62 Figure 52. Port B Schematic Diagram (Pin PB2) PULL- RESET DDB2 RESET PORTB2 MSTR WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB MSTR: SPI MASTER ENABLE SPI SS SPE: SPI ENABLE Figure 53. Port B Schematic Diagram (Pin PB3) PULL- RESET DDB3...
- Page 63 AT90S/LS2333 and AT90S/LS4433 Figure 54. Port B Schematic Diagram (Pin PB4) PULL- RESET DDB4 RESET PORTB4 WRITE PORTB MSTR WRITE DDRB READ PORTB LATCH SPI SLAVE READ PORTB PIN READ DDRB SPI ENABLE SPE: MASTER SELECT MSTR SPI MASTER Figure 55. Port B Schematic Diagram (Pin PB5) PULL- RESET DDB5...
- Page 64 Port C Port C is a 6-bit bi-directional I/O port. Three I/O memory address locations are allocated for the Port C, one each for the Data Register - PORTC, $15($35), Data Direction Register - DDRC, $14($34) and the Port C Input Pins - PINC, $13($33). The Port C Input Pins address is read only, while the Data Register and the Data Direction Register are read/write.
- Page 65 AT90S/LS2333 and AT90S/LS4433 Table 25. DDCn Effects on Port C Pins DDCn PORTCn Pull Up Comment Input Tri-state (Hi-Z) Input PCn will source current if ext. pulled low. Output Push-Pull Zero Output Output Push-Pull One Output Note: n: 5…0, pin number Port C Schematics Note that all port pins are synchronized.
- Page 66 Table 26. Port D Pins Alternate Functions Port Pin Alternate Function RXD (UART Input line) TXD (UART Output line) INT0 (External interrupt 0 input) INT1 (External interrupt 1 input) T0 (Timer/Counter 0 external counter input) T1 (Timer/Counter 1 external counter input) AIN0 (Analog comparator positive input) AIN1 (Analog comparator negative input) Port D Data Register - PORTD...
- Page 67 AT90S/LS2333 and AT90S/LS4433 Table 27. DDDn Bits on Port D Pins DDDn PORTDn Pull Up Comment Input Tri-state (Hi-Z) Input PDn will source current if ext. pulled low. Output Push-Pull Zero Output Output Push-Pull One Output Note: n: 7,6…0, pin number. Alternate Functions Of Port D •...
- Page 68 Port D Schematics Note that all port pins are synchronized. The synchronization latches are however, not shown in the figures. Figure 57. Port D Schematic Diagram (Pin PD0) PULL- RESET DDD0 RESET PORTD0 RXEN WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD RXD:...
- Page 69 AT90S/LS2333 and AT90S/LS4433 Figure 59. Port D Schematic Diagram (Pins PD2 and PD3) Figure 60. Port D Schematic Diagram (Pins PD4 and PD5) DDDn PORTBn WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD 4, 5...
- Page 70 Figure 61. Port D Schematic Diagram (Pins PD6 and PD7) PULL- RESET DDDn RESET PORTDn PWRDN AINm TO COMPARATOR WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD PWRDN: POWER DOWN MODE 6, 7 0, 1 AT90S/LS2333 and AT90S/LS4433...
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Page 71: Memory Programming
• CKSEL2..0: See Table 5, “Reset Delay Selections”, for which combination of CKSEL2..0 to use. Default value is ‘010’. Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and parallel mode. The three bytes reside in a separate address space. -
Page 72: Parallel Programming
The Program and Data memory arrays on the AT90S2333/4433 are programmed byte-by-byte in either programming modes. For the EEPROM, an auto-erase cycle is provided within the self-timed write instruction in the serial programming mode. During programming, the supply voltage must be in accordance with Table 29. Table 29. - Page 73 AT90S/LS2333 and AT90S/LS4433 Table 30. Pin Name Mapping Signal Name in Programming Mode Pin Name Function RDY/BSY 0: Device is busy programming, 1: Device is ready for new command Output Enable (Active low) Write Pulse (Active low) Byte Select (‘0’ selects low byte, ‘1’ selects high byte) XTAL Action Bit 0 XTAL Action Bit 1 DATA...
- Page 74 1. Set XA1, XA0 to ‘10’. This enables command loading. 2. Set BS to ‘0’. 3. Set DATA to ‘1000 0000’. This is the command for Chip erase. 4. Give XTAL1 a positive pulse. This loads the command. 5. Give WR a wide negative pulse to execute Chip Erase.
- Page 75 AT90S/LS2333 and AT90S/LS4433 • Address high byte needs only be loaded before programming a new 256 word page in the Flash. • Skip writing the data value $FF, that is the contents of the entire Flash and EEPROM after a Chip Erase. These considerations also applies to EEPROM programming, and Flash, EEPROM and Signature bytes reading.
- Page 76 Programming the EEPROM The programming algorithm for the EEPROM data memory is as follows (refer to Programming the Flash for details on Command, Address and Data loading): 1. A: Load Command ‘0001 0001’. 2. C: Load Address Low Byte ($00 - $7F/$FF). 3.
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Page 77: Parallel Programming Characteristics
AT90S/LS2333 and AT90S/LS4433 Bit 5 = SPIEN Fuse bit Bit 4 = BODLEVEL Fuse bit Bit 3 = BODEN Fuse bit Bit 2 = CKSEL2 Fuse bit Bit 1 = CKSEL1 Fuse bit Bit 0 = CKSEL0 Fuse bit 3. Set BS to ‘1’. The status of the Lock bits can now be read at DATA (‘0’ means programmed). Bit 2 = Lock Bit2 Bit 1= Lock Bit1 4. -
Page 78: Serial Downloading
Table 33. Parallel Programming Characteristics T = 25°C ± 10%, V =5V ± 10% Symbol Parameter Units Programming Enable Voltage 11.5 12.5 µΑ Programming Enable Current Data and Control Setup before XTAL1 High DVXH XTAL1 Pulse Width High XHXL Data and Control Hold after XTAL1 Low XLDX XTAL1 Low to WR Low XLWL... - Page 79 AT90S/LS2333 and AT90S/LS4433 For the EEPROM, an auto-erase cycle is provided within the self-timed write instruction and there is no need to first exe- cute the Chip Erase instruction. The Chip Erase instruction turns the content of every memory location in both the Program and EEPROM arrays into $FF.
- Page 80 Data Polling EEPROM When a byte is being programmed into the EEPROM, reading the address location being programmed will give the value P1 until the auto-erase is finished, and then the value P2. See Table 34 for P1 and P2 values. At the time the device is ready for a new EEPROM byte, the programmed value will read correctly.
- Page 81 AT90S/LS2333 and AT90S/LS4433 Table 35. Serial Programming Instruction Set Instruction Instruction Format Operation Byte 1 Byte 2 Byte 3 Byte4 Enable Serial Programming while 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Programming Enable RESET is low. Chip Erase Flash and EEPROM 1010 1100 100x xxxx xxxx xxxx...
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Page 82: Serial Programming Characteristics
Serial Programming Characteristics Figure 68. Serial Programming Timing MOSI SLSH OVSH SHOX SHSL MISO SLIV Table 36. Serial Programming Characteristics = -40°C to 85°C, V = 2.7 - 6.0V (Unless otherwise noted) Symbol Parameter Units Oscillator Frequency (V = 2.7 - 6.0V) CLCL Oscillator Period (V = 2.7 - 6.0V) -
Page 83: Electrical Characteristics
AT90S/LS2333 and AT90S/LS4433 Electrical Characteristics Absolute Maximum Ratings* *NOTICE: Stresses beyond those listed under “Absolute Operating Temperature........-55°C to +125°C Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and Storage Temperature ........-65°C to +150°C functional operation of the device at these or Voltage on any Pin except RESET other conditions beyond those indicated in the... - Page 84 DC Characteristics = -40°C to 85°C, V = 2.7V to 6.0V (unless otherwise noted) (Continued) Symbol Parameter Condition Units Analog Comparator Input = 5V ACIO Offset Voltage = 5V Analog Comparator Input ACLK Leakage A Analog Comparator = 2.7V ACPD Propagation Delay = 4.0V Notes:...
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Page 85: External Clock Drive Waveforms
AT90S/LS2333 and AT90S/LS4433 External Clock Drive Waveforms Figure 69. External Clock VIH1 VIL1 Table 39. External Clock Drive = 2.7V to 6.0V = 4.0V to 6.0V Symbol Parameter Units Oscillator Frequency CLCL Clock Period CLCL High Time CHCX Low Time CLCX µs Rise Time... -
Page 86: Typical Characteristics
Typical Characteristics The following charts show typical behavior. These data are characterized, but not tested. All current consumption measure- ments are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail to rail output is used as clock source. The power consumption in power-down mode is independent of clock selection. - Page 87 AT90S/LS2333 and AT90S/LS4433 Figure 71. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs. V FREQUENCY = 4 MHz T = 25 ˚ T = 85 ˚ Figure 72. Idle Supply Current vs. Frequency IDLE SUPPLY CURRENT vs. FREQUENCY T = 25˚C = 6V = 5.5V = 5V...
- Page 88 Figure 73. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs. V FREQUENCY = 4 MHz T = 85 ˚ T = 25 ˚ Figure 74. Power Down Supply Current vs. V POWER DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER DISABLED T = 85 ˚...
- Page 89 AT90S/LS2333 and AT90S/LS4433 Figure 75. Power Down Supply Current vs. V POWER DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ENABLED T = 85 ˚ T = 25 ˚ Figure 76. Power Down Supply Current vs. V POWER DOWN SUPPLY CURRENT vs. V BROWN OUT DETECTOR ENABLED T = 85 ˚...
- Page 90 Figure 77. Analog Comparator Current vs. V ANALOG COMPARATOR CURRENT vs. V T = 25 ˚ T = 85 ˚ Analog comparator offset voltage is measured as absolute offset Figure 78. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE V = 5V T = 25...
- Page 91 AT90S/LS2333 and AT90S/LS4433 Figure 79. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE V = 2.7V T = 25 ˚ T = 85 ˚ Common Mode Voltage (V) Figure 80. Analog Comparator Input Leakage Current ANALOG COMPARATOR INPUT LEAKAGE CURRENT V = 6V T = 25...
- Page 92 Figure 81. Watchdog Oscillator Frequency vs. V WATCHDOG OSCILLATOR FREQUENCY vs. V 1600 T = 25 ˚ 1400 T = 85 ˚ 1200 1000 V (V) AT90S/LS2333 and AT90S/LS4433...
- Page 93 AT90S/LS2333 and AT90S/LS4433 Sink and source capabilities of I/O ports are measured on one pin at a time. Figure 82. Pull-Up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE V = 5V T = 25 ˚ T = 85 ˚...
- Page 94 Figure 84. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE V = 5V T = 25 ˚ T = 85 ˚ Figure 85. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE V = 5V T = 25 ˚...
- Page 95 AT90S/LS2333 and AT90S/LS4433 Figure 86. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE V = 2.7V T = 25 ˚ T = 85 ˚ Figure 87. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE V = 2.7V T = 25 ˚...
- Page 96 Figure 88. I/O Pin Input Threshold Voltage vs. V I/O PIN INPUT THRESHOLD VOLTAGE vs. V T = 25 ˚ Figure 89. I/O Pin Input Hysteresis vs. V I/O PIN INPUT HYSTERESIS vs. V T = 25 ˚ 0.18 0.16 0.14 0.12 0.08...
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Page 97: Register Summary
AT90S/LS2333 and AT90S/LS4433 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page $3F ($5F) SREG page 17 $3E ($5E) Reserved page 17 $3D ($5D) page 17 $3C ($5C) Reserved $3B ($5B) GIMSK... - Page 98 Register Summary (Continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page $02 ($22) Reserved $01 ($21) Reserved $00 ($20) Reserved Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.
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Page 99: Instruction Set Summary
AT90S/LS2333 and AT90S/LS4433 Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS Rd ← Rd + Rr Rd, Rr Add two Registers Z,C,N,V,H Rd ← Rd + Rr + C Rd, Rr Add with Carry two Registers Z,C,N,V,H Rdh:Rdl ←... - Page 100 Instruction Set Summary (Continued) Mnemonics Operands Description Operation Flags #Clocks DATA TRANSFER INSTRUCTIONS Rd ← Rr Rd, Rr Move Between Registers None Rd ← K Rd, K Load Immediate None Rd ← (X) Rd, X Load Indirect None Rd ← (X), X ← X + 1 Rd, X+ Load Indirect and Post-Inc.
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Page 101: Ordering Information
AT90S/LS2333 and AT90S/LS4433 Ordering Information Power Supply Speed (MHz) Ordering Code Package Operation Range 2.7 - 6.0V AT90LS2333-4AC Commercial ° ° AT90LS2333-4PC 28P3 C to 70 AT90LS2333-4AI Industrial ° ° AT90LS2333-4PI 28P3 (-40 C to 85 4.0 - 6.0V AT90S2333-8AC Commercial °... -
Page 102: Packaging Information
Packaging Information 28P3, 28-lead, 0.300” Wide, 32A, 32-lead, Thin (1.0 mm) Plastic Gull Wing Quad Plastic Dual Inline Package (PDIP) Flat Package (TQFP) Dimensions in Inches and (Millimeters) Dimensions in Millimeters and (Inches) PIN 1 ID 9.00 (0.354) BSC 0.45 (0.018) 0.30 (0.012) 0.80 (0.031) BSC 9.00 (0.354) BSC... - Page 103 No licenses to patents or other intellectual prop- erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life suppor t devices or systems.
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