Atmel AT90PWM2 Manual page 255

21.10 Amplifier Control Registers
21.10.1 Amplifier 0 Control and Status register – AMP0CSR
AT90PWM2/3/2B/3B
256
The block diagram of the two amplifiers is shown on
Figure 21-18. Amplifiers block diagram
AMP0+
AMP0-
Sampling
AMP0EN AMP0IS AMP0G1 AMP0G0
AMP1+
AMP1-
Sampling
AMP1EN AMP1IS AMP1G1 AMP1G0
The configuration of the amplifiers are controlled via two dedicated registers AMP0CSR and
AMP1CSR. Then the start of conversion is done via the ADC control and status registers.
The conversion result is stored on ADCH and ADCL register which contain respectively the most
significant bits and the less significant bits.
Bit 7
AMP0EN AMP0IS
Read/Write R/W
Initial Value 0
+
-
00
01
10
01
Clock
AMP0CSR
+
-
00
01
10
01
Clock
AMP1CSR
6 5 4
AMP0G1 AMP0G0
R/W R/W R/W
0 0 0
Figure 21-18.
Toward ADC MUX
(AMP0)
ADCK/8
ASY0
ASY1
ASY2
- - AMP0TS1AMP0TS0
Toward ADC MU
(AMP1)
ADCK/8
ASY0
ASY1
ASY2
- - AMP1TS1AMP1TS0
3 2 1
- - AMP0TS1
- - R/W
0 0 0
0
AMP0TS0 AMP0CSR
R/W
0
4317I–AVR–01/08