Atmel AT90PWM2 Manual page 123

AT90PWM2/3/2B/3B
124
I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit correspond-
ing to the OCnA or OCnB pin must be set in order to enable the output driver.
When the OCnA or OCnB is connected to the pin, the function of the COMnx1:0 bits is depen-
dent of the WGMn3:0 bits setting.
WGMn3:0 bits are set to a Normal or a CTC mode (non-PWM).
Table 15-1. Compare Output Mode, non-PWM
COMnA1/COMnB1 COMnA0/COMnB0
0
0
1
1
Table 15-3 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast
PWM mode.
Table 15-2. Compare Output Mode, Fast PWM
COMnA1/COMnB1 COMnA0/COMnB0
0
0
1
1
Note: 1. A special case occurs when OCRnA/OCRnB equals TOP and COMnA1/COMnB1 is set. In
this case the compare match is ignored, but the set or clear is done at TOP.
Mode" on page 116.
Table 15-4 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase
correct or the phase and frequency correct, PWM mode.
Table 15-3. Compare Output Mode, Phase Correct and Phase and Frequency Correct
(1)
PWM
COMnA1/COMnB1 COMnA0/COMnB0
0
Table 15-2 shows the COMnx1:0 bit functionality when the
Description
0 Normal port operation, OCnA/OCnB disconnected.
1 Toggle OCnA/OCnB on Compare Match.
Clear OCnA/OCnB on Compare Match (Set output to
0
low level).
Set OCnA/OCnB on Compare Match (Set output to
1
high level).
(1)
Description
0 Normal port operation, OCnA/OCnB disconnected.
WGMn3:0 = 14 or 15: Toggle OC1A on Compare
Match, OC1B disconnected (normal port operation).
1
For all other WGM1 settings, normal port operation,
OC1A/OC1B disconnected.
Clear OCnA/OCnB on Compare Match, set
0
OCnA/OCnB at TOP
Set OCnA/OCnB on Compare Match, clear
1
OCnA/OCnB at TOP
for more details.
Description
0 Normal port operation, OCnA/OCnB disconnected.
See "Fast PWM
4317I–AVR–01/08