Atmel AT90PWM2 Manual page 21

6.3.3 The EEPROM Data Register – EEDR
6.3.4 The EEPROM Control Register – EECR
AT90PWM2/3/2B/3B
22
EEAR7 EEAR6
7 6
Read/Write R R
R/W R/W
Initial Value 0 0
X X
• Bits 15..9 – Reserved Bits
These bits are reserved bits in the AT90PWM2/2B/3/3B and will always read as zero.
• Bits 8..0 – EEAR8..0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the
512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and
511. The initial value of EEAR is undefined. A proper value must be written before the EEPROM
may be accessed.
Bit 7 6
EEDR7 EEDR6
Read/Write R/W R/W
Initial Value 0 0
• Bits 7..0 – EEDR7.0: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
Bit 7 6
– –
Read/Write R R
Initial Value 0 0
• Bits 7..6 – Reserved Bits
These bits are reserved bits in the AT90PWM2/2B/3/3B and will always read as zero.
• Bits 5..4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits
The EEPROM Programming mode bit setting defines which programming action that will be trig-
gered when writing EEWE. It is possible to program data in one atomic operation (erase the old
value and program the new value) or to split the Erase and Write operations in two different
operations. The Programming times for the different modes are shown in
EEWE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to
0b00 unless the EEPROM is busy programming.
Table 6-1. EEPROM Mode Bits
Programming
EEPM1 EEPM0
0 0 3.4 ms
0 1 1.8 ms
1 0 1.8 ms
1 1
EEAR5 EEAR4 EEAR3
5 4 3
R R R
R/W R/W R/W
0 0 0
X X X
5 4 3
EEDR5 EEDR4 EEDR3
R/W R/W R/W
0 0 0
5 4 3
EEPM1 EEPM0 EERIE
R/W R/W R/W
X X 0
Time Operation
Erase and Write in one operation (Atomic Operation)
Erase Only
Write Only
– Reserved for future use
EEAR2 EEAR1 EEAR0
2 1 0
R R R/W
R/W R/W R/W
0 0 X
X X X
2 1 0
EEDR2 EEDR1 EEDR0
R/W R/W R/W
0 0 0
2 1 0
EEMWE EEWE EERE
R/W R/W R/W
0 X 0
Table
EEARL
EEDR
EECR
6-1. While
4317I–AVR–01/08