Atmel ATmega128 Manuals

Atmel ATmega128 Manuals

Manuals and User Guides for Atmel ATmega128. We have 1 Atmel ATmega128 manual available for free PDF download: Manual

Atmel ATmega128 Manual

Atmel ATmega128 Manual (387 pages)

8-bit AVR Microcontroller with 128K Bytes In-System Programmable Flash

Brand: Atmel | Category: Microcontrollers | Size: 6.36 MB

Table of Contents

Table of Features

1
Pin Configurations

2
Overview

2
Resources

8
Data Retention

8
About Code Examples

9
AVR CPU Core

10
- Architectural Overview
  10
- Introduction
  10
- ALU - Arithmetic Logic Unit
  11
- Status Register
  11
- General Purpose Register File
  12
- AVR CPU General Purpose Working Registers
  13
- Stack Pointer
  14
- Instruction Execution Timing
  14
- Reset and Interrupt Handling
  15
- Interrupt Response Time
  17
AVR Atmega128 Memories

18
- In-System Reprogrammable Flash Program Memory
  18
- SRAM Data Memory
  19
  - Memory Configurations
    19
  - Data Memory Map
    20
- EEPROM Data Memory
  21
- I/O Memory
  26
- External Memory Interface
  26
  - External Memory with Sector Select
    27
  - Address Latch Requirements
    28
  - External SRAM Connected to the AVR
    28
  - Pull-Up and Bus-Keeper
    29
  - Timing
    29
  - XMEM Register Description
    31
  - MCU Control Register
    31
  - External Memory Control Register a –XMCRA
    31
System Clock and Clock Options

36
Power Management and Sleep Modes

45
- Idle Mode
  46
- ADC Noise Reduction Mode
  46
- Power-Down Mode
  46
- Power-Save Mode
  46
- Standby Mode
  47
- Extended Standby Mode
  47
- Minimizing Power Consumption
  48
  - Analog to Digital Converter
    48
  - Analog Comparator
    48
  - Brown-Out Detector
    48
  - JTAG Interface and On-Chip Debug System
    49
System Control and Reset

50
- Reset Sources
  50
- Resetting the AVR
  50
- Reset Characteristics
  51
- Reset Logic
  51
- External Reset
  52
- Power-On Reset
  52
- Brown-Out Detection
  53
- External Reset During Operation
  53
- Internal Voltage Reference
  54
- Watchdog Timer
  55
- Timed Sequences for Changing the Configuration of the Watchdog Timer
  58
- Interrupt Vectors in Atmega128
  60
- Interrupt Vector Change Enable
  65
I/O Ports

66
External Interrupts

90
- Interrupt Sense Control
  91
- Asynchronous External Interrupt Characteristics
  91
8-Bit Timer/Counter0 with PWM and Asynchronous Operation

93
- Overview
  93
- Timer/Counter Clock Sources
  94
- Counter Unit
  94
- Output Compare Unit
  95
- Compare Match Output Unit
  97
- Compare Output Mode and Waveform Generation
  97
- Modes of Operation
  98
  - Normal Mode
    98
  - Clear Timer on Compare Match (CTC) Mode
    98
  - Fast PWM Mode
    99
  - Fast PWM Mode, Timing Diagram
    100
  - Phase Correct PWM Mode
    101
  - Phase Correct PWM Mode, Timing Diagram
    101
- Timer/Counter Timing Diagrams
  102
- Timer/Counter Timing Diagram
  103
- 8-Bit Timer/Counter Register Description
  104
- Asynchronous Operation of the Timer/Counter
  107
- Timer/Counter Prescaler
  110
16-Bit Timer/Counter (Timer/Counter1 and Timer/Counter3)

112
- Overview
  112
- Accessing 16-Bit Registers
  115
- Timer/Counter Clock Sources
  118
- Counter Unit
  118
- Input Capture Unit
  119
  - Input Capture Pin Source
    120
  - Noise Canceler
    120
  - Using the Input Capture Unit
    120
- Output Compare Units
  121
  - Force Output Compare
    122
  - Using the Output Compare Unit
    122
- Compare Match Output Unit
  123
- Modes of Operation
  124
- Phase and Frequency Correct PWM Mode
  129
- Timer/Counter Timing Diagrams
  131
- 16-Bit Timer/Counter Register Description
  133
  - SPI Status Register
    169
  - Data Modes
    170
  - Usart
    171
  - Dual USART
    171
  - USART Block Diagram
    172
  - Asynchronous Clock
    185
  - Using MPCM
    188
  - USART Register Description
    189
  - Usartn I/O Data Register – Udrn
    189
  - Usartn Control and Status Register B
    190
  - Examples of Baud Rate Setting
    194
  - Examples of UBRR Settings for Commonly Used Oscillator Frequencies
    195
  - Two-Wire Serial Interface
    198
  - Two-Wire Serial Interface Bus Definition
    198
  - TWI Terminology
    198
  - Electrical Interconnection
    198
  - Data Transfer and Frame Format
    199
  - Transferring Bits
    199
  - START and STOP Conditions
    199
  - Address Packet Format
    200
  - Data Packet Format
    200
  - Combining Address and Data Packets into a Transmission
    201
  - Multi-Master Bus Systems, Arbitration and Synchronization
    201
  - Overview of the TWI Module
    204
  - Scl and SDA Pins
    204
  - Bit Rate Generator Unit
    204
  - Bus Interface Unit
    204
  - Address Match Unit
    205
  - Control Unit
    205
  - TWI Register Description
    206
  - TWI Bit Rate Register
    206
  - TWI Control Register
    206
  - TWI Status Register
    207
  - Interfacing the Application to the TWI in a Typical Transmission
    209
  - Data Transfer in Master Transmitter Mode
    214
  - Status Codes for Master Transmitter Mode
    215
  - Formats and States in the Master Transmitter Mode
    216
  - Master Receiver Mode
    217
  - Data Transfer in Master Receiver Mode
    217
  - Formats and States in the Master Receiver Mode
    218
  - Status Codes for Master Receiver Mode
    219
  - Status Codes for Slave Receiver Mode
    221
  - Slave Transmitter Mode
    222
  - Formats and States in the Slave Receiver Mode
    222
  - Data Transfer in Slave Transmitter Mode
    222
  - Status Codes for Slave Transmitter Mode
    223
  - Formats and States in the Slave Transmitter Mode
    224
  - Combining Several TWI Modes
    225
  - Multi-Master Systems and Arbitration
    225
  - An Arbitration Example
    226
  - Possible Status Codes Caused by Arbitration
    226
  - Special Function IO Register
    227
  - Analog Comparator Control and Status Register
    227
  - ACIS1/ACIS0 Settings
    228
  - Analog Comparator Multiplexed Input
    229
  - Analog to Digital Converter Block Schematic
    231
  - Prescaling and Conversion Timing
    233
  - ADC Prescaler
    233
  - ADC Timing Diagram, First Conversion
    234
  - ADC Timing Diagram, Single Conversion
    234
  - ADC Timing Diagram, Free Running Conversion
    234
  - ADC Conversion Time
    235
  - ADC Input Channels
    236
  - ADC Voltage
    236
  - ADC Noise
    236
  - Analog Input Circuitry
    237
  - Analog Noise Canceling Techniques
    237
  - ADC Power Connections
    238
  - Offset Compensation Schemes
    238
  - ADC Accuracy Definitions
    239
  - Offset Error
    239
  - Gain Error
    239
  - Integral Non-Linearity (INL)
    240
  - Differential Non-Linearity (DNL)
    240
  - ADC Conversion Result
    241
  - Differential Measurement Range
    241
  - Correlation between Input Voltage and Output Codes
    242
  - Voltage Reference Selections for ADC
    242
  - Input Channel and Gain Selections
    243
  - ADC Prescaler Selections
    245
  - TAP Controller State Diagram
    248
  - TAP Controller
    248
  - Using the On-Chip Debug System
    249
  - On-Chip Debug Related Register in I/O Memory
    251
  - Using the JTAG Programming Capabilities
    251
  - Bibliography
    251
  - Bypass Register
    253
  - Device Identification Register
    253
  - Reset Register
    253
  - Boundary-Scan Specific JTAG Instructions
    254
  - General Port Pin Schematic Diagram
    257
  - Additional Scan Signal for the Two-Wire Interface
    258
  - Observe-Only Cell
    258
  - Boundary-Scan Cells for Oscillators and Clock Options
    259
  - General Boundary-Scan Cell Used for Signals for Comparator and ADC
    260
  - Boundary-Scan Signals for the Analog Comparator
    261
  - Boundary-Scan Signals for the ADC
    262
  - Algorithm for Using the ADC
    265
  - Atmega128 Boundary-Scan Order
    266
  - Boot Loader Lock Bits
    275
  - Memory Sections
    275
  - Boot Lock Bit0 Protection Modes (Application Section)
    276
  - Boot Lock Bit1 Protection Modes (Boot Loader Section)
    276
  - Boot Reset Fuse
    276
  - Addressing the Flash During SPM
    279
  - Setting the Boot Loader Lock Bits
    281
  - EEPROM Write Prevents Writing to SPMCSR
    281
  - Reading the Fuse and Lock Bits from Software
    281
  - Preventing Flash Corruption
    282
  - Programming Time for Flash When Using SPM
    282
  - Simple Assembly Code Example for a Boot Loader
    282
  - Atmega128 Boot Loader Parameters
    284
  - Explanation of Different Variables
    285
  - Memory Programming
    286
  - Program and Data Memory Lock Bits
    286
  - Lock Bit Byte
    286
  - Lock Bit Protection Modes
    286
  - Fuse Bits
    287
  - Extended Fuse Byte
    287
  - Latching of Fuses
    288
  - Fuse High Byte
    288
  - Fuse Low Byte
    288
  - Signature Bytes
    289
  - Calibration Byte
    289
  - Signal Names
    290
  - Parallel Programming
    290
  - Pin Name Mapping
    290
  - Pin Values Used to Enter Programming Mode
    291
  - XA1 and XA0 Coding
    291
  - Command Byte Bit Coding
    291
  - Enter Programming Mode
    292
  - Considerations for Efficient Programming
    292
  - Chip Erase
    292
  - Programming the Flash
    293
  - Addressing the Flash Which Is Organized in Pages
    294
  - Programming the EEPROM
    295
  - Programming the Flash Waveforms
    295
  - Reading the Flash
    296
  - Reading the EEPROM
    296
  - Programming the Fuse Low Bits
    296
  - Programming the EEPROM Waveforms
    296
  - Programming the Fuse High Bits
    297
  - Programming the Extended Fuse Bits
    297
  - Programming the Lock Bits
    297
  - Reading the Fuse and Lock Bits
    297
  - Reading the Signature Bytes
    298
  - Reading the Calibration Byte
    298
  - Parallel Programming Characteristics
    298
  - Parallel Programming Timing, Loading Sequence with Timing Requirements
    299
  - Serial Downloading
    300
  - SPI Serial Programming Pin Mapping
    300
  - SPI Serial Programming Algorithm
    301
  - SPI Serial Programming and Verify
    301
  - Data Polling Flash
    302
  - Data Polling EEPROM
    302
  - Minimum Wait Delay before Writing the Next Flash or EEPROM Location
    303
  - SPI Serial Programming Waveforms
    303
  - SPI Serial Programming Instruction Set
    304
  - Programming Via the JTAG Interface
    305
  - Programming Specific JTAG Instructions
    305
  - State Machine Sequence for Changing the Instruction Word
    306
  - Programming Command Register
    309
  - JTAG Programming Instruction
    310
  - Virtual Flash Page Load Register
    313
  - State Machine Sequence for Changing/Reading the Data Word
    313
  - Virtual Flash Page Read Register
    314
  - Entering Programming Mode
    315
  - Leaving Programming Mode
    315
  - Electrical Characteristics
    318
  - Absolute Maximum Ratings
    318
  - DC Characteristics
    318
  - Speed Grades
    320
  - External Clock Drive Waveforms
    320
  - External Clock Drive
    320
  - External RC Oscillator, Typical Frequencies
    321
  - Two-Wire Serial Interface Characteristics
    322
  - Two-Wire Serial Bus Requirements
    322
  - SPI Timing Characteristics
    323
  - SPI Timing Parameters
    323
  - SPI Interface Timing Requirements (Master Mode)
    324
  - SPI Interface Timing Requirements (Slave Mode)
    324
  - ADC Characteristics
    325
  - ADC Characteristics, Differential Channels
    326
  - External Data Memory Timing
    328
  - Typical Characteristics
    333
  - Active Supply Current
    333
  - Active Supply Current Vs. Frequency
    334
  - Active Supply Current Vs. V
    334
  - Power-Down Supply Current
    340
  - Standby Supply Current
    342
  - Pin Pull-Up
    343
  - I/O Pin Pull-Up Resistor Current Vs. Input Voltage
    343
  - Pin Driver Strength
    344
  - I/O Pin Sink Current Vs. Output Voltage
    345
  - Pin Thresholds and Hysteresis
    346
  - BOD Thresholds and Analog Comparator Offset
    347
  - BOD Threshold Vs. Temperature
    348
  - Bandgap Voltage Vs. Operating Voltage
    348
  - Internal Oscillator Speed
    349
  - Watchdog Oscillator Frequency
    349
  - Calibrated 1 Mhz RC Oscillator Frequency Vs. Temperature
    349
  - Calibrated 2 Mhz RC Oscillator Frequency Vs. Temperature
    351
  - Calibrated 2 Mhz RC Oscillator Frequency Vs. V
    351
  - 2 Mhz RC Oscillator Frequency Vs. Osccal Value
    352
  - Calibrated 4 Mhz RC Oscillator Frequency Vs. Temperature
    352
  - Calibrated 4 Mhz RC Oscillator Frequency Vs. V
    353
  - 4 Mhz RC Oscillator Frequency Vs. Osccal Value
    353
  - Calibrated 8 Mhz RC Oscillator Frequency Vs. Temperature
    354
  - Calibrated 8 Mhz RC Oscillator Frequency Vs. V
    354
  - 8 Mhz RC Oscillator Frequency Vs. Osccal Value
    355
  - Brownout Detector Current Vs. V
    355
  - ADC Current Vs. AV
    356
  - Current Consumption in Reset and Reset
    358
  - Pulse Width
    358
  - Reset Pull-Up Resistor Current Vs. Reset Pin Voltage
    359
  - Register Summary
    362
  - Instruction Set Summary
    365
  - Packaging Information
    369
  - Errata
    371
  - Atmega128 Rev. F to M
    371
  - Stabilizing Time Needed When Changing OSCCAL Register
    372
  - IDCODE Masks Data from TDI Input
    372
  - Table of Contents
    379

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