Video Display Field 2 Vertical Blanking End Register (Vdvblke2) - Texas Instruments TMS320C64x DSP Reference Manual

4.12.8 Video Display Field 2 Vertical Blanking End Register (VDVBLKE2)

The video display field 2 vertical blanking end register (VDVBLKE2) controls
the end of vertical blanking in field 2. The VDVBLKE2 is shown in Figure 4–46
and described in Table 4–13.
In raw data mode, VBLNK is deasserted whenever the frame line counter
(FLCOUNT) is equal to VBLNKYSTOP2 and the frame pixel counter (FPCOUNT)
is equal to VBLNKXSTOP2 (this is shown in Figure 4–6, page 4-7).
In
FLCOUNT = VBLNKYSTOP2
VBLNK output control is completely independent of the timing control codes.
The V bit in the EAV/SAV codes for field 2 is controlled by the VDVBIT2 register.
Figure 4–46. Video Display Field 2 Vertical Blanking End Register (VDVBLKE2)
31 28 27
Reserved
R-0
15 12 11
Reserved
R-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
SPRU629
BT.656 and Y/C mode,
VBLNKYSTOP2
VBLNKXSTOP2
Video Display Registers
VBLNK is deasserted
and FPCOUNT = VBLNKXSTOP2.
R/W-0
R/W-0
Video Display Port
whenever
This
16
0
4-67