Capturing Video In Raw Data Mode - Texas Instruments TMS320C64x DSP Reference Manual

Capturing Video in Raw Data Mode

3.11 Capturing Video in Raw Data Mode
In order to capture video in the raw data mode, the following steps are needed:
1) Set VCxSTOP1 to specify size of an image to be captured (VCXSTOP sets
2) Write to VCxTHRLD to set the capture threshold. Every time the number
3) Configure a DMA channel to move data from YSRCx to a destination in
4) Write to the video port interrupt enable register (VPIE) to enable overrun
5) Write to VCxCTL to:
6) Capture starts when the ICAPEN signal is asserted and VCEN = 1. Data
7) If continuous capture is enabled, the video port begins capturing again on
3-46 Video Capture Port
the lower 12 bits and VCYSTOP sets the upper 12 bits of the captured
image size in pixels).
of received pixels reaches the number specified by the VCTHRLD1 bits,
a YEVTx is generated by the video capture module.
the DSP memory. The channel transfers should be triggered by the
YEVTx. The size of the transfers should be set to VCTHRLD1/4 for 8-bit
mode, VCTHRLD1/3 for dense 10-bit mode, VCTHRLD1/2 for 10-bit or
16-bit mode, or VCTHRLD1 for 20-bit mode. The DMA must start on a
doubleword boundary and move an even number of words.
(COVRx) and capture complete (CCMPx) interrupts, if desired.
-
Set capture mode (CMODE = x1x for raw data mode).
-
Choose capture operation (CON, FRAME bits).
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Set 10-bit pack mode (10BPK bits), if 10-bit operation is selected.
-
Enable raw data sync (RDS), if desired.
-
Set VCEN bit to enable capture.
is captured on every VCLKINx rising edge when CAPENx is active. DMA
events (YEVTx) are generated as triggered by VCxTHRLD1. When a
complete data block has been captured (DCOUNT = VCYSTOP and
VCXSTOP combined value), the FRMC bit in VCxSTAT is set causing the
CCMPx bit in VPIS to be set. This generates a DSP interrupt, if CCMPx
is enabled in VPIE.
the next VCLKIN rising edge when CAPEN is valid. If noncontinuous
capture is enabled, the next data block is captured during which the DSP
must clear the FRMC bit or further capture is disabled. If single frame
capture is enabled, capture is disabled until the DSP clears the FRMC bit
(at which point, raw data sync must again be performed if enabled).
SPRU629