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Table 2–8. Video Port Interrupt Enable Register (VPIE) Field Descriptions (Continued)
†
Bit
field
symval
10
STC
DISABLE
ENABLE
9–8
Reserved –
7
LFDA
DISABLE
ENABLE
6
SFDA
DISABLE
ENABLE
5
VINTA2
DISABLE
ENABLE
4
VINTA1
DISABLE
ENABLE
3
SERRA
DISABLE
ENABLE
2
CCMPA
DISABLE
ENABLE
1
COVRA
DISABLE
ENABLE
0
VIE
DISABLE
ENABLE
† For CSL implementation, use the notation VP_VPIE_field_symval
SPRU629
†
Value
Description
System time clock interrupt enable bit.
0
Interrupt is disabled.
1
Interrupt is enabled.
0
Reserved. The reserved bit location is always read as 0. A value
written to this field has no effect.
Long field detected on channel A interrupt enable bit.
0
Interrupt is disabled.
1
Interrupt is enabled.
Short field detected on channel A interrupt enable bit.
0
Interrupt is disabled.
1
Interrupt is enabled.
Channel A field 2 vertical interrupt enable bit.
0
Interrupt is disabled.
1
Interrupt is enabled.
Channel A field 1 vertical interrupt enable bit.
0
Interrupt is disabled.
1
Interrupt is enabled.
Channel A synchronization error interrupt enable bit.
0
Interrupt is disabled.
1
Interrupt is enabled.
Capture complete on channel A interrupt enable bit.
0
Interrupt is disabled.
1
Interrupt is enabled.
Capture overrun on channel A interrupt enable bit.
0
Interrupt is disabled.
1
Interrupt is enabled.
Video port global interrupt enable bit. Must be set for interrupt to be
sent to DSP.
0
Interrupt is disabled.
1
Interrupt is enabled.
Video Port Control Registers
Video Port
2-23
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