Display Dma Event Generation - Texas Instruments TMS320C64x DSP Reference Manual

Dsp video port/vcxo interpolated control (vic) port
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DMA Operation
Because the capture FIFOs may hold multiple thresholds worth of data, a
problem arises at the boundaries between fields. Since Field 1 and Field 2
may have different threshold values, the amount of data in the FIFO required
to generate the DMA event changes depending on the current capture field
and the field of any outstanding DMA requests. Similarly, the threshold value
loaded in the outgoing data counter needs to change depending on which
field's DMA event is being serviced (not which field is currently being
captured). To prevent confusion at the field boundaries, the VCxEVTCT regis-
ter is programmed to indicate the number of events to generate for each field.
An event counter tracks how many events have been generated and indicates
which threshold value to use in event generation and in the outgoing data
counter. After the last Field 1 event has been generated, the DMA logic looks
for FIFO > THRSHLD1 + THRSHLD2 to pregenerate the first Field 2 event.
Once the last Field 1 event
FIFO > 2
Some initial devices may require THRSHLD1 and THRSHLD2 to be set to the
same value. Check the latest device errata, if you want to use different thresh-
olds for the two fields.
2.3.2

Display DMA Event Generation

Display DMA events are generated based on the amount of room available in
the FIFO. The VDTHRLDn value indicates the level at which the FIFO has
room to receive another DMA. If the FIFO has at least VDTHRLDn locations
available, a DMA event is generated. Once a DMA event has been requested,
another DMA event may not be generated until the servicing of the first DMA
event has begun (as indicated by the first write to the FIFO by the DMA event
service). If there is at least 2 the threshold space still available in the FIFO
after the first DMA service is begun (and the display event counter has not
expired) then another DMA event may be generated. Thus, up to one DMA
request may be outstanding.
An incoming data counter is loaded with the VDTHRLDn (or VDTHRLDn/2 for
Cb and Cr FIFOs) value at the beginning of each DMA event service and
counts down the incoming DMA doublewords When the counter reaches 0, the
DMA event is complete. Figure 2–2 shows the display DMA event generation.
2-8
Video Port
THRSHLD2 (assuming a Field 2 event is outstanding).
completes,
the
logic
looks
for
SPRU629

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