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Displaying Video in Raw Data Mode
11) Set the horizontal synchronization in VDHSYNC. Specify the frame pixel
12) Set the video display field 1 timing. Specify the first line and pixel of field 1
13) Set the video display field 2 timing. Specify the first line and pixel of field 2
14) Configure a DMA to move data from table in the DSP memory to YDSTA
15) Set DISPEVT1 and DISPEVT2 bits in VDDISPEVT. Event count is total
16) Write to VPIE to enable underrun (DUND) and display complete (DCMP)
17) Write to VDTHRLD to set the display FIFO threshold (VDTHRLD bits) and
18) Write to VDCTL to:
19) Wait for 2 or more frame times, to allow the display counters and control
20) Write to VDCTL to clear the BLKDIS bit.
21) Display is enabled at the start of the first frame after BLKDIS = 0 and
4-50
Video Display Port
counter value for a pixel where HSYNC gets asserted (HSYNCYSTART)
and width of the HSYNC pulse (HSYNCSTOP) in frame pixel clocks.
in VDFLDT1.
in VDFLDT2.
(memory-mapped display FIFO). The transfers should be triggered by the
YEVT.
doublewords per field divided by total doublewords per Y DMA.
interrupts, if desired.
the FPCOUNT increment rate (INCPIX bit).
-
Set display mode (DMODE =01x for 8/10-bit output, 11x for 16/20 bit
output).
-
Set desired field/frame operation (CON, FRAME, DF1, DF2 bits).
-
Select control outputs (VCTL1S, VCTL2S, VCTL3S bits) or external
sync inputs (HXS, VXS, FXS bits).
-
Select 10-bit unpacking mode (DPK bit), if appropriate.
-
Set VDEN bit to enable the display.
signals to become properly synchronized
begins with the first selected field. DMA events are generated as triggered
by VDTHRLD and the DEVTCT counter. When a selected field has been
displayed (FLCOUNT = FRMHEIGHT and FPCOUNT = FRMWIDTH),
the appropriate F1D, F2D, or FRMD bits are set and cause the DCMP bit
in VPIS to be set. This generates a DSP interrupt, if the DCMP bit is
enabled in VPIE.
SPRU629
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