Tsi Clock Initialization Msb Register (Tsiclkinitm); Tsi Clock Initialization Msb Register (Tsiclkinitm) Field Descriptions - Texas Instruments TMS320C64x DSP Reference Manual

3.13.13 TSI Clock Initialization MSB Register (TSICLKINITM)

The transport stream interface clock initialization MSB register (TSICLKINITM)
is used to initialize the hardware counter to synchronize with the system time
clock. TSICLKINITM is shown in Figure 3–41 and described in Table 3–26.
On receiving the first packet containing a program clock reference (PCR)
header, the DSP writes the most-significant bit (MSB) of the PCR and the 9-bit
PCR extension into TSICLKINITM. This initializes the counter to the system
time clock. TSICLKINITM should also be updated by the DSP whenever a
discontinuity in the PCR field is detected.
To ensure synchronization and prevent false compare detection, the software
should disable the system time clock interrupt (clear the STEN bit in TSICTL)
prior to writing to TSICLKINITM. All bits of the system time counter are initial-
ized whenever either TSICLKINITL or TSICLKINITM are written.
Figure 3–41. TSI Clock Initialization MSB Register (TSICLKINITM)
31
15
Reserved
R-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 3–26. TSI Clock Initialization MSB Register (TSICLKINITM) Field Descriptions
†
Bit field symval
31–10 Reserved –
9–1 INPCRE OF(value)
0 INPCRM OF(value)
† For CSL implementation, use the notation VP_TSICLKINITM_field_symval
SPRU629
Reserved
R-0
10 9
BT.656, Y/C Mode,
†
Value
or Raw Data Mode
0 Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
0–1FFh Not used.
0–1 Not used.
Video Capture Registers
INPCRE
R/W-0
Description
TSI Mode
Initializes the extension portion of the
system time clock.
Initializes the MSB of the system time
clock.
Video Capture Port
16
1 0
INPCRM
R/W-0
3-75