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Texas Instruments TMS320C6000 DSP Reference Manual

Texas Instruments TMS320C6000 DSP Reference Manual

External memory interface (emif)
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TMS320C6000 DSP
External Memory Interface (EMIF)
Reference Guide
Literature Number: SPRU266A
September 2003

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Summary of Contents for Texas Instruments TMS320C6000 DSP

  • Page 1 TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide Literature Number: SPRU266A September 2003...
  • Page 2 TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions:...

  • Page 3: Read This First

    TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the TMS320C6000 CPU architecture, instruction set, pipeline, and interrupts for these digital signal processors. TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190) describes the peripherals available on the TMS320C6000 DSPs.
  • Page 4 Trademarks Related Documentation From Texas Instruments / Trademarks TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the TMS320C62x and TMS320C67x DSPs, develop- ment tools, and third-party support. TMS320C64x Technical Overview (SPRU395) gives an introduction to the TMS320C64x DSP and discusses the application areas that are enhanced by the TMS320C64x VelociTI.

  • Page 5: Table Of Contents

    ............... Provides an overview and describes the common operation of the external memory interface (EMIF) in the digital signal processors (DSPs) of the TMS320C6000 DSP family. Overview .
  • Page 6 Contents SDRAM Interface ............2.4.1 C620x/C670x Bootmode .
  • Page 7 Contents TMS320C64x EMIF ............. . Describes the operation and registers of the EMIF in the TMS320C64x DSP.
  • Page 8 Figures Figures 1−1 SDRAM Refresh Timing Diagram ..........1−2 TMS320C6000 SDRAM Deactivate All Banks (DCAB) Command Timing Diagram .
  • Page 9 Figures 3−4 TMS320C621x/C671x EMIF to 16-bit SRAM (Big Endian) Block Diagram ... . . 3−5 EMIF to 16M-Bit SDRAM Interface Block Diagram ....... . 3−6 Logical Address-to-Page Register Mapping for 32-Bit Logical Address .
  • Page 10 Figures 4−30 PDT Read Transaction (CAS Latency is 3) Timing Diagram ..... . . 4-48 4−31 Case D: Glueless PDT Read Interface to Synchronous FIFO Block Diagram .
  • Page 11 Tables Tables 1−1 Differences Between the C62x/C67x and C64x EMIF ......1−2 TMS320C6000 EMIF SDRAM Commands .
  • Page 12 Tables 3−10 EMIF Registers for C621x/C671x DSP ......... 3-25 3−11 EMIF Global Control Register (GBLCTL) Field Descriptions...

  • Page 13: Overview

    Chapter 1 Overview This chapter provides an overview and describes the common operation of the external memory interface (EMIF) in the digital signal processors (DSPs) of the TMS320C6000 DSP family. For operation and registers unique in the TMS320C620x/C670x EMIF, see Chapter 2. For operation and registers unique in the TMS320C621x/C671x EMIF, see Chapter 3.

  • Page 14: Differences Between The C62X/C67X And C64X Emif

    Overview 1.1 Overview The external memory interfaces (EMIFs) of all C6000 devices support a glueless interface to a variety of external devices, including: Pipelined synchronous-burst SRAM (SBSRAM) Synchronous DRAM (SDRAM) Asynchronous devices, including SRAM, ROM, and FIFOs An external shared-memory device Table 1−1 summarizes the differences between the C6000 EMIFs.

  • Page 15: 1.2 Command-To-Command Turnaround Time

    Command-to-Command Turnaround Time Overview / Command-to-Command Turnaround Time Table 1−1. Differences Between the C62x/C67x and C64x EMIF (Continued) C62x/C67x EMIF C64x EMIF ‡ EMIFA EMIFB C6416/15/14/12, C6411, Other Other DM642 DM640/641 C6416/15/14 † † C620x/C670x C620x/C670x Feature Feature Feature C6201/C6701 C6201/C6701 C621x/C671x C621x/C671x...

  • Page 16: Tms320C6000 Emif Sdram Commands

    SDRAM Interface 1.3 SDRAM Interface The C6000 EMIF supports the SDRAM commands shown in Table 1−2. Table 1−3 shows the signal truth table for the SDRAM commands. The 16-bit EMIF, 32-bit EMIF, and 64-bit EMIF table entries refer to the total bus width of the EMIF and not the size of the transfer.

  • Page 17: Truth Table For Sdram Commands

    SDRAM Interface Table 1−3. Truth Table for SDRAM Commands SDRAM: A[19:16] A[15:11] A[9:0] 16-bit SDCKE SDRAS SDCAS SDWE EA[20:17] ‡ EA[16:12] EA11 EA[10:1] EMIF: † 32-bit † SDCKE § SDRAS SDCAS SDWE EA[21:18] ¶ EA[17:13] EA12 EA[11:2] EMIF: 64-bit SDCKE SDRAS SDCAS SDWE...

  • Page 18: Tms320C6000 Sdram Signal Descriptions

    SDRAM Interface Table 1−4. TMS320C6000 SDRAM Signal Descriptions SDRAM EMIF Signal SDRAM Function Signal DQMx Data/output mask. DQM is an input/output buffer control signal. When high, it disables writes and places outputs in the high impedance state during reads. DQM has a 2-CLK-cycle latency on reads and a 0-CLK-cycle latency on writes. DQM pins serve as byte strobes and are connected to BE outputs.

  • Page 19: Tms320C6000 Sdram Interface Summary

    SDRAM Interface Table 1−5. TMS320C6000 SDRAM Interface Summary C62x/C67x EMIF C64x EMIF EMIFA EMIFB C6416/15/14/12, C6411, Other DM642 DM640/641 † C6416/15/14 ‡ C620x/C670x Feature C6201/C6701 C621x/C671x Interface width 32-bit 32-bit 32-, 16-, 8-bit 64-, 32-, 16-, 32-, 16-, 8-bit 16-, 8-bit 8-bit SDRAM clock SDCLK...

  • Page 20: Sdram Interface

    SDRAM Interface 1.3.1 SDRAM Initialization After reset, none of the CE spaces are configured as SDRAM. The CPU should initialize all of the CE space control registers and the SDRAM extension register before performing SDRAM initialization by setting the INIT bit to 1. If SDRAM does not exist in the system, you should not write a 1 to the INIT bit.

  • Page 21: Sdram Refresh Mode

    SDRAM Interface 1.3.3 SDRAM Refresh Mode The RFEN bit in the SDRAM control register (SDCTL) selects the SDRAM refresh mode of the EMIF. When RFEN = 0, all EMIF refreshes are disabled, and you must ensure that refreshes are implemented in an external device. When RFEN = 1, the EMIF performs refreshes of SDRAM.

  • Page 22: Tms320C6000 Sdram Deactivate All Banks (Dcab) Command Timing Diagram

    SDRAM Interface 1.3.4 SDRAM Deactivation (DCAB and DEAC) The SDRAM deactivation (DCAB) is performed after a hardware reset or when INIT = 1 in the SDRAM control register (SDCTL). The SDRAMs also require this cycle prior to a refresh (REFR) and mode set register (MRS) command. On the C6000 EMIF, a DCAB is issued when a page boundary is crossed.

  • Page 23: Tms320C621X/C671X And Tms320C64X Sdram Deactivate Single Bank (Deac)

    SDRAM Interface Figure 1−3. TMS320C621x/C671x and TMS320C64x SDRAM Deactivate Single Bank (DEAC) Command Timing Diagram DEAC † Clock BE[3:0] EA[21:13] Bank ‡ EA12 EA[11:2] ED[31:0] SDRAS SDCAS SDWE † Clock = ECLKOUT for C621x/C671x DSP. = ECLKOUT1 for C64x DSP. ‡...

  • Page 24: Tms320C6000 Sdram Activate (Actv) Command Before An Sdram Write Timing Diagram

    SDRAM Interface 1.3.5 SDRAM Activation (ACTV) The C6000 EMIF automatically issues the activate (ACTV) command before a read or write to a new row of SDRAM. The ACTV command opens up a page of memory, allowing future accesses (reads or writes) with minimum latency. When the EMIF issues an ACTV command, a delay of t is incurred before a read or write command is issued.

  • Page 25: Tms320C6000 Sbsram Operating Speeds

    SBSRAM Interface 1.4 SBSRAM Interface The C6000 EMIF interfaces directly to industry-standard synchronous burst SRAMs (SBSRAMs). This memory interface allows a high-speed memory interface without some of the limitations of SDRAM. Most notably, since SBSRAMs are SRAM devices, random accesses in the same direction can occur in a single cycle.

  • Page 26: Tms320C6000 Sbsram Signal Descriptions

    SBSRAM Interface Table 1−7. TMS320C6000 SBSRAM Signal Descriptions EMIF Signal † SBSRAM Signal SBSRAM Function SSADS ADSC Address strobe SSOE Output enable SSWE Write enable SSCLK/CLKOUT2/ECLKOUT ‡ SBSRAM clock † For C64x DSP, SBSRAM control signals are renamed as SADS/SRE, SOE, and SWE, respectively.

  • Page 27: Emif To 32-Bit Sram Interface Block Diagram

    Asynchronous Interface 1.5 Asynchronous Interface The asynchronous interface offers configurable memory cycle types to interface to a variety of memory and peripheral types, including SRAM, EPROM, and flash memory, as well as FPGA and ASIC designs. Table 1−9 lists the asynchronous interface pins.

  • Page 28: Emif To 8-Bit Rom Interface Block Diagram

    Asynchronous Interface Figure 1−6. EMIF to 8-Bit ROM Interface Block Diagram EMIF † EA[N + 2:2] A[N:0] ED[7:0] D[7:0] ARDY † For C64x EMIFA, EA[N + 3:3] is used; for EMIFB, EA[N + 1:1] is used. Figure 1−7. EMIF to 16-Bit ROM Interface Block Diagram EMIF †...

  • Page 29: Tms320C6000 Asram Interface Summary

    Asynchronous Interface Table 1−10. TMS320C6000 ASRAM Interface Summary C62x/C67x EMIF C64x EMIF EMIFA EMIFB C6416/15/14/12, DM642 C6411, DM640/641 C6416/15/14 † Feature C620x/C670x C621x/C671x Interface width 32-bit ASRAM; 32-, 16-, 8-bit 64-, 32-, 16-, 8-bit 32-, 16-, 8-bit 16-, 8-bit × ×...

  • Page 30: Programmable Asram Parameters

    Asynchronous Interface 1.5.1 Programmable ASRAM Parameters The C6000 EMIF allows a high degree of programmability for shaping asynch- ronous accesses. The programmable parameters are: Setup: The time between the beginning of a memory cycle (CE low, address valid) and the activation of the read or write strobe. Strobe: The time between the activation and deactivation of the read (ARE) or write strobe (AWE).

  • Page 31: Asynchronous Reads

    Asynchronous Interface 1.5.2 Asynchronous Reads Figure 1−9 shows an asynchronous read with the setup, strobe, and hold param- eter programmed with the values 2, 3, and 1, respectively. An asynchronous read proceeds as: At the beginning of the setup period: CE becomes active.

  • Page 32: Asynchronous Read Timing Diagram

    Asynchronous Interface Figure 1−9. Asynchronous Read Timing Diagram Setup Strobe Hold CE Hold † Clock ‡ § BE[3:0] Address EA[21:2] Read D ED[31:0] ARDY † Clock = CLKOUT1 for C620x/C670x DSP. = ECLKOUT for C621x/C671x DSP. = ECLKOUT1 for C64x DSP. ‡...

  • Page 33: Asynchronous Writes

    Asynchronous Interface 1.5.3 Asynchronous Writes Figure 1−10 shows two back-to-back asynchronous write cycles with the ARDY signal pulled high (always ready). The SETUP, STROBE, and HOLD are programmed to 2, 3, and 1, respectively. At the beginning of the setup period: CE becomes active.

  • Page 34: Asynchronous Write Timing Diagram

    Asynchronous Interface Figure 1−10. Asynchronous Write Timing Diagram Setup Hold Strobe Hold CE write hold Strobe Setup † Clock ‡ § BE[3:0] EA[21:2] Á Á Á Á ¶ ED[31:0] Á Á Á Á ARDY † Clock = CLKOUT1 for C620x/C670x DSP. = ECLKOUT for C621x/C671x DSP.
  • Page 35 Asynchronous Interface 1.5.3.1 C621x/C671x Asynchronous Writes Setup Timing For a C621x/C671x asynchronous write cycle, the address (EA) and strobe (CE and BE) signals have setup time of WRSETUP cycles as programmed in the EMIF CE space control register (CECTL). However, the data lines (ED) may become valid one cycle later than the address (EA) and strobe (CE and BE) signals.

  • Page 36: Tms320C620X/C670X Emif Ready Operation Timing Diagram

    Asynchronous Interface 1.5.4 Ready Input In addition to programmable access shaping, you can insert extra cycles into the strobe period by deactivating the ARDY input. The ready input is internally synchronized to the CPU clock (C620x/C670x EMIF), ECLKOUT (C621x/C671x EMIF), or ECLKOUT1 (C64x EMIF). This synchronization allows an asynchronous ARDY input while avoiding metastablility.

  • Page 37: Tms320C621X/C671X Emif Ready Operation Timing Diagram

    Asynchronous Interface 1.5.4.2 C621x/C671x EMIF If ARDY is low on the first rising edge of ECLKOUT before the end of the programmed strobe period (Figure 1−12), then the strobe period is extended by one ECLKOUT cycle. For each subsequent ECLKOUT rising edge that ARDY is sampled low, the strobe period is extended by one ECLKOUT cycle.

  • Page 38: Tms320C64X Emif Ready Operation Timing Diagram

    Asynchronous Interface 1.5.4.3 C64x EMIF If ARDY is low on the second rising edge of ECLKOUT before the end of the programmed strobe period (Figure 1−13), then the strobe period is extended by one ECLKOUT cycle. For each subsequent ECLKOUT rising edge that ARDY is sampled low, the strobe period is extended by one ECLKOUT cycle.

  • Page 39: 1.6 Resetting The Emif

    Resetting the EMIF 1.6 Resetting the EMIF A hardware reset using the RESET pin on the device forces all register values to their reset state. During reset, all outputs are driven to their inactive levels, with the exception of the clock outputs (SDCLK, SSCLK, CLKOUT1, and CLKOUT2).

  • Page 40: 1.7 Hold Interface

    Hold Interface 1.7 Hold Interface The EMIF responds to hold requests for the external bus. The hold handshake allows an external device and the EMIF to share the external bus. The hand- shake mechanism uses: HOLD: hold request input. HOLD synchronizes internally to the CPU clock.

  • Page 41: Tms320C62X/C67X Emif Reset Considerations With The Hold Interface

    Hold Interface Note: There is no mechanism to ensure that the external device does not attempt to drive the bus indefinitely. You should be aware of system-level issues, such as refresh, that you may need to perform. During host requests, the refresh counters within the EMIF continue to log refresh requests;...

  • Page 42: 1.8 Boundary Conditions When Accessing Emif Registers

    Boundary Conditions When Accessing EMIF Registers 1.8 Boundary Conditions When Accessing EMIF Registers The C6000 EMIF has internal registers that change memory type, asynchronous memory timing, SDRAM refresh, SDRAM initialization (MRS COMMAND), clock speed, arbitration type, HOLD/NOHOLD condition, etc. The following actions can cause improper data reads or writes: Writing to the CE0, CE1, CE2, or CE3 space control registers while an external access to that CE space is active.

  • Page 43: Emif Output Clock (Eclkoutn) Operation

    Clock Output Enabling Clock Output Enabling 1.9 Clock Output Enabling To reduce electromagnetic interference (EMI) radiation, the C62x/C67x EMIF allows the disabling (holding high) of CLKOUT2, CLKOUT1 (all C62x/C67x devices, except C6713 DSP), SSCLK, and SDCLK. This disabling is performed by clearing the CLK2EN, CLK1EN, SSCEN, and SDCEN bits to 0 in the EMIF global control register (GBLCTL).

  • Page 44: Tms320C64X Emif Clock Block Diagram

    Emulation Halt Operation Clock Output Enabling / Emulation Halt Operation / Power Down Figure 1−14. TMS320C64x EMIF Clock Block Diagram EK1EN EK1HZ HOLD Reset Controller CPU/6 EMIF input clock CPU/4 ECLKIN ECLKIN_SEL EK2RATE EK2EN EK2HZ HOLD 1.10 Emulation Halt Operation The EMIF continues operating during emulation halts.

  • Page 45: Topic Page

    Chapter 2 TMS320C620x/C670x EMIF This chapter describes the operation and registers of the EMIF in the TMS320C620x/C670x DSP. For operation and registers unique to the TMS320C621x/C671x EMIF, see Chapter 3. For operation and registers unique to the TMS320C64x EMIF, see Chapter 4. Topic Page Overview...

  • Page 46: Tms320C620X/C670X Dsp Block Diagram

    Overview 2.1 Overview The C620x/C670x EMIF services requests of the external bus from four requestors: On-chip program memory controller that services CPU program fetches On-chip data memory controller that services CPU data fetches On-chip direct-memory access (DMA) controller External shared-memory device controller (using EMIF arbitration signals) If multiple requests arrive simultaneously, the EMIF prioritizes them and performs the necessary number of operations.

  • Page 47: Tms320C6201/C6701 Emif Interface Signals

    EMIF Interface Signals 2.2 EMIF Interface Signals following describes EMIF interface signals C620x/C670x devices. 2.2.1 C6201/C6701 EMIF The EMIF signals of the C6201/C6701 DSP are shown in Figure 2−2 and described in Table 2−1. The C6201/C6701 devices provide separate clock and control signals for the SBSRAM and SDRAM interface.

  • Page 48: Tms320C6202/C6203/C6204/C6205 Emif Interface Signals

    EMIF Interface Signals 2.2.2 C6202(B)/C6203(B)/C6204/C6205 EMIF The EMIF signals of the C6202/C6203/C6204/C6205 DSP are shown in Figure 2−3 and described in Table 2−1. These C620x devices have combined the SDRAM and SBSRAM signals. Only one of these two memory types can be used in a system.

  • Page 49: Tms320C620X/C670X Emif Interface Signal Descriptions

    EMIF Interface Signals Table 2−1. TMS320C620x/C670x EMIF Interface Signal Descriptions I/O/Z Description CLKOUT1 Clock output. Runs at the CPU clock rate. CLKOUT2 Clock output. Runs at 1/2 the CPU clock rate. Used for synchronous memory interface on all C620x/C670x devices, except C6201/C6701 DSP. ED[31:0] I/O/Z EMIF 32-bit data bus I/O.

  • Page 50: Addressable Memory Ranges

    Memory Width and Byte Alignment Memory Width and Byte Alignment / SDRAM Interface 2.3 Memory Width and Byte Alignment The C620x/C670x EMIF supports 32-bit-wide ASRAM, SDRAM, and SBSRAM interface in both big-endian and little-endian modes. CE1 space supports ×16 and ×8 read-only memory (ROM) interfaces. The packing format in ROM is always little-endian, regardless of the value of the LENDIAN config- uration bit.

  • Page 51: Emif To 16M-Bit Sdram Interface Block Diagram

    SDRAM Interface C620x/C670x EMIF, not all the memory space is accessible. Table 2−4 provides examples of possible SDRAM interface to larger memories where only part of the larger memories is accessible. Figure 2−4. EMIF to 16M-Bit SDRAM Interface Block Diagram 16M-bit EMIF SDRAM...

  • Page 52: Tms320C620X/C670X Dsp Compatible Sdram

    SDRAM Interface Table 2−3. TMS320C620x/C670x DSP Compatible SDRAM Address- able SDRAM Space Column Bank Pre- Devices/ Size (MBytes) Address Address Select charge 16M bit ×8 SDRAM A8−A0 A10−A0 EMIF EA10−EA2 SDA10, EA13 SDA10 EA11−EA2 ×16 512K SDRAM A7−A0 A10−A0 EMIF EA9−EA2 SDA10, EA13...

  • Page 53: Example C620X/C670X Sdram Interface With Unused Sdram Address Pins

    SDRAM Interface Table 2−4. Example C620x/C670x SDRAM Interface with Unused SDRAM Address Pins Address- able SDRAM Space Column Bank Pre- Devices/ Size (MBytes) Address Address Select charge 128M bit ×16 16M (1) SDRAM A8−A0 A11−A0 (2) BA1−BA0 EMIF EA10−EA2 SDA10, EA14−EA13 SDA10 EA11−EA2...

  • Page 54: Monitoring Page Boundaries

    SDRAM Interface 2.4.2 Monitoring Page Boundaries The C620x/C670x EMIF storage and comparison is performed independently for each CE space. The C620x/C670x EMIF has 4 internal page registers. Each page register corresponds to a single CE space. If a given CE space is configured for SDRAM operation (by the MTYPE field in CECTL), the corre- sponding page register is used for accesses to that CE space.

  • Page 55: Byte Address-To-Ea Mapping For Sdram Ras And Cas

    SDRAM Interface 2.4.3 Address Shift The same EMIF pins determine the row and column address, thus the C620x/C670x EMIF interface appropriately shifts the address in row and column address selection. Table 2−5 shows the translation between bits of the byte address and how they appear on the EA pins for row and column addresses on the C620x/C670x DSP.

  • Page 56: Sdram Refresh Mode

    SDRAM Interface 2.4.4 SDRAM Refresh Mode The RFEN bit in the SDRAM control register (SDCTL) enables the SDRAM refresh mode of the C620x/C670x EMIF. When RFEN = 0, all EMIF refreshes are disabled, and you must ensure that refreshes are implemented in an external device.

  • Page 57: Mode Register Value

    SDRAM Interface 2.4.5 Mode Register Set (MRS) The C620x/C670x EMIF automatically performs a deactivate (DCAB) command followed by a mode register set (MRS) command whenever the INIT field in the SDRAM control register (SDCTL) is set. INIT can be set by device reset or by a write.

  • Page 58: Sdram Mode Register Set: Mrs Command Timing Diagram

    SDRAM Interface Figure 2−8. SDRAM Mode Register Set: MRS Command Timing Diagram † Clock BE[3:0] EA[15:2] MRS value SDA10 SDRAS SDCAS SDWE † Clock = SDCLK for C6201/C6701 DSP. = CLKOUT2 for all C620x/C670x DSP, except C6201/C6701 DSP. 2.4.6 Timing Requirements Several SDRAM timing parameters decouple the EMIF from SDRAM speed limitations.

  • Page 59: Sdram Read

    SDRAM Interface 2.4.7 SDRAM Read During an SDRAM read, the selected bank is activated with the row address during the ACTV command. Figure 2−9 shows the timing for the C620x/C670x EMIF issuing three read commands performed at three different column addresses. The EMIF uses a CAS latency of three and a burst length of one.

  • Page 60: Sdram Write

    SDRAM Interface 2.4.8 SDRAM Write All SDRAM writes have a burst length of one on the C620x/C670x EMIF. The bank is activated with the row address during the ACTV command. There is no latency on writes, so data is output on the same cycle as the column address. Writes to particular bytes are disabled using the appropriate DQM inputs;...

  • Page 61: 2.5 Sbsram Interface

    SBSRAM Interface 2.5 SBSRAM Interface The SBSRAM interface on the C620x/C670x EMIF is shown in Figure 2−11. For the C620x/C670x EMIF, the ADV signal of the SBSRAM is pulled high. This disables the internal burst advance counter of the SBSRAM. This inter- face allows bursting by strobing a new address into the SBSRAM on every cycle.

  • Page 62: Sbsram Four-Word Read Timing Diagram

    SBSRAM Interface 2.5.1 SBSRAM Read Figure 2−12 shows a four-word read of an SBSRAM. Every access strobes a new address into the SBSRAM, indicated by the SSADS strobe low. The first access requires an initial start-up penalty of two cycles; thereafter, all accesses occur in a single EMIF clock cycle.

  • Page 63: Sbsram Interface

    SBSRAM Interface 2.5.2 SBSRAM Write Figure 2−13 shows a four-word write to an SBSRAM. Every access strobes a new address into the SBSRAM. The first access requires an initial start-up penalty of two cycles; thereafter, all accesses can occur in a single EMIF clock cycle.

  • Page 64: Byte Address To Ea Mapping For Asynchronous Memory Widths

    ROM Access Modes 2.6 ROM Access Modes The C620x/C670x EMIF supports 8-bit-wide and 16-bit-wide ROM access modes that are selected by the MTYPE field in the CE space control register (CECTL). In reading data from these narrow memory spaces, the EMIF packs multiple reads into one 32-bit-wide value.

  • Page 65: Bit Rom Mode

    ROM Access Modes 2.6.1 8-Bit ROM Mode In 8-bit ROM mode, the address is left-shifted by 2 bits to create a byte address on EA to access byte-wide ROM. The EMIF always packs four consecutive bytes aligned on a 4-byte boundary (byte address = 4N) into a word access, regardless of the access size.

  • Page 66: 2.7 Memory Request Priority

    Memory Request Priority 2.7 Memory Request Priority The C620x/C670x EMIF has multiple requestors competing for the interface. Table 2−9 summarizes the priority scheme that the EMIF uses in the case of multiple pending requests. The priority scheme may change if the DMA channel that issues a request through the DMA controller is of high priority.

  • Page 67: Emif Registers

    EMIF Registers 2.8 EMIF Registers Control of the EMIF and the memory interfaces it supports is maintained through memory-mapped registers within the EMIF. Access to these registers requires the EMIF clock. Table 2−10 lists the memory-mapped registers and their memory addresses in the C620x/C670x DSP. Table 2−10.

  • Page 68: Emif Global Control Register (Gblctl) (C6201/C6701 Dsp)

    EMIF Registers Figure 2−14. EMIF Global Control Register (GBLCTL) (C6201/C6701 DSP) Reserved R/W-0 Reserved † Reserved ARDY HOLD HOLDA R/W-0 R/W-0 R/W-1 R/W-1 NOHOLD SDCEN SSCEN CLK1EN CLK2EN SSCRT RBTR8 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 † The reserved bit fields should always be written with their default values when modifying the GBLCTL. Writing a value other than the default value to these fields may cause improper operation.

  • Page 69: Emif Global Control Register (Gblctl) Field Descriptions

    EMIF Registers Table 2−11. EMIF Global Control Register (GBLCTL) Field Descriptions † † Value Description field symval 31−11 Reserved − Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. ARDY ARDY input bit.

  • Page 70: Emif Global Control Register (Gblctl) Field Descriptions

    EMIF Registers Table 2−11. EMIF Global Control Register (GBLCTL) Field Descriptions (Continued) † † Value Description field symval CLK1EN CLKOUT1 enable bit. DISABLE CLKOUT1 is held high. ENABLE CLKOUT1 is enabled to clock. CLK2EN For C6201/C6701 DSP: CLKOUT2 is enabled/disabled using SSCEN/SDCEN bits.

  • Page 71: Emif Ce Space Control Register (Cectl)

    EMIF Registers 2.8.2 EMIF CE Space Control Registers (CECTL0−3) The CE space control register (CECTL) is shown in Figure 2−16 and described in Table 2−12. These registers correspond to the CE memory spaces supported by the EMIF. There are four CE space control registers corresponding to the four external CE signals.

  • Page 72: Emif Ce Space Control Register (Cectl) Field Descriptions

    EMIF Registers Table 2−12. EMIF CE Space Control Register (CECTL) Field Descriptions † † Value Description field symval 31−28 WRSETUP OF(value) 0−Fh Write setup width. Number of clock cycles ‡ of setup time for address (EA), chip enable (CE), and byte enables (BE) before write strobe falls.

  • Page 73: Emif Sdram Control Register (Sdctl)

    EMIF Registers 2.8.3 EMIF SDRAM Control Register (SDCTL) The SDRAM control register (SDCTL) controls SDRAM parameters for all CE spaces that specify an SDRAM memory type in the MTYPE field of the associated CE space control register (CECTL). Because SDCTL controls all SDRAM spaces, each space must contain SDRAM with the same refresh, timing, and page characteristics.

  • Page 74: Emif Sdram Control Register (Sdctl) Field Descriptions

    EMIF Registers Table 2−13. EMIF SDRAM Control Register (SDCTL) Field Descriptions † † Value Description field symval 31−27 Reserved − Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. SDWID SDRAM column width select.

  • Page 75: Emif Sdram Timing Register (Sdtim)

    EMIF Registers 2.8.4 EMIF SDRAM Timing Register (SDTIM) The SDRAM timing register (SDTIM) controls the refresh period in terms of EMIF clock cycles. The SDTIM is shown in Figure 2−18 and described in Table 2−14. Optionally, the PERIOD field can send an interrupt to the CPU. Thus, this counter can be used as a general-purpose timer if SDRAM is not used by the system.

  • Page 76: Tms320C621X/C671X Emif

    Chapter 3 TMS320C621x/C671x EMIF This chapter describes the operation and registers of the EMIF in the TMS320C621x/C671x DSP. For operation and registers unique to the TMS320C620x/C670x EMIF, see Chapter 2. For operation and registers unique to the TMS320C64x EMIF, see Chapter 4. Topic Page Overview...

  • Page 77: Tms320C621X/C671X Dsp Block Diagram

    Overview 3.1 Overview The C621x/C671x EMIF services requests of the external bus from two requestors: On-chip enhanced direct-memory access (EDMA) controller External shared-memory device controller A block diagram of the C621x/C671x DSP is shown in Figure 3−1. Figure 3−1. TMS320C621x/C671x DSP Block Diagram EMIF L1P Cache C6000 DSP core...

  • Page 78: Emif Interface Signals

    EMIF Interface Signals 3.2 EMIF Interface Signals The EMIF signals of the C621x/C671x DSP are shown in Figure 3−2 and described in Table 3−1. The C621x/C671x EMIF has the following features: All of the memories interfacing with the C621x/C671x EMIF should oper- ate off of ECLKOUT (EMIF clock output).

  • Page 79: Tms320C621X/C671X Emif Interface Signals

    EMIF Interface Signals Figure 3−2. TMS320C621x/C671x EMIF Interface Signals EMIF ECLKIN ECLKOUT † ED[31:0] EA[21:2] Shared by all external interfaces CE[3:0] BE[3:0] Enhanced data memory ARDY controller AOE/SDRAS/SSOE MUXed Async/SDRAM/SBSRAM ARE/SDCAS/SSADS control AWE/SDWE/SSWE HOLD HOLDA BUSREQ Control registers Internal peripheral bus †...

  • Page 80: Tms320C621X/C671X Emif Interface Signal Descriptions

    EMIF Interface Signals Table 3−1. TMS320C621x/C671x EMIF Interface Signal Descriptions I/O/Z Description CLKOUT1 Clock output. Runs at the CPU clock rate. CLKOUT2 Clock output. Runs at 1/2 the CPU clock rate. ECLKIN EMIF clock input. Must be provided by the system on C621x/C671x DSP. ECLKOUT EMIF clock output.

  • Page 81: Addressable Memory Ranges

    Memory Width and Byte Alignment 3.3 Memory Width and Byte Alignment The C621x/C671x EMIF supports memory widths of 8 bits, 16 bits, and 32 bits, including reads and writes of both big- and little-endian devices. The C6712 EMIF supports memory widths of 8 bits and 16 bits only. There is no distinction between ROM and asynchronous interface.

  • Page 82: Byte Alignment By Endianness

    Memory Width and Byte Alignment Figure 3−3. Byte Alignment by Endianness (a) 32-bit bus TMS320C621x/C671x DSP † ED[31:24] ED[23:16] ED[15:8] ED[7:0] 32-bit device 16-bit device big endian 16-bit device little endian 8-bit 8-bit device device big endian little endian (b) 16-bit bus †...

  • Page 83: Tms320C621X/C671X Emif To 16-Bit Sram (Big Endian) Block Diagram

    Memory Width and Byte Alignment Figure 3−4. TMS320C621x/C671x EMIF to 16-bit SRAM (Big Endian) Block Diagram † External clock EMIF SRAM ECLKIN EA[N + 2:2] A[N:0] ED[31:16] † D[15:0] BE[3:2] B[1:0] ARDY † Does not apply to C6712/C6712C DSP, because ED[31:16] do not exist on C6712/C6712C DSP. TMS320C621x/C671x EMIF SPRU266A...

  • Page 84: Emif To 16M-Bit Sdram Interface Block Diagram

    SDRAM Interface 3.4 SDRAM Interface The C621x/C671x EMIF supports SDRAM commands shown in Table 1−2 and Table 1−3 shows the signal truth table for the SDRAM commands. Table 1−4 summarizes the pin connection and related signals specific to SDRAM operation. Table 1−5 summarizes the similarities and differences on the C6000 SDRAM interface.

  • Page 85: Tms320C621X/C671X Dsp Compatible Sdram

    SDRAM Interface Table 3−3. TMS320C621x/C671x DSP Compatible SDRAM Address- SDRAM Devices/ able Column Bank Pre- Size Address Address Select charge space 16M bit ×4 SDRAM A9−A0 A10−A0 EMIF EA11−EA2 EA12−EA2 EA13 EA12 ×8 SDRAM A8−A0 A10−A0 EMIF EA10−EA2 EA12−EA2 EA13 EA12 ×16 512K...

  • Page 86: Monitoring Page Boundaries

    SDRAM Interface 3.4.1 Monitoring Page Boundaries The C621x/C671x EMIF can simultaneously open up to four pages of SDRAM. These pages can be within a single CE space, or spread over all CE spaces. For example, two pages can be open in CE0 and CE2, or four pages can be open in CE0.

  • Page 87: Logical Address-To-Page Register Mapping

    SDRAM Interface Figure 3−6. Logical Address-to-Page Register Mapping for 32-Bit Logical Address CE space nrb=11 ncb=8 CE space nrb=11 ncb=8 nbb=2 CE space nrb=12 ncb=8 CE space nrb=12 ncb=8 nbb=2 CE space nrb=13 ncb=8 CE space nrb=13 ncb=8 nbb=2 Page Register= nrb + nbb CE space nrb=11 ncb=9...

  • Page 88: Address Shift

    SDRAM Interface 3.4.2 Address Shift The same EMIF pins determine the row and column address, thus the C621x/C671x EMIF interface appropriately shifts the address in row and column address selection. Table 3−4 describes the addressing for a 8-, 16-, and 32-bit-wide SDRAM interface. The address presented on the pins are shifted for 8-bit and 16-bit interfaces.

  • Page 89: Byte Address-To-Ea Mapping For 8-, 16-, And 32-Bit Interface

    SDRAM Interface Table 3−4. Byte Address-to-EA Mapping for 8-, 16-, and 32-Bit Interface # of [21:17] column column Interface DRAM address bus width bits É É É É É É É É É É É É É É É É É É...

  • Page 90: Mode Register Value

    SDRAM Interface 3.4.3 SDRAM Refresh Mode The RFEN bit in the SDRAM control register (SDCTL) enables the SDRAM refresh mode of the C621x/C671x EMIF. When RFEN = 0, all EMIF refreshes are disabled, and you must ensure that refreshes are implemented in an external device.

  • Page 91: Sdram Mode Register Set: Mrs Command Timing Diagram

    SDRAM Interface Table 3−5. Implied SDRAM Configuration by MRS Command Field Selection Write burst length 4 words 6−4 Read latency If TCL = 0, 2 cycles If TCL = 1, 3 cycles Serial/interleave burst type Serial 2−0 Burst length 4 words Figure 3−8.

  • Page 92: Sdram Timing Parameters

    SDRAM Interface 3.4.5 Timing Requirements Several SDRAM timing parameters decouple the EMIF from SDRAM speed limitations. The C621x/C671x EMIF has additional timing parameters that are programmable using the SDRAM control register (SDCTL) and the SDRAM extension register (SDEXT), as shown in Table 3−6. Consult the SDRAM data sheet for information on the appropriate parameters for the specific SDRAM.

  • Page 93: Recommended Values For Command-To-Command Parameters

    SDRAM Interface Table 3−7. Recommended Values for Command-to-Command Parameters Suggested Suggested value for value for Value in EMIF Parameter Description clock cycles † TCL = 0 TCL = 1 READ to READ command to READ command. RD2RD + 1 RD2RD = 0 RD2RD = 0 READ Used to interrupt a READ burst for random...

  • Page 94: Sdram Three-Word Read Timing Diagram

    SDRAM Interface 3.4.6 SDRAM Read Figure 3−9 shows the C621x/C671x EMIF performing a three word read burst from SDRAM. The EMIF uses a burst length of four, and has a programmable CAS latency of either two or three cycles. The CAS latency is three cycles in this example (CASL = 1).

  • Page 95: Sdram Three-Word Write Timing Diagram

    SDRAM Interface 3.4.7 SDRAM Write All SDRAM writes have a burst length of four on the C621x/C671x EMIF. The bank is activated with the row address during the ACTV command. Writes have no latency, so data is output on the same cycle as the column address. Writes to particular bytes are disabled using the appropriate DQM inputs;...

  • Page 96: Emif To Sbsram Interface Block Diagram

    SBSRAM Interface 3.5 SBSRAM Interface Figure 3−11 shows the SBSRAM interface on the C621x/C671x EMIF. The interface takes advantage of the internal advance counter of the SBSRAM. For this interface, the ADV signal is pulled low, so that every access to the SBSRAM from the C621x/C671x DSP is assumed to be a four-word burst.

  • Page 97: Sbsram Six-Word Read Timing Diagram

    SBSRAM Interface Table 3−8. BSRAM in Linear Burst Mode Case 1 Case 2 Case 3 Case 4 SBSRAM address A[1:0] A[1:0] A[1:0] A[1:0] EMIF address EA[3:2] EA[3:2] EA[3:2] EA[3:2] First address Fourth address 3.5.1 SBSRAM Read Figure 3−12 shows six-word read SBSRAM C621x/C671x EMIF.

  • Page 98: Sbsram Six-Word Write Timing Diagram

    SBSRAM Interface Gaps may occur within a read burst due to other DMA activities. The following specific condition also causes a gap in a read burst: when requesting a read from SBSRAM, a delay of one ECLKOUT cycle will be observed. This only happens when reading a burst of (N ×...

  • Page 99: Emif Prioritization Of Memory Requests

    Table 3−9. EMIF Prioritization of Memory Requests Priority Requestor Highest External hold Mode register set Refresh Lowest Enhanced DMA † † Refer to TMS320C6000 DSP Enhanced DMA (EDMA) Controller Reference Guide (SPRU234) for details on prioritization within the EDMA. 3-24 TMS320C621x/C671x EMIF SPRU266A...

  • Page 100: Emif Registers

    EMIF Registers 3.7 EMIF Registers Control of the EMIF and the memory interfaces it supports is maintained through memory-mapped registers within the EMIF. Access to these registers requires the EMIF clock. Table 3−10 lists the memory-mapped registers in the C621x/C671x DSP. See the device-specific datasheet for the memory address of these registers.

  • Page 101: Emif Global Control Register (Gblctl) Field Descriptions

    EMIF Registers Table 3−11. EMIF Global Control Register (GBLCTL) Field Descriptions † † Value Description field symval 31−12 Reserved − Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. BUSREQ Bus request (BUSREQ) output bit indicates if the EMIF has an access/refresh pending or in progress.

  • Page 102: Emif Ce Space Control Registers (Cectl0−3)

    EMIF Registers Table 3−11. EMIF Global Control Register (GBLCTL) Field Descriptions (Continued) † † Value Description field symval CLK1EN Not on C6713, C6712C, and C6711C DSP: CLKOUT1 enable bit. On C6713, C6712C, and C6711C DSP, this bit must be programmed to 0 for proper operation. DISABLE CLKOUT1 is held high.

  • Page 103: Emif Ce Space Control Register (Cectl) Field Descriptions

    EMIF Registers Figure 3−15. EMIF CE Space Control Register (CECTL) 28 27 22 21 20 19 WRSETUP WRSTRB WRHLD RDSETUP R/W-1111 R/W-11 1111 R/W-11 R/W-1111 14 13 RDSTRB MTYPE Reserved RDHLD R/W-11 R/W-11 1111 R/W-0010 R/W-011 Legend: R/W = Read/Write; -n = value after reset Table 3−12.

  • Page 104: Emif Ce Space Control Register (Cectl) Field Descriptions

    EMIF Registers Table 3−12. EMIF CE Space Control Register (CECTL) Field Descriptions (Continued) † † Value Description field symval 7−4 MTYPE § 0−Fh Memory type of the corresponding CE spaces. ASYNC8 8-bit-wide asynchronous interface. ASYNC16 16-bit-wide asynchronous interface. ASYNC32 32-bit-wide asynchronous interface. SDRAM32 32-bit-wide SDRAM.

  • Page 105: Emif Sdram Control Register (Sdctl) Field Descriptions

    EMIF Registers 3.7.3 EMIF SDRAM Control Register (SDCTL) The SDRAM control register (SDCTL) controls SDRAM parameters for all CE spaces that specify an SDRAM memory type in the MTYPE field of the associated CE space control register (CECTL). Because SDCTL controls all SDRAM spaces, each space must contain SDRAM with the same refresh, timing, and page characteristics.

  • Page 106: Emif Sdram Control Register (Sdctl) Field Descriptions

    EMIF Registers Table 3−13. EMIF SDRAM Control Register (SDCTL) Field Descriptions (Continued) † † Value Description field symval 27−26 SDCSZ 0−3h SDRAM column size bits. 9COL 9 column address pins (512 elements per row). 8COL 8 column address pins (256 elements per row). 10COL 10 column address pins (1024 elements per row).

  • Page 107: Emif Sdram Timing Register (Sdtim)

    EMIF Registers 3.7.4 EMIF SDRAM Timing Register (SDTIM) The SDRAM timing register (SDTIM) controls the refresh period in terms of EMIF clock cycles. The SDTIM is shown in Figure 3−17 and described in Table 3−14. Optionally, the PERIOD field can send an interrupt to the CPU. Thus, this counter can be used as a general-purpose timer if SDRAM is not used by the system.

  • Page 108: Emif Sdram Timing Register (Sdtim) Field Descriptions

    EMIF Registers Figure 3−17. EMIF SDRAM Timing Register (SDTIM) 26 25 24 23 12 11 Reserved XRFR CNTR PERIOD R/W-0 R/W-0 R-5DCh R/W-5DCh Legend: R/W = Read/Write; R = Read only; -n = value after reset Table 3−14. EMIF SDRAM Timing Register (SDTIM) Field Descriptions †...

  • Page 109: Emif Sdram Extension Register (Sdext) Field Descriptions

    EMIF Registers 3.7.5 EMIF SDRAM Extension Register (SDEXT) The SDRAM extension register (SDEXT) allows programming of many parameters of SDRAM. The SDEXT is shown in Figure 3−18 and described in Table 3−15. This programmability offers two distinct advantages: Allows an interface to a wide variety of SDRAMs and is not limited to a few configurations or speed characteristics.
  • Page 110 EMIF Registers Table 3−15. EMIF SDRAM Extension Register (SDEXT) Field Descriptions (Continued) † † Value Description field symval 16−15 R2WDQM OF(value) 0−3h Specifies number of of cycles that BEx signals must be high preceding a WRITE interrupting a READ. R2WDQM = (# of cycles BEx high) − 1 14−12 RD2WR OF(value) 0−7h...

  • Page 111: Tms320C64X Emif

    Chapter 4 TMS320C64x EMIF This chapter describes the operation and registers of the EMIF in the TMS320C64x DSP. operation registers unique TMS320C620x/C670x EMIF, see Chapter 2. For operation and registers unique to the TMS320C621x/C671x EMIF, see Chapter 3. Topic Page Overview .

  • Page 112: Tms320C64X Dsp Block Diagram

    Overview 4.1 Overview The C64x EMIF services requests of the external bus from two requestors: On-chip enhanced direct-memory access (EDMA) controller External shared-memory device controller A block diagram of the C64x DSP is shown in Figure 4−1. The C64x EMIF offers additional flexibility by replacing the SBSRAM mode with a program- mable synchronous mode, which supports glueless interfaces to the following: ZBT (zero bus turnaround) SRAM...

  • Page 113: 4.2 Emif Interface Signals

    EMIF Interface Signals 4.2 EMIF Interface Signals The EMIF signals of the C64x DSP are shown in Figure 4−2 and described in Table 4−2. These signals apply to both EMIFA and EMIFB with the exception of the SDCKE signal, which applies to EMIFA only. The C64x EMIF is an enhanced version of the C621x EMIF.

  • Page 114: Tms320C64X Emifa And Emifb Interface Signals

    EMIF Interface Signals Figure 4−2. TMS320C64x EMIFA and EMIFB Interface Signals ECLKIN EMIF ECLKOUT1 ECLKOUT2 † Shared by all external interfaces † CE[3:0] † Enhanced ARDY data memory controller SOE3 AOE/SDRAS/SOE MUXed Asynchronous/SDRAM/ ARE/SDCAS/SADS/SRE synchronous memory control AWE/SDWE/SWE HOLD HOLDA BUSREQ Control registers...

  • Page 115: Tms320C64X Emif Interface Signal Descriptions

    EMIF Interface Signals Table 4−2. TMS320C64x EMIF Interface Signal Descriptions I/O/Z Description CLKOUT4 Clock output. Runs at 1/4 the CPU clock rate. CLKOUT4 pin is MUXed with the GP1 (general-purpose input/output 1 pin); by default, this pin functions as CLKOUT4. CLKOUT6 Clock output.
  • Page 116 EMIF Interface Signals Table 4−2. TMS320C64x EMIF Interface Signal Descriptions (Continued) I/O/Z Description SDRAS Active-low row address strobe for SDRAM memory interface. Synchronous memory output enable. Active-low read strobe for asynchronous memory interface. SDCAS Active-low column address strobe for SDRAM memory interface. SADS/SRE Synchronous memory address strobe or read enable (selected by RENEN in CE space secondary control register).

  • Page 117: Addressable Memory Ranges

    Memory Width and Byte Alignment 4.3 Memory Width and Byte Alignment The C64x DSP has two EMIFs: EMIFA and EMIFB. EMIFA supports memory widths of 8 bits, 16 bits, 32 bits, and 64 bits. EMIFB supports memory widths of 8 bits and 16 bits. Table 4−3 summarizes the addressable memory ranges on the C64x device.

  • Page 118: Byte Alignment By Endianness

    Memory Width and Byte Alignment Figure 4−3. Byte Alignment by Endianness (a) EMIFA (64-bit bus): TMS320C64x EMIFA ED[63:56] ED[55:48] ED[47:40] ED[39:32] ED[31:24] ED[23:16] ED[15:8] ED[7:0] 64-bit device 32-bit device 16-bit device 8-bit device (b) EMIFA (32-bit bus): TMS320C64x EMIFA ED[31:24] ED[23:16] ED[15:8] ED[7:0]...

  • Page 119: Emifa To 64M-Bit Sdram Interface Block Diagram

    SDRAM Interface 4.4 SDRAM Interface The C64x EMIF supports SDRAM commands shown in Table 1−2 and Table 1−3 shows the signal truth table for the SDRAM commands. Table 1−4 summarizes the pin connection and related signals specific to SDRAM operation. Table 1−5 summarizes the similarities and differences on the C6000 SDRAM interface.

  • Page 120: Tms320C64X Dsp Compatible Sdram

    SDRAM Interface Table 4−4. TMS320C64x DSP Compatible SDRAM Address- Devices able SDRAM Column Bank Pre- space Size Address Address Select charge × 16M bit SDRAM A9−A0 A10−A0 EMIFA EA12−EA3 EA13−EA3 EA14 EA13 EMIFB EA10−EA1 EA11−EA1 EA12 EA11 × SDRAM A8−A0 A10−A0 EMIFA EA11−EA3...
  • Page 121 SDRAM Interface Table 4−4. TMS320C64x DSP Compatible SDRAM (Continued) Address- SDRAM Devices able Column Bank Pre- Size space Address Address Select charge × 128M bit 128M SDRAM A9−A0 A11−A0 A13−A12 EMIFA EA12−EA3 EA14−EA3 EA16−EA15 EA13 EMIFB EA10−EA1 EA12−EA1 EA14−EA13 EA11 ×...

  • Page 122: Monitoring Page Boundaries

    SDRAM Interface 4.4.1 Monitoring Page Boundaries Similar to the C621x/C671x EMIF, up to four pages of SDRAM can be opened simultaneously with the C64x EMIF SDRAM paging scheme. This can be all in one CE space, or spread across multiple CE spaces. However, the page register always stores 16 bits of address (instead of being limited by the number of row address bits plus the number of bank address bits (NRB + NBB)).

  • Page 123: Logical Address-To-Page Register Mapping For Emifa

    SDRAM Interface Figure 4−5. Logical Address-to-Page Register Mapping for EMIFA CE space nrb=11 ncb=8 CE space nrb=11 ncb=8 nbb=2 CE space nrb=12 ncb=8 CE space nrb=12 ncb=8 nbb=2 CE space nrb=13 ncb=8 CE space nrb=13 ncb=8 nbb=2 Page Register=16 bits CE space nrb=11 ncb=9...

  • Page 124: Logical Address-To-Page Register Mapping For Emifb

    SDRAM Interface Figure 4−6. Logical Address-to-Page Register Mapping for EMIFB CE space nrb=11 ncb=8 CE space nrb=11 ncb=8 nbb=2 CE space nrb=12 ncb=8 CE space nrb=12 ncb=8 nbb=2 CE space nrb=13 ncb=8 CE space nrb=13 ncb=8 nbb=2 Page Register=16 bits CE space nrb=11 ncb=9...

  • Page 125: Address Shift

    SDRAM Interface 4.4.2 Address Shift The same EMIF pins determine the row and column address, thus the C64x EMIF interface appropriately shifts the address in row and column address selection. Table 4−5 describes the addressing for a 8-, 16-, 32-, and 64-bit-wide SDRAM interface.

  • Page 126: Byte Address-To-Ea Mapping For 8-, 16-, 32-, 64-Bit Interface

    SDRAM Interface Table 4−5. Byte Address-to-EA Mapping for 8-, 16-, 32-, 64-Bit Interface EMIFB ‡ EMIFA # of Inter- ‡ column column face face address DRAM bits width É É É É É É É É É É É É É...
  • Page 127 SDRAM Interface 4.4.4 SDRAM Self-Refresh Mode The SLFRFR bit in the SDRAM control register (SDCTL) forces the C64x EMIF to place the external SDRAM in a low-power mode (self refresh), in which the SDRAM maintains valid data while consuming a minimal amount of power.

  • Page 128: Mode Register Value

    SDRAM Interface Note: The EMIF SDCKE signal must be connected to the SDRAM CKE signal for proper SLFRFR operation. 4.4.5 Mode Register Set (MRS) The C64x EMIF uses a mode register value of either 0032h or 0022h. The register value and description are shown in Figure 4−7 and summarized in Table 4−6.

  • Page 129: Sdram Mode Register Set: Mrs Command Timing Diagram

    SDRAM Interface Figure 4−8. SDRAM Mode Register Set: MRS Command Timing Diagram † Clock BE[3:0] ‡ EA[16:3] MRS value SDA10 SDRAS SDCAS SDWE † Clock = ECLKOUT1. ‡ For EMIFB, EA[14:1] are used. SPRU266A TMS320C64x EMIF 4-19...

  • Page 130: Sdram Timing Parameters

    SDRAM Interface 4.4.6 Timing Requirements Several SDRAM timing parameters decouple the EMIF from SDRAM speed limitations. The C64x EMIF has additional timing parameters that are programmable using the SDRAM control register (SDCTL) and the SDRAM extension register (SDEXT), as shown in Table 4−7. Consult the SDRAM data sheet for information on the appropriate parameters for a specific SDRAM.

  • Page 131: Recommended Values For Command-To-Command Parameters

    SDRAM Interface Table 4−8. Recommended Values for Command-to-Command Parameters Suggested Suggested value for value for Value in EMIF Parameter Description clock cycles † TCL = 0 TCL = 1 READ to READ command to READ command. RD2RD + 1 RD2RD = 0 RD2RD = 0 READ Used to interrupt a READ burst for random...

  • Page 132: Sdram Read Timing Diagram

    SDRAM Interface 4.4.7 SDRAM Read Figure 4−9 shows the C64x EMIF performing a three doubleword (EMIFA) or halfword (EMIFB) read burst from SDRAM. The EMIF uses a burst length of four, and has a programmable CAS latency of either two or three cycles. The CAS latency is three cycles in this example (CASL = 1).

  • Page 133: Sdram Write Timing Diagram

    SDRAM Interface 4.4.8 SDRAM Write All SDRAM writes have a burst length of four on the C64x EMIF. The bank is activated with the row address during the ACTV command. Writes have no latency, so data is output on the same cycle as the column address. Writes to particular bytes are disabled using the appropriate DQM inputs;...

  • Page 134: Programmable Synchronous Pins

    Programmable Synchronous Interface 4.5 Programmable Synchronous Interface The C64x EMIF offers additional flexibility by replacing the SBSRAM interface with a programmable synchronous interface. The programmable synchro- nous interface supports glueless interfaces to the following devices: Pipelined and flow-through SBSRAM Zero bus turnaround (ZBT) synchronous pipeline SRAM Synchronous FIFOs in standard and first word fall through (FWFT) mode The programmable synchronous interface is configured by the CE space secondary control register (CESEC).

  • Page 135: Emif To Sbsram Interface Block Diagram

    Programmable Synchronous Interface 4.5.1 SBSRAM Interface The programmable synchronous mode supports SBSRAM interface, shown in Figure 4−11. In order to support different synchronous memory types, the C64x SBSRAM interface combines the C620x/C670x EMIF and C621x/C671x EMIF interfaces. The C64x interface does not explicitly make use of the burst mode of the SBSRAM.

  • Page 136: Sbsram Six-Element Read Timing Diagram

    Programmable Synchronous Interface 4.5.1.1 SBSRAM Read Figure 4−12 shows a six-element (doubleword for EMIFA, halfword for EMIFB) read with a two-cycle read latency of an SBSRAM for the C64x EMIF. Every access strobes a new address into the SBSRAM, indicated by the SADS strobe low.

  • Page 137: Sbsram Six-Element Write Timing Diagram

    Programmable Synchronous Interface 4.5.1.2 SBSRAM Write Figure 4−13 shows a six-element (doubleword for EMIFA, halfword for EMIFB) write to SBSRAM. Every access strobes a new address into the SBSRAM. The C64x EMIF issues a deselect cycle at the end of the burst transfer.

  • Page 138: Emif To Zero Bus Turnaround (Zbt) Sram Interface Block Diagram

    Programmable Synchronous Interface 4.5.2 Zero Bus Turnaround (ZBT) SRAM Interface The programmable synchronous mode supports zero bus turnaround (ZBT) SRAM interface shown in Figure 4−14. For ZBT SRAM interface, the following fields in CESEC must be set: SYNCRL = 10b; 2 cycle read latency SYNCWL = 10b;...

  • Page 139: Zero Bus Turnaround (Zbt) Sram Six-Element Write Timing Diagram

    Programmable Synchronous Interface 4.5.2.1 ZBT SRAM Read The ZBT SRAM read waveforms are identical to the SBSRAM read wave- forms, since the register settings corresponding to the reads are the same. Refer to section 4.5.1.1 for details. 4.5.2.2 ZBT SRAM Write For ZBT SRAM writes, the control signal waveforms are exactly the same as standard SRAM writes.

  • Page 140: Read And Write Synchronous Fifo Interface With Glue Block Diagram

    Programmable Synchronous Interface 4.5.3 Synchronous FIFO Interface The programmable synchronous mode supports both standard timing synchronous FIFO interface and first word fall through (FWFT) FIFO interface. For synchronous FIFO interface, set the following field in CESEC: RENEN = 1; SADS/SRE signal acts as SRE signal Figure 4−16 shows the synchronous FIFO interface with glue.

  • Page 141: Glueless Synchronous Fifo Read Interface In Ce3 Space Block Diagram

    Programmable Synchronous Interface Figure 4−17. Glueless Synchronous FIFO Read Interface in CE3 Space Block Diagram ECLKOUTn † RCLK WCLK § EMIF SOE3 SADS/SRE Synchronous FIFO EXT_INTx ED[63:0] ‡ Q[n:0] ‡ D[31:0] † ECLKOUTn used is selected by the SNCCLK bit in CESEC. ‡...

  • Page 142: Standard Synchronous Fifo Read Timing Diagram (Ce0, Ce1, Or Ce2)

    Programmable Synchronous Interface 4.5.3.1 Standard Synchronous FIFO Read Figure 4−19 and Figure 4−20 show a six-word read from a standard synchro- nous FIFO. The CESEC settings are: SYNCRL = 01b; one cycle read latency RENEN = 1; SADS/SRE signal acts as SRE signal CEEXT = 0;...

  • Page 143: Standard Synchronous Fifo Read Timing Diagram (Ce3 Only)

    Programmable Synchronous Interface Figure 4−20. Standard Synchronous FIFO Read Timing Diagram (CE3 only) Read Read Read Read Read Read ECLKOUTn † CE3 (CEEXT = 0) † CE3 (CEEXT = 1) ‡ BE[7:0] ‡ EA[all] RL = 1 ‡ ED[63:0] SRE (RENEN = 1) SOE3 †...

  • Page 144: Standard Synchronous Fifo Write Timing Diagram

    Programmable Synchronous Interface 4.5.3.2 Standard Synchronous FIFO Write Figure 4−21 shows a six-word write to a standard synchronous FIFO. The CESEC settings are: SYNCWL = 00b; zero cycle write latency RENEN = 1; SADS/SRE signal acts as SRE signal Figure 4−21. Standard Synchronous FIFO Write Timing Diagram Write Write Write...
  • Page 145 Programmable Synchronous Interface 4.5.3.4 First Word Fall Through (FWFT) Synchronous FIFO Read Figure 4−22 shows a six-word read from a first word fall through (FWFT) synchronous FIFO. The CESEC settings are: SYNCRL = 00b; zero cycle read latency RENEN = 1; SADS/SRE signal acts as SRE signal CEEXT = 0;...
  • Page 146 Peripheral Device Transfer (PDT) 4.6 Peripheral Device Transfer (PDT) To perform a peripheral device transfer (PDT), the PDTS or PDTD bits in the EDMA options parameter must be appropriately set (see the TMS320C6000 DSP Enhanced DMA (EDMA) Controller Reference Guide (SPRU234) for details).

  • Page 147: Peripheral Device Transfer (Pdt) Signal Description

    Peripheral Device Transfer (PDT) 2) Generates PDT control signal (PDT) and the PDT address pins. PDT is asserted low 0, 1, 2, or 3 cycles prior to the data phase of the transaction. The PDTWL and PDTRL fields in the PDT control register (PDTCTL) control the latency of the PDT signal for write and read transfers, respec- tively (see section 4.8.7).
  • Page 148 Peripheral Device Transfer (PDT) 4.6.1 PDT Write A PDT write transfer refers to a transfer from a peripheral to memory, in which the memory is physically written. To enable a PDT write transfer, set the PDTD bit in the EDMA options field to 1. The assertion/deassertion of the PDT address pins (PDTA and PDTDIR) and the PDT pin are timed according to the destination memory clock.

  • Page 149: Pdt Write Transaction Timing Diagram

    Peripheral Device Transfer (PDT) Figure 4−23. PDT Write Transaction Timing Diagram ACTV/PDT_OPEN WRITE ECLKOUT1 †‡ BE[7:0] †‡ ED[63:0] † EA[18:14] Prev Bank/Row Bank † EA13 Prev † EA[12:3] Prev Column SDRAS SDCAS SDWE PDTA PDTDIR PDT (PDTWL = 0) PDT (PDTWL = 1) PDT (PDTWL = 2) PDT (PDTWL = 3) †...

  • Page 150: Supported Set Ups For Pdt Write Transfers

    Peripheral Device Transfer (PDT) 4.6.1.1 PDT Write Examples Both the standard synchronous (STD) FIFO interface and the first word fall through (FWFT) FIFO interface support PDT write transactions. Table 4−11 gives an overview of the supported systems. Figure 4−24 through Figure 4−29 describe the various systems where PDT write transfers are supported.

  • Page 151: Case A: Glueless Pdt Write Interface From Synchronous Fifo Block Diagram

    Peripheral Device Transfer (PDT) Figure 4−24. Case A: Glueless PDT Write Interface From Synchronous FIFO Block Diagram ECLKIN SDRAM † ECLKOUT1 SDRAS SDCAS SDWE EMIFA SDCKE BE[7:0] DQM[7:0] EA[18:3] A[15:0] PDTA (EA19) ED[63:0] D[63:0] PDTD RCLK Synchronous FIFO Q[63:0] † SDRAM must be the only memory type present in the system.

  • Page 152: Case A: Glueless Pdt Write Transfer From Synchronous Fifo Timing Diagram

    Peripheral Device Transfer (PDT) Figure 4−25. Case A: Glueless PDT Write Transfer From Synchronous FIFO Timing Diagram ACTV/PDT_OPEN WRITE ECLKOUT1 †‡ BE[7:0] †‡ ED[63:0] † EA[18:14] Prev Bank/Row Bank † EA13 Prev outputs † EA[12:3] Prev Column SDRAS SDCAS SDWE PDTA (PDTWL = 0 FWFT FIFO)

  • Page 153: Case B: Pdt Write Interface From Fwft Fifo With Glue Block Diagram

    Peripheral Device Transfer (PDT) Figure 4−26. Case B: PDT Write Interface From FWFT FIFO With Glue Block Diagram SDRAM or non-SDRAM ECLKIN ECLKOUT1 SDRAS SDCAS SDRAM SDWE EMIFA SDCKE BE[7:0] DQM[7:0] EA[18:3] A[15:0] ED[63:0] D[63:0] RCLK FWFT FIFO Q[63:0] D-FLOP SPRU266A TMS320C64x EMIF 4-43...

  • Page 154: Case B: Pdt Write Transfer From Fwft Fifo With Glue Timing Diagram

    Peripheral Device Transfer (PDT) Figure 4−27. Case B: PDT Write Transfer From FWFT FIFO With Glue Timing Diagram ACTV/PDT_OPEN WRITE ECLKOUT †‡ BE[7:0] †‡ ED[63:0] † EA[18:14] Prev Bank/Row Bank † EA13 Prev outputs † EA[12:3] Prev Column SDRAS SDCAS SDWE FIFO inputs...

  • Page 155: Case C: Pdt Write Interface From Standard Fifo With Glue Block Diagram

    Peripheral Device Transfer (PDT) Figure 4−28. Case C: PDT Write Interface From Standard FIFO With Glue Block Diagram SDRAM or non-SDRAM ECLKIN ECLKOUT1 SDRAS SDCAS SDRAM EMIFA SDWE SDCKE BE[7:0] DQM[7:0] EA[18:3] A[15:0] ED[63:0] D[63:0] RCLK Standard FIFO D-FLOP Q[63:0] SPRU266A TMS320C64x EMIF 4-45...

  • Page 156: Case C: Pdt Write Transfer From Standard Fifo With Glue Timing Diagram

    Peripheral Device Transfer (PDT) Figure 4−29. Case C: PDT Write Transfer From Standard FIFO With Glue Timing Diagram ACTV/PDT_OPEN WRITE ECLKOUT †‡ BE[7:0] †‡ ED[63:0] † EA[18:14] Prev Bank/Row † EA13 Prev outputs † EA[12:3] Prev Column SDRAS SDCAS SDWE FIFO inputs †...
  • Page 157 Peripheral Device Transfer (PDT) 4.6.2 PDT Read A PDT read transfer refers to a transfer from memory to a peripheral, in which the memory is physically read. To enable a PDT read transfer, set the PDTS bit in the EDMA options field to 1. The assertion/deassertion of the PDT address pins (PDTA and PDTDIR) and the PDT pin are timed according to the source memory clock.

  • Page 158: Pdt Read Transaction (Cas Latency Is 3) Timing Diagram

    Peripheral Device Transfer (PDT) Figure 4−30. PDT Read Transaction (CAS Latency is 3) Timing Diagram Read data latched Read data latched Read data latched ACTV/PDT_OPEN Read Read data latched ECLKOUT †‡ BE[7:0] †‡ ED[63:0] † EA[18:14] Prev Bank/Row † EA13 Prev †...

  • Page 159: Case D: Glueless Pdt Read Interface To Synchronous Fifo Block Diagram

    Peripheral Device Transfer (PDT) 4.6.2.1 PDT Read Examples Both the standard synchronous FIFO interface and the first word fall through (FWFT) FIFO interface support PDT read transactions. Figure 4−31 shows an example of a PDT read transaction from SDRAM to a synchronous FIFO. The PDT signal is used to generate the write enable (WEN) input to the FIFO.

  • Page 160: Case D: Glueless Pdt Read Transfer To Synchronous Fifo Timing Diagram

    Peripheral Device Transfer (PDT) Figure 4−32. Case D: Glueless PDT Read Transfer to Synchronous FIFO Timing Diagram Read data latched Read data latched Read data latched Read data ACTV/PDT_OPEN Read latched ECLKOUT †‡ BE[7:0] †‡ ED[63:0] † EA[18:14] Prev Bank/Row †...
  • Page 161 Peripheral Device Transfer (PDT) 4.6.3 PDT Transfers with Multiple FIFOs on the Same Bus The following sections describe PDT transfers with multiple FIFOs connected to a single CE space via the same data bus. 4.6.3.1 PDT Read and Write Transactions on the Same Bus If both PDT read and write transactions are required on the same bus, glue is required to properly create the OE, REN, and WEN signals for the FIFO.

  • Page 162: Case E: Pdt Read And Write Interface With Multiple Fifos Block Diagram

    Peripheral Device Transfer (PDT) Figure 4−33. Case E: PDT Read and Write Interface With Multiple FIFOs Block Diagram SDRAM or non-SDRAM ECLKIN ECLKOUT1 SDRAS SDCAS SDRAM SDWE EMIFA SDCKE BE[7:0] DQM[7:0] EA[18:3] A[15:0] PDTDIR (EA20) ED[63:0] D[63:0] RCLK Direction Synchronous detect FIFO Q[63:0]...

  • Page 163: Case E: Pdt Write Transfer With Read And Write Fifos In The System (Fwft Fifo) Timing Diagram

    Peripheral Device Transfer (PDT) Figure 4−34. Case E: PDT Write Transfer with Read and Write FIFOs in the System (FWFT FIFO) Timing Diagram WRITE ACTV/PDT_OPEN ECLKOUT † ED[63:0] PDTDIR † For EMIFB, ED[15:0] is used; for 32-bit EMIFA, ED[31:0] is used. Figure 4−35.

  • Page 164: Limitations On The Number Of Additional Peripherals For A Pdt Transfer

    Peripheral Device Transfer (PDT) 4.6.3.2 Multiple PDT Read and Write Transactions on the Same Bus Each of the previous systems can extend to include additional read and or write FIFOs. In a system where more than two synchronous FIFOs interface to a single CE space, additional unused upper row address bits of the SDRAM can be used to select the appropriate FIFO for the current transaction.

  • Page 165: Dma Configuration For A Pdt Transfer

    (MTYPE) bus width. Element size (ESIZE) is set to a 32-bit word. This is a preferred setting, see the TMS320C6000 DSP Enhanced DMA (EDMA) Controller Reference Guide (SPRU234). Element count (ELECNT) is set to a multiple of the bus width size (in elements).

  • Page 166: Emif Prioritization Of Memory Requests

    Table 4−14. EMIF Prioritization of Memory Requests Priority Requestor Highest External hold Mode register set Refresh Lowest EDMA † † Refer to TMS320C6000 DSP Enhanced DMA (EDMA) Controller Reference Guide (SPRU234) for details on prioritization within the EDMA. 4-56 TMS320C64x EMIF SPRU266A...

  • Page 167: Emif Global Control Register (Gblctl)

    EMIF Registers 4.8 EMIF Registers Control of the EMIF and the memory interfaces it supports is maintained through memory-mapped registers within the EMIF. Access to these registers requires the EMIF clock. Table 4−15 lists the memory-mapped registers in the C64x DSP. See the device-specific datasheet for the memory address of these registers.

  • Page 168: Emif Registers

    EMIF Registers Table 4−16. EMIF Global Control Register (GBLCTL) Field Descriptions † † Value Description field symval 31−20 Reserved − Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. § 19−18 EK2RATE 0−3h ECLKOUT2 rate.
  • Page 169 EMIF Registers Table 4−16. EMIF Global Control Register (GBLCTL) Field Descriptions (Continued) † † Value Description field symval ARDY ARDY input bit. Valid ARDY bit is shown only when performing asynchronous memory access (when async CEn is active). ARDY input is low. External device is not ready. HIGH ARDY input is high.

  • Page 170: Emif Ce Space Control Registers (Cectl0−3)

    EMIF Registers Table 4−16. EMIF Global Control Register (GBLCTL) Field Descriptions (Continued) † † Value Description field symval CLK6EN ¶ CLKOUT 6 enable bit. CLKOUT6 pin is muxed with GP2 pin. Upon exiting reset, CLKOUT6 is enabled and clocking. After reset, CLKOUT6 may be configured as GP2 via the GPIO enable register (GPEN).

  • Page 171: Emif Ce Space Control Register (Cectl)

    EMIF Registers Figure 4−37. EMIF CE Space Control Register (CECTL) 28 27 22 21 20 19 WRSETUP WRSTRB WRHLD RDSETUP R/W-1111 R/W-11 1111 R/W-11 R/W-1111 14 13 RDSTRB MTYPE WRHLDMSB RDHLD R/W-11 R/W-11 1111 R/W-0 R/W-0 R/W-011 Legend: R/W = Read/Write; -n = value after reset Table 4−17.
  • Page 172 EMIF Registers Table 4−17. EMIF CE Space Control Register (CECTL) Field Descriptions (Continued) † † Value Description field symval 7−4 MTYPE § 0−Fh Memory type of the corresponding CE spaces. ASYNC8 8-bit-wide asynchronous interface. ASYNC16 16-bit-wide asynchronous interface. ASYNC32 32-bit-wide asynchronous interface. SDRAM32 32-bit-wide SDRAM.

  • Page 173: Emif Ce Space Secondary Control Register (Cesec)

    EMIF Registers 4.8.3 EMIF CE Space Secondary Control Registers (CESEC0−3) The CE space secondary control register (CESEC) is shown in Figure 4−38 and described in Table 4−18. These registers are added for the programmable synchronous interface, and control the cycle timing of programmable synchronous memory accesses and the clock, used for synchronization for the specific CE space.

  • Page 174: Emif Ce Space Secondary Control Register (Cesec) Field Descriptions

    EMIF Registers Table 4−18. EMIF CE Space Secondary Control Register (CESEC) Field Descriptions † † Value Description field symval 31−7 Reserved − Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. SNCCLK Synchronization clock selection bit.

  • Page 175: Emif Sdram Control Register (Sdctl)

    EMIF Registers 4.8.4 EMIF SDRAM Control Register (SDCTL) The SDRAM control register (SDCTL) controls SDRAM parameters for all CE spaces that specify an SDRAM memory type in the MTYPE field of the associated CE space control register (CECTL). Because SDCTL controls all SDRAM spaces, each space must contain SDRAM with the same refresh, timing, and page characteristics.
  • Page 176 EMIF Registers Table 4−19. EMIF SDRAM Control Register (SDCTL) Field Descriptions (Continued) † † Value Description field symval 29−28 SDRSZ 0−3h SDRAM row size bits. 11ROW 11 row address pins (2048 rows per bank). 12ROW 12 row address pins (4096 rows per bank). 13ROW 13 row address pins (8192 rows per bank).

  • Page 177: Emif Sdram Timing Register (Sdtim)

    EMIF Registers Table 4−19. EMIF SDRAM Control Register (SDCTL) Field Descriptions (Continued) † † Value Description field symval 11−1 Reserved − Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. SLFRFR Self-refresh mode, if SDRAM is used in the system: DISABLE...

  • Page 178: Emif Sdram Timing Register (Sdtim)

    EMIF Registers Figure 4−40. EMIF SDRAM Timing Register (SDTIM) 26 25 24 23 12 11 Reserved XRFR CNTR PERIOD R/W-0 R/W-0 R-5DCh R/W-5DCh Legend: R/W = Read/Write; R = Read only; -n = value after reset Table 4−20. EMIF SDRAM Timing Register (SDTIM) Field Descriptions †...

  • Page 179: Emif Sdram Extension Register (Sdext)

    EMIF Registers 4.8.6 EMIF SDRAM Extension Register (SDEXT) The SDRAM extension register (SDEXT) allows programming of many parameters of SDRAM. The SDEDXT is shown in Figure 4−41 and described in Table 4−21. The programmability offers two distinct advantages: Allows an interface to a wide variety of SDRAMs and is not limited to a few configurations or speed characteristics.
  • Page 180 EMIF Registers Table 4−21. EMIF SDRAM Extension Register (SDEXT) Field Descriptions (Continued) † † Value Description field symval 16−15 R2WDQM OF(value) 0−3h Specifies number of of cycles that BEx signals must be high pre- ceding a WRITE interrupting a READ. R2WDQM = (# of cycles BEx high) −...

  • Page 181: Emif Peripheral Device Transfer Control Register (Pdtctl) Field Descriptions

    EMIF Registers 4.8.7 EMIF Peripheral Device Transfer Control Register (PDTCTL) The peripheral device transfer control register (PDTCTL) configures the latency of the PDT signal with respect to the data phase of the transaction. The PDTCTL is shown in Figure 4−42 and defined in Table 4−22. Figure 4−42.

  • Page 182: Document Revision History

    Appendix A Appendix A Revision History Table A−1 lists the changes made since the previous version of this document. Table A−1. Document Revision History Page Additions/Modifications/Deletions Added last paragraph in section 1.3.1: For the duration of SDRAM initialization, the BE signals are inactive high.
  • Page 183 Revision History Table A−1. Document Revision History (Continued) Page Additions/Modifications/Deletions Added second and third paragraph in section 2.4: The C620x/C670x EMIF allows programming of the SDRAM column size to be 8 or 9 address bits. The number of row address bits and bank bits are not user-programmable.
  • Page 184 Revision History Table A−1. Document Revision History (Continued) Page Additions/Modifications/Deletions 3-10 Added Note in Table 3−3: Other SDRAM configurations are possible, if the number of column, row, and bank bits are supported by the C621x/C671x DSP. 3-12 Changed title in Figure 3−6: Logical Address-to-Page Register Mapping for 32-Bit Logical Address 3-23 Added first two sentences: Gaps may occur within a read burst due to other DMA activities.
  • Page 185 Revision History Table A−1. Document Revision History (Continued) Page Additions/Modifications/Deletions 4-25 Changed first paragraph in section 4.5.1. The programmable synchronous mode supports SBSRAM interface, shown in Figure 4−11. In order to support different synchronous memory types, the C64x SBSRAM interface combines the C620x/C670x EMIF and C621x/C671x EMIF interfaces.
  • Page 186 Index Index EMIF to 16M-bit SDRAM interface C620x/C670x DSP 2-7 C621x/C671x DSP 3-9 ARDY bit, in GBLCTL EMIF to 32-bit SRAM interface 1-15 C6201/C6701 DSP 2-24 EMIF to 64M-bit SDRAM interface C6202/C6203/C6204/C6205 DSP 2-24 C620x/C670x DSP 2-7 C621x/C671x DSP 3-25 C64x DSP 4-9 C64x DSP 4-57 EMIF to ROM interface...
  • Page 187 Index EMIF global control register (GBLCTL) C620x/C670x DSP 2-23 C621x/C671x DSP 3-25 CE space control registers (CECTL) C64x DSP 4-57 C620x/C670x DSP 2-27 EMIF interface C621x/C671x DSP 3-27 programmable synchronous interface C64x DSP 4-60 (C64x DSP) 4-24 CE space secondary control registers SBSRAM 4-25 (CESEC) 4-63 synchronous FIFO 4-30...
  • Page 188 Index EMIF to ROM interface 8-bit 1-16 16-bit 1-16 INIT bit, in SDCTL 32-bit 1-16 C620x/C670x DSP 2-29 EMIF to SBSRAM interface C621x/C671x DSP 3-30 C620x/C670x DSP 2-17 C64x DSP 4-65 C621x/C671x DSP 3-21 C64x DSP 4-25 EMIF to synchronous FIFO interface (C64x DSP) glueless read 4-31 glueless write 4-31 MAP bit, in GBLCTL...
  • Page 189 C6201/C6701 DSP 2-24 C621x/C671x DSP 3-32 C6202/C6203/C6204/C6205 DSP 2-24 C64x DSP 4-67 RD2DEAC bits, in SDEXT related documentation from Texas Instruments iii C621x/C671x DSP 3-34 RENEN bit, in CESEC 4-63 C64x DSP 4-69 resetting the EMIF 1-27 RD2RD bit, in SDEXT...
  • Page 190 Index ROM access modes (C620x/C670x DSP) 2-20 SDRAM extension register (SDEXT) 8-bit ROM mode 2-21 C621x/C671x DSP 3-34 16-bit ROM mode 2-21 C64x DSP 4-69 SDRAM initialization 1-8 SDRAM interface C6000 DSP 1-4 activation 1-12 SBSRAM interface commands 1-4 C6000 DSP 1-13 commands truth table 1-5 differences summary 1-14 deactivation 1-10...
  • Page 191 Index SDRSZ bit, in SDCTL TRP bits, in SDCTL C621x/C671x DSP 3-30 C620x/C670x DSP 2-29 C64x DSP 4-65 C621x/C671x DSP 3-30 C64x DSP 4-65 SDTIM TRRD bit, in SDEXT C620x/C670x DSP 2-31 C621x/C671x DSP 3-34 C621x/C671x DSP 3-32 C64x DSP 4-67 C64x DSP 4-69 TWR bits, in SDEXT SDWID bit, in SDCTL 2-29...

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