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Video Display Registers
4.12.22 Video Display Display Event Register (VDDISPEVT)
The video display display event register (VDDISPEVT) is programmed with
the number of DMA events to be generated for display field 1 and field 2. The
VDDISPEVET is shown in Figure 4–60 and described in Table 4–27.
Figure 4–60. Video Display Display Event Register (VDDISPEVT)
31
28 27
Reserved
R-0
15
12 11
Reserved
R-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 4–27. Video Display Display Event Register (VDDISPEVT) Field Descriptions
†
Bit
field
symval
31–28 Reserved
–
27–16 DISPEVT2
OF(value)
15–12 Reserved
–
11–0
DISPEVT1
OF(value)
† For CSL implementation, use the notation VP_VDDISPEVT_DISPEVTn_symval
4-84
Video Display Port
BT.656 and Y/C Mode
†
Value
0
Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
0–FFFh
Specifies the number of DMA
event sets (YEVT, CbEVT,
CrEVT) to be generated for
field 2 output.
0
Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
0–FFFh
Specifies the number of DMA
event sets (YEVT, CbEVT,
CrEVT) to be generated for
field 1 output.
DISPEVT2
R/W-0
DISPEVT1
R/W-0
Description
Raw Data Mode
Specifies the number of DMA
events (YEVT) to be
generated for field 2 output.
Specifies the number of DMA
events (YEVT) to be
generated for field 1 output.
16
0
SPRU629
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