Page 1 TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide Literature Number: SPRU234B March 2005...
Page 2 Reserved bits in a register figure designate a bit that is used for future device expansion. Related Documentation From Texas Instruments The following documents describe the C6000™ devices and related support tools. Copies of these documents are available on the Internet at www.ti.com.
Page 3 Trademarks Related Documentation From Texas Instruments / Trademarks TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190) describes the peripherals available on the TMS320C6000™ DSPs. TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the TMS320C62x™ and TMS320C67x™ DSPs, develop- ment tools, and third-party support.
Page 4: Table Of Contents
Provides an overview and describes the common operation of the enhanced direct-memory access (EDMA) controller in the digital signal processors (DSPs) of the TMS320C6000 DSP family. Also describes the quick DMA (QDMA) used for fast data requests by the CPU.
Page 5 Contents EDMA Transfer Controller ............Describes the EDMA transfer controller (EDMATC).
Page 6 Contents TMS320C64x EDMA ............. Describes the operation and registers of the EDMA controller in the TMS320C64x DSP.
Page 7 Figures Figures 1−1 TMS320C621x/C671x/C64x DSP Block Diagram ....... . . 1−2 EDMA Channel Controller Block Diagram .
Page 8 Figures 3−5 Priority Queue Status Register (PQSR) ......... 3-14 3−6 EDMA Channel Interrupt Pending Register (CIPR)
Page 9 Figures 4−27 QDMA Registers ............4-44 4−28 QDMA Channel Options Register (QOPT)
Page 10 Figures A−42 Block Synchronized 2D-to-2D Transfer (SUM = 00, DUM = 00) ....A-47 A−43 Block Synchronized 2D-to-2D Transfer (SUM = 00, DUM = 01) .
Page 11 Tables Tables 1−1 Differences Between the C621x/C671x and C64x EDMA ......1−2 EDMA Parameter RAM Contents—C6416 DSP .
Page 12 Tables 3−22 EDMA Channel Transfer Count Parameter (CNT) Field Descriptions ....3-26 3−23 EDMA Channel Destination Address Parameter (DST) Field Descriptions ... 3-27 3−24 EDMA Channel Index Parameter (IDX) Field Descriptions...
Page 13 Chapter 1 Overview This chapter provides an overview and describes the common operation of the enhanced direct memory access channel controller (EDMACC) in the digital signal processors (DSPs) of the TMS320C6000™ DSP family. This chapter also describes the quick DMA (QDMA) used for direct data requests by the CPU.
Page 14: 1.1 Overview
Overview 1.1 Overview The enhanced direct memory access (EDMA) controller handles all data transfers between the level-two (L2) cache/memory controller and the device peripherals on the C621x/C671x/C64x DSP, as shown in Figure 1−1. These data transfers include cache servicing, non-cacheable memory accesses, user-programmed data transfers, and host accesses.
Page 15: Tms320C621X/C671X/C64X Dsp Block Diagram
Overview Figure 1−1. TMS320C621x/C671x/C64x DSP Block Diagram L1P cache direct mapped controller External memory CPU core interface EDMA Instruction fetch (EMIF) Control registers transfer Instruction dispatch controller In-circuit emulation (EDMATC) Instruction decode Other Data path 1 Data path 2 Peripherals A register file B register file EDMA...
Page 16: Edma Channel Controller Block Diagram
Overview Figure 1−2. EDMA Channel Controller Block Diagram Parameter RAM Chain Event (PaRAM) trigger trigger trigger Ch0 parameter set Event 0 Ch1 parameter set Event 1 Transfer From Ch2 parameter set Event 2 request peripherals Ch3 parameter set Event 3 (TR) or external (to EDMA...
Page 17: Differences Between The C621X/C671X And C64X Edma
Overview Table 1−1. Differences Between the C621x/C671x and C64x EDMA Features C621x/C671x EDMA C64x EDMA Alternate transfer complete Does not apply. Supported chaining and interrupt CIPR, CIER, CCER, ER, EER, Each of these registers supports Each of these registers supports ECR, ESR 16 channels.
Page 18: 1.2 Edma Terminology
EDMA Terminology 1.2 EDMA Terminology The following definitions help in understanding some of the terms used in this document: Enhanced Direct Memory Access (EDMA) Controller: Consists of the EDMA transfer controller (EDMATC) and the EDMA channel controller (EDMACC). EDMA Transfer Controller (EDMATC): The central data transfer engine of the EDMA.
Page 19 EDMA Terminology Array-Synchronized Transfer: An array-synchronized transfer submits a transfer request (TR) for a single array of element count elements when a synchronization event is received. The EDMA channel controller updates the source address, destination address, and array count after each TR.
Page 20: 1.3 Parameter Ram Overview
Parameter RAM Overview EDMA Terminology / Parameter RAM Overview 1-dimensional (1D) transfer: A group of frames comprise a 1D block. The number of frames (FRMCNT) in a block can range from 1 to 65536. The number of elements (ELECNT) per frame can range from 1 to 65535. Either elements or full frames can be transferred at a time.
Page 21: Edma Parameter Ram Contents-C6416 Dsp
Parameter RAM Overview Table 1−2. EDMA Parameter RAM Contents—C6416 DSP Address Parameters 01A0 0000h to 01A0 0017h Parameters for event 0 (6 words) 01A0 0018h to 01A0 002Fh Parameters for event 1 (6 words) 01A0 0030h to 01A0 0047h Parameters for event 2 (6 words) 01A0 0048h to 01A0 005Fh Parameters for event 3 (6 words) 01A0 0060h to 01A0 0077h...
Page 22: Edma Channel Parameter Entries For Each Edma Event-C6416 Dsp
Parameter RAM Overview Figure 1−3. EDMA Channel Parameter Entries for Each EDMA Event—C6416 DSP EDMA parameter Word 0 EDMA Channel Options Parameter (OPT) Word 1 EDMA Channel Source Address (SRC) Word 2 Array/frame count (FRMCNT) Element count (ELECNT) Word 3 EDMA Channel Destination Address (DST) Word 4 Array/frame index (FRMIDX)
Page 23: 1.4 Types Of Edma Transfers
Types of EDMA Transfers 1.4 Types of EDMA Transfers The EDMA provides for two types of data transfers, 1-dimensional (1D) and 2-dimensional (2D). The 2DD and 2DS fields in the channel options parameter register (OPT) select the type of transfer. When the 2DD field is set to 1, a 2D transfer on the destination is performed.
Page 24 Types of EDMA Transfers 1.4.1.1 Element Synchronized 1D Transfer (FS = 0) Note: For element synchronized transfers, ELERLD should be set to the ELECNT value by the programmer. For an element synchronized transfer, each sync event transfers a single element. After each sync event is received and the single-element TR is submitted to the EDMA, the EDMA channel controller updates the source and destination addresses within the parameter table.
Page 25 Types of EDMA Transfers If linking is enabled (LINK = 1, see section 1.11), the complete transfer parameters get reloaded (from the parameter reload space in EDMA channel controller parameter RAM) after sending the last transfer request to the EDMA transfer controller.
Page 26: 2-Dimensional Transfers
Types of EDMA Transfers If linking is enabled (LINK = 1, see section 1.11), the complete transfer parameters get reloaded (from the parameter reload space in EDMA channel controller parameter RAM) after sending the last transfer request to the EDMA transfer controller.
Page 27 Types of EDMA Transfers 1.4.2.1 Array Synchronized 2D Transfer (FS = 0) For an array synchronized transfer, each sync event transfers a single array of contiguous elements. A channel that is configured to perform a 2D transfer with array synchronization updates its source and destination registers after the transfer request for each array is submitted.
Page 28 Types of EDMA Transfers 1.4.2.2 Block Synchronized 2D Transfer (FS = 1) For a 2D block synchronized transfer, a single sync event transfers an entire block of arrays. For a 2D transfer, the complete block gets transferred when the channel’s event occurs and FS = 1. Block synchronization causes the address generation/transfer logic to implement the array index (FRMIDX).
Page 29: 1.5 Initiating An Edma Channel Controller Transfer
Initiating an EDMA Channel Controller Transfer 1.5 Initiating an EDMA Channel Controller Transfer There are three ways to initiate a programmed data transfer using the EDMA channel controller (EDMACC): Event-triggered transfer request (this is a typical usage of the EDMACC). Allows for a peripheral, system, or externally-generated event to trigger a transfer request (TR).
Page 30: Chain-Triggered Transfer Request
Initiating an EDMA Channel Controller Transfer 1.5.2 Chain-Triggered Transfer Request Chaining is a mechanism by which the completion of one transfer automatically triggers the transfer request (TR) submission for another channel. When a transfer completion code (TCC/ATCC) is received, if the corresponding bit in the channel chain enable register is enabled (CCERn = 1), then the EDMA channel controller processes the corresponding PaRAM channel entry.
Page 31: 1.6 Edma Channel Controller Event-To-Channel Mapping
EDMA Channel Controller Event-to-Channel Mapping 1.6 EDMA Channel Controller Event-to-Channel Mapping All EDMA channels are tied to a specific synchronization event. Synchronization allows EDMA transfers to be triggered by events from peripherals, external hardware, or an EDMA transfer completion event. A channel only requests a data transfer when it receives its event or when the CPU manually synchronizes it (by writing to ESR).
Page 32: Edma Channel Synchronization Events-C6211 Dsp
EDMA Channel Controller Event-to-Channel Mapping Table 1−4. EDMA Channel Synchronization Events—C6211 DSP EDMA Channel Number † Event Acronym Event Description DSPINT Host port to DSP interrupt TINT0 Timer 0 interrupt TINT1 Timer 1 interrupt SD_INT EMIF SDRAM timer interrupt EXT_INT4 External interrupt pin 4 EXT_INT5 External interrupt pin 5...
Page 33: Edma Channel Synchronization Events-C6416 Dsp
EDMA Channel Controller Event-to-Channel Mapping Table 1−5. EDMA Channel Synchronization Events—C6416 DSP EDMA Channel Number † Event Acronym Event Description DSPINT Host port to DSP interrupt TINT0 Timer 0 interrupt TINT1 Timer 1 interrupt SD_INT0 EMIFA SDRAM timer interrupt GPINT4/EXT_INT4 GPIO event 4/External interrupt 4 GPINT5/EXT_INT5 GPIO event 5/External interrupt 5...
Page 34 EDMA Channel Controller Event-to-Channel Mapping Table 1−5. EDMA Channel Synchronization Events—C6416 DSP (Continued) EDMA Channel † Number Event Acronym Event Description VCPXEVT VCP transmit interrupt TCPREVT TCP receive interrupt TCPXEVT TCP transmit interrupt UREVT UTOPIA receive event 33−39 − None UXEVT UTOPIA transmit event 41−47...
Page 35: 1.7 Element Size And Alignment
Fixed-Mode Transfer Considerations Element Size and Alignment / Fixed-Mode Transfer Considerations 1.7 Element Size and Alignment The element size that the EDMA channel controller (EDMACC) uses for a transfer is specified in the ESIZE field of the channel op tions parameter regis- †...
Page 36: Fixed-Mode Transfer Considerations
Fixed-Mode Transfer Considerations Then you must ensure that the following conditions are true: Element count (ELECNT) must be a multiple of 2 Frame/Array index field must be a multiple of 8 bytes (2 words, 1 doubleword) Both the source address and destination address must be double- word aligned (that is, a multiple of 8 bytes (2 words, 1 doubleword)) Operation is undefined, if the above conditions are not met.
Page 37: 1.9 Parameter Set Updates
Parameter Set Updates 1.9 Parameter Set Updates 1.9.1 Element and Frame/Array Count Updates The EDMA channel controller parameter entry contains values for the element count (ELECNT) and frame/array count (FRMCNT). Each entry is a 16-bit unsigned value. ELECNT specifies the actual number of elements in a frame or array.
Page 38: Source/Destination Address Updates
Parameter Set Updates Reloading the element count for element synchronized transfers has a special condition. When a sync event occurs at the end of a frame (ELECNT = 1 prior to event), the EDMA channel controller sends off the transfer request and re- loads ELECNT from the element count reload field in the parameter RAM.
Page 39: Source/Destination Address Update Modes
Parameter Set Updates Table 1−7. Source/Destination Address Update Modes SUM/DUM Bit Address Value (Binary) Modification 1D Transfer 2D Transfer None All elements located at the same All elements in an array are at the address. same address. Increment All elements are contiguous, with All elements within an array are subsequent elements located at a contiguous, with subsequent...
Page 40: Edma Source Address Parameter Updates
Parameter Set Updates Table 1−8. EDMA Source Address Parameter Updates Source Update Mode (SUM) Sync Type 2DS:2DD 00 Element None +ESIZE −ESIZE +ELEIDX or + FRMIDX if ELECNT = 1 Increment by element Decrement by element Add signed ELEIDX to size.
Page 41: Edma Destination Address Parameter Updates
Parameter Set Updates Table 1−9. EDMA Destination Address Parameter Updates Destination Update Mode (DUM) Sync Type 2DS:2DD 00 Element None +ESIZE −ESIZE +ELEIDX or + FRMIDX if ELECNT = 1 Increment by element Decrement by element size. size. Add signed ELEIDX to each element in a frame except the last.
Page 42: 1.10 Channel Completion Conditions
Channel Completion Conditions 1.10 Channel Completion Conditions A parameter set for a given channel is complete when the required number of transfer requests are submitted (based on receiving the required number of synchronization events). This is shown in Table 1−10 for each transfer type. Table 1−10.
Page 43: 1.11 Linking Edma Transfers
Linking EDMA Transfers 1.11 Linking EDMA Transfers The EDMA channel controller (EDMACC) provides linking, a feature especially useful for maintaining ping-pong buffers, complex sorting, and circular buffer- ing all with no CPU intervention. If LINK = 1, upon completion of a transfer, the EDMACC link feature reloads the current transfer parameters with the param- eter pointed to by the 16-bit link address.
Page 44: Linked Edma Transfer
Linking EDMA Transfers Figure 1−10. Linked EDMA Transfer Reload Event N parameters with Event N parameters parameters located at address 01A0 0180h Options (LINK=1) Options (LINK=1) Source (SRC) address Source (SRC) address Array/Frame count Element count Array/Frame count Element count Destination (DST) address Destination (DST) address Array/Frame index...
Page 45: 1.12 Terminating An Edma Transfer
Terminating an EDMA Transfer Terminating an EDMA Transfer / Chaining EDMA Channels 1.12 Terminating an EDMA Transfer All EDMA channel controller (EDMACC) transfers must terminate by linking to a NULL parameter set after the last transfer. The NULL parameter set serves as the termination point of any EDMA transfer.
Page 46: 1.14 Transfer Complete Code (Tcc) Generation
Transfer Complete Code (TCC) Generation 1.14 Transfer Complete Code (TCC) Generation The EDMA channel controller (EDMACC) and EDMA transfer controller (EDMATC) provide a user-programmable transfer completion code (TCC) that is programmable in the TCC field of the channel options parameter (OPT). If enabled for completion code generation (TCINT = 1) on the final TR submis- sion for a parameter set, the EDMACC submits the transfer completion code to the EDMATC along with the TR (see Table 1−10 for details on when a...
Page 47: Transfer Complete Code (Tcc) To Edma Interrupt Mapping (C621X/C671X Dsp)
Transfer Complete Code (TCC) Generation For example, if TCC = 1100b (and also TCCM = 00 for the C64x DSP), CIPR[12] (C621x/C671x DSP) or CIPRL[12] (C64x DSP) is set to 1 after the transfer is complete, and this generates a CPU interrupt only if CIER[12] = 1. You can program the transfer complete code to any value in Table 1−11 for any EDMA channel.
Page 48: Alternate Transfer Complete Code (Atcc) Generation (C64X Edma Only)
Transfer Complete Code (TCC) Generation 1.14.1 Alternate Transfer Complete Code (ATCC) Generation (C64x EDMA only) The C64x EDMA also supports (in addition to TCC) a user-programmable alternate transfer complete code (ATCC) that is programmable in the ATCC field of the channel options parameters (OPT). If enabled for alternate transfer complete code generation (ATCINT = 1), on every TR submission except for the final TR of a parameter set, the EDMACC submits the alternate transfer complete code to the EDMATC along with the TR (see Table 1−13 for details...
Page 49: 1.15 Edma Interrupt Generation Based On Completion Code
EDMA Interrupt Generation Based on Completion Code Transfer Complete Code (TCC) Generation / EDMA Interrupt Generation Based on Completion Code Table 1−13. Channel Completion Conditions For Alternate Transfer Complete Codes Total number of alternate transfer complete code Total number of completion (ATCC) requests code requests Sync Type...
Page 50: 1.15.1 Edmaint Servicing By The Cpu
EDMA Interrupt Generation Based on Completion Code In summary, to configure the EDMA for any channel (or QDMA request) to interrupt the CPU: Set CIEn to 1, in CIER Set TCINT (or ATCINT) to 1, in OPT Set TCC (or ATCC) to n, in OPT 1.15.1 EDMAINT Servicing by the CPU When a completion code is detected by the EDMACC, the EDMACC sets the appropriate bit in CIPR as per the transfer complete code specified.
Page 51: Quick Dma (Qdma)
Quick DMA (QDMA) 1.16 Quick DMA (QDMA) Quick DMA (QDMA) provides an alternate means for the CPU to directly sub- mit transfer requests (TR) to the EDMA transfer controller without using the EDMA channel controller. Since the QDMA registers are local to the CPU, the total amount of time for setting up a QDMA transfer is less than the time to set up a transfer in the EDMA channel controller.
Page 52: 1.16.2 Qdma Stalls And Priority
Emulation Operation Quick DMA (QDMA) / Emulation Operation All of the QDMA registers retain their value after the request is submitted, so if a second transfer is performed with any of the same parameter settings, they do not need to be rewritten by the CPU. Only the changed registers require rewriting, with the final parameter written to the appropriate pseudo-register to submit the transfer.
Page 53: 1.18 Transfer Examples
Transfer Examples 1.18 Transfer Examples The EDMA channel controller performs a wide variety of transfers depending on the parameter configuration. The more basic transfers are performed either by an EDMA channel or by submitting a QDMA. More complicated transfers or repetitive transfers require the use of an EDMA channel. For a representa- tion of various types of EDMA transfers, see Appendix A.
Page 54: Block Move Example Qdma Registers Content
Transfer Examples Figure 1−13. Block Move Example QDMA Registers Content (a) QDMA Registers Register Contents Register 4120 0001h QDMA Channel Options Register (QOPT) A000 0000h QDMA Channel Source Address Register (QSRC) 0000h 0100h QDMA Channel Transfer Count Register (QCNT) 0000 2000h QDMA Channel Destination Address Register (QDST) Don’t care Don’t care...
Page 55: 1.18.2 Subframe Extraction Example
Transfer Examples A block that contains greater than 64K elements requires the use of both element count and array/frame count. Since the element count field is only 16 bits, the largest count value that can be represented is 65535. Any count larger than 65535 needs to be represented with an array count as well.
Page 56: Subframe Extraction Example Qdma Registers Content
Transfer Examples Figure 1−15. Subframe Extraction Example QDMA Registers Content (a) QDMA Registers Register Contents Register 4D20 0001h QDMA Channel Options Register (QOPT) A000 0788h QDMA Channel Source Address Register (QSRC) 000Bh 0010h QDMA Channel Transfer Count Register (QCNT) 0000 2000h QDMA Channel Destination Address Register (QDST) 04E0h Don’t care...
Page 57: 1.18.3 Data Sorting Example
Transfer Examples 1.18.3 Data Sorting Example Many applications require the use of multiple data arrays; it is often desirable to have the arrays arranged such that the first elements of each array are adjacent, the second elements are adjacent, and so on. Often this is not how the data is presented to the device.
Page 58: Data Sorting Example Qdma Registers Content
Transfer Examples For this example, assume that the 16-bit data is located in external RAM, beginning at address A000 0000h (CE2). The QDMA brings 4 frames of 1K halfwords from their locations in RAM to internal data memory beginning at 0000 2000h. The index value required is ELEIDX = F × S = 4 × 2 = 8. Since separate QDMA transfer requests are submitted for each frame, the QDMA parameters only use ELEIDX.
Page 59: 1.18.4 Peripheral Servicing Examples
Transfer Examples To summarize, the CPU performs four writes to configure the channel options, the source address, the count, and the destination address. The CPU then performs a write to the channel index pseudo-register (or the register is still not configured) to submit the transfer request for the first frame.
Page 60: Servicing Incoming Mcbsp Data Example Diagram
Transfer Examples 1.18.4.1 Non-bursting Peripherals Non-bursting peripherals include the on-chip multichannel buffered serial port (McBSP) and many external devices, such as codecs. Regardless of the peripheral, the EDMA channel configuration is the same. The on-chip McBSP is the most commonly-used peripheral in a C6000 DSP system.
Page 61: Servicing Incoming Mcbsp Data Example Edma Parameters Content
Transfer Examples To transfer the incoming data stream to its proper location in L2 memory, the EDMA channel must be set up for a 1D-to-1D transfer with element synchro- nization (FS = 0). Since an event (REVT0) is generated for every word as it arrives, it is necessary to have the EDMA issue the transfer request for each element individually.
Page 62: Transfer With Frame Synchronization (Fs = 1)
Transfer Examples 1.18.4.2 Bursting Peripherals Higher bandwidth applications require that multiple data elements be presented to the DSP for every sync event. This frame of data can either be from multiple sources that are working simultaneously or from a single high-throughput peripheral that streams data to/from the DSP.
Page 63: Servicing Peripheral Bursts Example Edma Parameters Content
Transfer Examples Figure 1−21. Servicing Peripheral Bursts Example EDMA Parameters Content (a) EDMA Parameters Parameter Contents Parameter 28A0 0000h EDMA Channel Options Parameter (OPT) 9001 0000h EDMA Channel Source Address (SRC) 01DFh 0280h EDMA Channel Transfer Count (CNT) A000 0000h EDMA Channel Destination Address (DST) 0500h Don’t care...
Page 64: Servicing Continuous Mcbsp Data Example Diagram
Transfer Examples 1.18.4.3 Continuous Operation Configuring an EDMA channel to receive a single frame of data can be useful, and is applicable to some systems. A majority of the time, however, data is going to be continuously transmitted and received throughout the entire opera- tion of the DSP.
Page 65: Servicing Continuous Mcbsp Data Example Edma Parameters Content
Transfer Examples Figure 1−23. Servicing Continuous McBSP Data Example EDMA Parameters Content (a) EDMA Parameters for Receive Channel 13 Parameter Contents Parameter 3060 0002h EDMA Channel Options Parameter (OPT) 3000 0000h EDMA Channel Source Address (SRC) 007Fh 0002h EDMA Channel Transfer Count (CNT) 0000 2000h EDMA Channel Destination Address (DST) FF81h...
Page 66: Servicing Continuous Mcbsp Data Example Edma Reload Parameters Content
Transfer Examples Figure 1−24. Servicing Continuous McBSP Data Example EDMA Reload Parameters Content (a) EDMA Reload Parameters for Receive Channel 13 (Address 01A0 0198h) Parameter Contents Parameter 3060 0002h EDMA Channel Options Parameter (OPT) 3000 0000h EDMA Channel Source Address (SRC) 007Fh 0002h EDMA Channel Transfer Count (CNT)
Page 67 Transfer Examples The parameter table must keep track of the element count within the frame since each element is sent individually (FS = 0). It is required that an element count reload be provided in the parameter set. This value is reloaded to the element count field every time the element count reaches 0.
Page 68: Ping-Pong Buffering For Mcbsp Data Example Diagram
Transfer Examples Each channel has two parameter sets, ping and pong. The EDMA channel is initially loaded with the ping parameters (Figure 1−26). The link address for the ping entry is set to the PaRAM offset of the pong parameter set (Figure 1−27). The link address for the pong entry is set to the PaRAM offset of the ping parameter set (Figure 1−28).
Page 69: Ping-Pong Buffering Example Edma Parameters Content
Transfer Examples Figure 1−26. Ping-Pong Buffering Example EDMA Parameters Content (a) EDMA Parameters for Channel 13 Parameter Contents Parameter 307D 0002h EDMA Channel Options Parameter (OPT) 3000 0000h EDMA Channel Source Address (SRC) 007Fh 0002h EDMA Channel Transfer Count (CNT) 0000 2000h EDMA Channel Destination Address (DST) FF81h...
Page 70: Ping-Pong Buffering Example Edma Pong Parameters Content
Transfer Examples Figure 1−27. Ping-Pong Buffering Example EDMA Pong Parameters Content (a) EDMA Pong Parameters for Channel 13 at Address 01A0 01B0h Parameter Contents Parameter 307D 0002h EDMA Channel Options Parameter (OPT) 3000 0000h EDMA Channel Source Address (SRC) 007Fh 0002h EDMA Channel Transfer Count (CNT) 0000 2200h...
Page 71: Ping-Pong Buffering Example Edma Ping Parameters Content
Transfer Examples Figure 1−28. Ping-Pong Buffering Example EDMA Ping Parameters Content (a) EDMA Ping Parameters for Channel 13 at Address 01A0 01C8h Parameter Contents Parameter 307D 0002h EDMA Channel Options Parameter (OPT) 3000 0000h EDMA Channel Source Address (SRC) 007Fh 0002h EDMA Channel Transfer Count (CNT) 0000 2000h...
Page 72: 1.18.5 Transfer Chaining Examples
Transfer Examples 1.18.5 Transfer Chaining Examples The following examples explain the alternate transfer complete chaining func- tion in detail. 1.18.5.1 Servicing Input/Output FIFOs with a Single Event Most common systems for ADSL, networking, and video applications require the use of a pair of external FIFOs that must be serviced at the same rate. One FIFO buffers data input, and the other buffers data output.
Page 73: Alternate Transfer Complete Chaining Example
Transfer Examples Figure 1−29. Alternate Transfer Complete Chaining Example HARDWIRED EVENT CHAINED EVENT (tied to EXT_INT7, event 7) (event 16) event 7 Alternate Transfer Complete † Channel 7, Array 0 Channel 16, Array 0 event 7 Alternate † Transfer Complete Channel 7, Array 1 Channel 16, Array 1 event 7...
Page 74: Single Large Block Data Transfer Example
Transfer Examples 1.18.5.2 Breaking up Large Transfers with ATCC Another feature of the alternate transfer completion code (ATCC) is for break- ing up large transfers. A large transfer may lock out other transfers of the same priority level (section 4.5) for the duration of the transfer. For example, a large transfer with high priority from the internal memory to the external memory using the EMIF may lock out other EDMA transfers on the high priority queue.
Page 75: Smaller Packet Data Transfers Example
Transfer Examples The CPU starts the EDMA transfer by writing to the appropriate bit of the event set register (ESRL[8]). The EDMA transfers the first 1 Kbyte array. Upon completion of the first array (an intermediate transfer), alternate transfer complete code chaining generates a synchronization event to channel 8, a value specified by the ATCC field.
Page 76 Transfer Examples 1-64 Overview SPRU234B...
Page 77: Topic Page
Chapter 2 EDMA Transfer Controller This chapter describes the EDMA transfer controller (EDMATC) that handles all data transfers between the level-two (L2) cache/memory controller and the device peripherals on the C621x/C671x/C64x DSP. These data transfers include EDMA channel controller transfers, cache accesses to/from EMIF range, noncacheable memory accesses, and master peripheral accesses.
Page 78 EDMA Transfer Controller Performance 2.1 EDMA Transfer Controller Performance EDMA bandwidth is fully utilized when performing burst transfer, which is obtained if and only if the EDMA transfer is configured as follows: Transfer/synchronization type array-/frame-/block-synchronized transfer (not element-synchronized, see section 1.9.1) Element size is 32-bit (ESIZE = 00b) Addressing mode is increment, decrement, or fixed (not indexed, SUM or DUM = 00/01/10b in the options parameter)
Page 79: Edma Transfer Request Block Diagram
Transfer Request Submission 2.2 Transfer Request Submission 2.2.1 Request Chain All transfer requestors to the EDMA are connected to the transfer request chain, as shown in Figure 2−1. A transfer request, once submitted, shifts through the chain to the transfer crossbar (TC), where it is prioritized and processed.
Page 80: Cache Controller Data Transfers-C621X/C671X Dsp
Transfer Request Submission L2 Controller Transfer Requests 2.2.1.1 The L2 controller submits all transfer requests for cache servicing, for access- ing noncacheable memory, and for QDMA transfers. See the Two-Level Internal Memory Reference Guides (SPRU609 and SPRU610) for details on the cacheability of memory.
Page 81 Transfer Request Submission HPI/PCI Transfer Requests 2.2.1.2 The HPI/PCI automatically generates transfer requests to service host activity. For C621x/C671x DSP, these transfer request submissions are submitted only with a high priority and are invisible. For C64x DSP, by default HPI/PCI transfer requests are submitted with medium priority, but request priority can be programmed to any of the four priority levels by setting the PRI field in the transfer request control register (TRCTL) to the appropriate value.
Page 82: Address Generation/Transfer Logic Block Diagram
Transfer Request Submission 2.2.3 Address Generation/Transfer Logic The address generation/transfer logic block, shown in Figure 2−2, controls the transferring of data by the EDMA. Each priority queue has one register set, which monitors the progress of a transfer. Within the register set for a particular queue, the current source address, destination address, and count are main- tained for a transfer.
Page 83 Chapter 3 TMS320C621x/C671x EDMA This chapter describes the operation and registers of the EDMA controller in the TMS320C621x/C671x DSP. This chapter also describes the quick DMA (QDMA) registers that the CPU uses for fast data requests. For operation and registers unique to the TMS320C64x™ EDMA, see Chapter 4. Topic Page Event Service Priority...
Page 84: Parameter Ram Overview
Event Service Priority Event Service Priority / Parameter RAM (PaRAM) 3.1 Event Service Priority The EDMA event register (ER) captures up to 16 events; therefore, it is possible for events to occur simultaneously on the EDMA event inputs. For events arriving simultaneously, the channel with the highest event number submits its transfer request first.
Page 85: Edma Parameter Ram Contents-C621X/C671X Dsp
Parameter RAM (PaRAM) Table 3−1. EDMA Parameter RAM Contents—C621x/C671x DSP Address Parameters 01A0 0000h to 01A0 0017h Parameters for event 0 (6 words) 01A0 0018h to 01A0 002Fh Parameters for event 1 (6 words) 01A0 0030h to 01A0 0047h Parameters for event 2 (6 words) 01A0 0048h to 01A0 005Fh Parameters for event 3 (6 words) 01A0 0060h to 01A0 0077h...
Page 86: Edma Channel Parameter Entries For Each Edma Event-C621X/C671X Dsp
Parameter RAM (PaRAM) Figure 3−1. EDMA Channel Parameter Entries for Each EDMA Event—C621x/C671x DSP EDMA parameter Byte 0 EDMA Channel Options Parameter (OPT) Byte 4 EDMA Channel Source Address (SRC) Byte 8 Array/frame count (FRMCNT) Element count (ELECNT) Byte 12 EDMA Channel Destination Address (DST) Byte 16 Array/frame index (FRMIDX)
Page 87: Chaining Edma Channels
Chaining EDMA Channels by an Event 3.3 Chaining EDMA Channels by an Event See section 1.13 for an overview of chaining. Four of the user-specified 4-bit transfer complete codes (TCC values 8, 9, 10, and 11) can be used to trigger another EDMA channel transfer.
Page 88: Programmable Priority Levels For Data Requests-C621X/C671X Dsp
EDMA Transfer Controller Priority 3.4 EDMA Transfer Controller Priority The EDMA channels have programmable priority. The PRI bits in the channel options parameter (OPT) specify the priority levels. The highest priority available is level 0 (urgent priority), which is not supported for EDMA channel controller transfer requests.
Page 89 EDMA Transfer Controller Priority 3.4.1.1 Interaction Between Requestors Each requestor individually tracks its queue allocation usage. Therefore, when a given requestor exceeds its allocation, only that requestor is impacted, as defined in the following sections. Note that L2 and QDMA are considered a single requestor.
Page 90: Edma Control Registers-C621X/C671X Dsp
EDMA Control Registers 3.5 EDMA Control Registers Each of the 16 channels in the EDMA has a specific synchronization event associated with it. These events trigger the data transfer associated with that channel. The list of control registers that perform various processing of events is shown in Table 3−5.
Page 91: Edma Event Selector Register 0 (Esel0)
EDMA Control Registers Figure 3−2. EDMA Event Selector Register 0 (ESEL0) 30 29 24 23 22 21 Reserved EVTSEL3 Reserved EVTSEL2 R/W-03h R/W-02h 14 13 Reserved EVTSEL1 Reserved EVTSEL0 R/W-01h R/W-0 Legend: R = Read only, R/W = Read/Write; -n = value after reset Table 3−6.
Page 92: Edma Event Selector Register 1 (Esel1)
EDMA Control Registers Figure 3−3. EDMA Event Selector Register 1 (ESEL1) 30 29 24 23 22 21 Reserved EVTSEL7 Reserved EVTSEL6 R/W-07h R/W-06h 14 13 Reserved EVTSEL5 Reserved EVTSEL4 R/W-05h R/W-04h Legend: R = Read only, R/W = Read/Write; -n = value after reset Table 3−7.
Page 93: Edma Event Selector Register 3 (Esel3)
EDMA Control Registers Figure 3−4. EDMA Event Selector Register 3 (ESEL3) 30 29 24 23 22 21 Reserved EVTSEL15 Reserved EVTSEL14 R/W-0Fh R/W-0Eh 14 13 Reserved EVTSEL13 Reserved EVTSEL12 R/W-0Dh R/W-0Ch Legend: R = Read only, R/W = Read/Write; -n = value after reset Table 3−8.
Page 94: Default Edma Event For Edma Channel-C6713 Dsp
EDMA Control Registers Table 3−9. Default EDMA Event for EDMA Channel—C6713 DSP EDMA Event Selector Register Default EDMA Event Selector Value (Binary) EDMA Channel Bits Field Default EDMA Event ESEL0[5−0] EVTSEL0 00 0000 DSPINT ESEL0[13−8] EVTSEL1 00 0001 TINT0 ESEL0[21−16] EVTSEL2 00 0010 TINT1...
Page 95 EDMA Control Registers Table 3−10. EDMA Event for EDMA Event Selector Value—C6713 DSP (Continued) EDMA Event Selector Value (Binary) EDMA Event Module 00 1011 GPINT3 GPIO 00 1100 XEVT0 McBSP0 00 1101 REVT0 McBSP0 00 1110 XEVT1 McBSP1 00 1111 REVT1 McBSP1 01 0000−01 1111...
Page 96: Priority Queue Status Register (Pqsr) Field Descriptions
EDMA Control Registers 3.5.2 Priority Queue Status Register (PQSR) The priority queue status register (PQSR) indicates whether the transfer controller is empty on each priority level. The PQSR is shown in Figure 3−5 and described in Table 3−11. The priority queue status (PQ) bit provides the status of the queues as well as any active transfers.
Page 97: Edma Channel Interrupt Pending Register (Cipr) Field Descriptions
EDMA Control Registers 3.5.3 EDMA Channel Interrupt Pending Register (CIPR) The EDMA channel interrupt pending register (CIPR) is shown in Figure 3−6 and described in Table 3−12. Figure 3−6. EDMA Channel Interrupt Pending Register (CIPR) Reserved CIP15 CIP14 CIP13 CIP12 CIP11 CIP10 CIP9...
Page 98: Edma Channel Interrupt Enable Register (Cier) Field Descriptions
EDMA Control Registers 3.5.4 EDMA Channel Interrupt Enable Register (CIER) The EDMA channel interrupt enable register (CIER) is shown in Figure 3−7 and described in Table 3−13. Figure 3−7. EDMA Channel Interrupt Enable Register (CIER) Reserved CIE15 CIE14 CIE13 CIE12 CIE11 CIE10 CIE9...
Page 99: Edma Channel Chain Enable Register (Ccer) Field Descriptions
EDMA Control Registers 3.5.5 EDMA Channel Chain Enable Register (CCER) The EDMA channel chain enable register (CCER) is shown in Figure 3−8 and described in Table 3−14. Figure 3−8. EDMA Channel Chain Enable Register (CCER) Reserved Reserved CCE11 CCE10 CCE9 CCE8 R/W-0 R/W-0...
Page 100: Edma Event Register (Er) Field Descriptions
EDMA Control Registers 3.5.6 EDMA Event Register (ER) The event register (ER) captures all events, even when the events are disabled. The ER is shown in Figure 3−9 and described in Table 3−15. Section 1.5 describes the type of synchronization events and the EDMA channels associated with each of them.
Page 101: Edma Event Enable Register (Eer) Field Descriptions
EDMA Control Registers 3.5.7 EDMA Event Enable Register (EER) Each event in the event register (ER) can be enabled or disabled using the event enable register (EER). Any of the event bits in EER can be set to 1 to enable that corresponding event or can be cleared to 0 to disable that corresponding event.
Page 102: Edma Event Clear Register (Ecr)
EDMA Control Registers 3.5.8 Event Clear Register (ECR) Once an event has been posted in the event register (ER), it can clear the event in two ways. If the event is enabled in the event enable register (EER) and the EDMA submits a transfer request for that event, it clears the corre- sponding event bit in ER.
Page 103: Edma Event Set Register (Esr)
EDMA Control Registers 3.5.9 EDMA Event Set Register (ESR) The CPU can set events using the event set register (ESR), shown in Figure 3−12 and described in Table 3−18. Writing a 1 to one of the event bits causes a transfer request to be submitted. The event does not have to be enabled.
Page 104: Edma Parameter Entries-C621X/C671X Dsp
EDMA Channel Parameter Entries 3.6 EDMA Channel Parameter Entries See section 1.3 for an overview of the parameter RAM (PaRAM). Each param- eter set of an EDMA channel is organized into six 32-bit words or 24 bytes as listed in Table 3−19. See Table 3−1 (page 3-3) for the memory address of these registers.
Page 105: Edma Channel Options Parameter (Opt) Field Descriptions
EDMA Channel Parameter Entries Table 3−20. EDMA Channel Options Parameter (OPT) Field Descriptions field † symval † Value Description 31−29 PRI OF(value) 0−7h Priority levels for EDMA events. DEFAULT Reserved. This level is reserved only for L2 requests and not valid for EDMA channel or QDMA transfer requests.
Page 106 EDMA Channel Parameter Entries Table 3−20. EDMA Channel Options Parameter (OPT) Field Descriptions (Continued) field † symval † Value Description 22−21 DUM OF(value) 0−3h Destination address update mode. DEFAULT Fixed address mode. No destination address modification. NONE Destination address increment depends on the 2DD and FS bits. Destination address decrement depends on the 2DD and FS bits.
Page 107: Edma Channel Source Address Parameter (Src) Field Descriptions
EDMA Channel Parameter Entries Table 3−20. EDMA Channel Options Parameter (OPT) Field Descriptions (Continued) field † symval † Value Description OF(value) Frame synchronization. DEFAULT Channel is element/array synchronized. Channel is frame synchronized. The relevant event for a given EDMA channel is used to synchronize a frame. †...
Page 108: Edma Channel Transfer Count Parameter (Cnt) Field Descriptions
EDMA Channel Parameter Entries 3.6.3 EDMA Channel Transfer Count Parameter (CNT) The EDMA channel transfer count parameter (CNT) in the EDMA parameter entries specifies the frame/array count and element count. The CNT is shown in Figure 3−15 and described in Table 3−22. The frame/array count (FRMCNT) is a 16-bit unsigned value plus 1 that speci- fies the number of frames in a 1D block or the number of arrays in a 2D block.
Page 109: Edma Channel Destination Address Parameter (Dst) Field Descriptions
EDMA Channel Parameter Entries 3.6.4 EDMA Channel Destination Address Parameter (DST) The EDMA channel destination address parameter (DST) in the EDMA parameter entries specifies the starting byte address of the destination. The DST is shown in Figure 3−16 and described in Table 3−23. Use the DUM bits in the EDMA channel options parameter (OPT) to modify the destination address.
Page 110: Edma Channel Index Parameter (Idx) Field Descriptions
EDMA Channel Parameter Entries 3.6.5 EDMA Channel Index Parameter (IDX) The EDMA channel index parameter (IDX) in the EDMA parameter entries specifies the frame/array index and element index used for address modifica- tion. The EDMA is shown in Figure 3−17 and described in Table 3−24. The EDMA uses the indexes for address updates, depending on the type of trans- fer (1D or 2D) selected, and the FS, SUM, and DUM bits in the EDMA channel options parameter (OPT).
Page 111 EDMA Channel Parameter Entries 3.6.6 EDMA Channel Count Reload/Link Address Parameter (RLD) The EDMA channel count reload/link address parameter (RLD) in the EDMA parameter entries specifies the value used to reload the element count field and the link address. The RLD is shown in Figure 3−18 and described in Table 3−25.
Page 112: Edma Channel Count Reload/Link Address Parameter (Rld) Field Descriptions
EDMA Channel Parameter Entries Figure 3−18. EDMA Channel Count Reload/Link Address Parameter (RLD) 16 15 ELERLD LINK R/W-0 R/W-0 Legend: R/W = Read/Write; -n = value after reset Table 3−25. EDMA Channel Count Reload/Link Address Parameter (RLD) Field Descriptions field †...
Page 113 QDMA Registers 3.7 QDMA Registers Since the QDMA is used for quick, one-time transfers it does not have the capability to reload a count or link. The count reload/link address register is therefore not available to the QDMA. The QDMA registers are not updated during or after a transfer by the hardware, they retain the submitted values.
Page 114 QDMA Registers Figure 3−19. QDMA Registers (a) QDMA registers Address QDMA register 0200 0000h QDMA Channel Options QOPT 0200 0004h QDMA Channel Source Address (SRC) QSRC 0200 0008h Array/frame count (FRMCNT) Element count (ELECNT) QCNT 0200 000Ch QDMA Channel Destination Address (DST) QDST 0200 0010h Array/frame index (FRMIDX)
Page 115 QDMA Registers 3.7.2 QDMA Channel Source Address Register (QSRC, QSSRC) Figure 3−21. QDMA Channel Source Address Register (QSRC) Source Address (SRC) Legend: W= Write only; -n = value after reset 3.7.3 QDMA Channel Transfer Count Register (QCNT, QSCNT) Figure 3−22. QDMA Channel Transfer Count Register (QCNT) 16 15 FRMCNT ELECNT...
Page 116 QDMA Registers SPRU234B 3-34 TMS320C621x/C671x EDMA...
Page 117 Chapter 4 TMS320C64x EDMA This chapter describes the operation and registers of the EDMA controller in the TMS320C64x™ DSP. This chapter also describes the quick DMA (QDMA) registers that the CPU uses for fast data requests. For operation and registers unique to the TMS320C621x/C671x EDMA, see Chapter 3.
Page 118: 4.1 Event Service Priority
Event Service Priority Event Service Priority / Parameter RAM (PaRAM) 4.1 Event Service Priority The EDMA event registers (ERL and ERH) capture up to 64 events; therefore, it is possible for events to occur simultaneously on the EDMA event inputs. For events arriving simultaneously, the channel with the highest event number submits its transfer request first.
Page 119: Edma Parameter Ram Contents-C64X Dsp
Parameter RAM (PaRAM) Table 4−1. EDMA Parameter RAM Contents—C64x DSP Address Parameters 01A0 0000h to 01A0 0017h Parameters for event 0 (6 words) 01A0 0018h to 01A0 002Fh Parameters for event 1 (6 words) 01A0 0030h to 01A0 0047h Parameters for event 2 (6 words) 01A0 0048h to 01A0 005Fh Parameters for event 3 (6 words) 01A0 0060h to 01A0 0077h...
Page 120: Edma Channel Parameter Entries For Each Edma Event-C64X Dsp
Parameter RAM (PaRAM) Table 4−1. EDMA Parameter RAM Contents—C64x DSP (Continued) Address Parameters 01A0 07F8h to 01A0 07FFh Scratch pad area (2 words) †‡ 01A0 07F8h to 01A0 080Fh Reload/link parameter for Event 21 (6 words) ‡ 01A0 0810h to 01A0 0827h Reload/link parameter for Event 22 (6 words) ‡...
Page 121: Edma Channel Parameter Descriptions-C64X Dsp
Parameter RAM (PaRAM) Table 4−2. EDMA Channel Parameter Descriptions—C64x DSP Offset As defined for… address 1D transfer 2D transfer (bytes) Acronym Parameter Section Channel options Transfer configuration options. 4.8.1 Channel source address The address from which data is transferred. 4.8.2 †...
Page 122 Chaining EDMA Channels With a Single Event 4.3 Chaining EDMA Channels With a Single Event See section 1.13 for an overview of chaining. Any of the 64 transfer completion codes of the EDMA can trigger another channel transfer. To enable the EDMA controller to chain channels by way of a single event, you must set the TCINT bit to 1.
Page 123 2 EMIF bus cycles. When PDT is enabled, data is driven by the external source directly, and written to the external destination in the same data bus trans- action. See TMS320C6000 DSP External Memory Interface (EMIF) Refer- ence Guide (SPRU266) for a detailed description of PDT.
Page 124: Programmable Priority Levels For Data Requests-C64X Dsp
EDMA Transfer Controller Priority 4.5 EDMA Transfer Controller Priority The EDMA channels have programmable priority. The PRI bits in the channel options parameter (OPT) specify the priority levels. The highest priority avail- able is level 0 (urgent priority). Table 4−3 shows the available priority levels for the different requestors.
Page 125: Transfer Request Queues-C6416 Dsp
EDMA Transfer Controller Priority 4.5.1 Transfer Controller Transfer Request Queue Length The C64x EDMA transfer controller has four transfer request queues, Q0, Q1, Q2, and Q3, with a fixed length of 16 transfer requests per queue. Table 4−4 shows the transfer request queues for the C6416 device. Refer to the device- specific data manual for the transfer request queues of other devices.
Page 126 EDMA Transfer Controller Priority 4.5.1.1 Interaction Between Requestors Each requestor individually tracks its queue allocation usage, which can be user programmed. Therefore, when a given requestor exceeds its allocation, only that requestor is impacted, as defined in the following sections. Note that L2 and QDMA are considered a single requestor.
Page 127 EDMA Transfer Controller Priority For priority levels other than the one used for cache requests, QDMA requests are the only request type for L2 transfer request submissions. The queue allocation for QDMA requests is limited to the value programmed into the L2ALLOCn registers (where n! = CCFG.PRI).
Page 128: L2 Edma Access Control Register (Edmaweight) Field Descriptions
EDMA Access Into L2 Control 4.6 EDMA Access Into L2 Control The C64x DSP incorporates an L2 EDMA access control register (EDMAWEIGHT), located in the L2 cache register memory map, that controls the relative priority weighting of EDMA versus L1D access into L2. EDMAWEIGHT gives EDMA accesses a temporary boost in priority by limiting the amount of time L1D blocks EDMA access to L2.
Page 129: Edma Control Registers-C64X Dsp
EDMA Control Registers 4.7 EDMA Control Registers Each of the 64 channels in the EDMA has a specific synchronization event associated with it. These events trigger the data transfer associated with that channel. The list of control registers that perform various processing of events is shown in Table 4−6.
Page 130: Priority Queue Status Register (Pqsr)
EDMA Control Registers 4.7.1 Priority Queue Status Register (PQSR) The priority queue status register (PQSR) indicates whether the transfer controller is empty on each priority level. The PQSR is shown in Figure 4−3 and described in Table 4−7. The priority queue status (PQ) bit provides the status of the queues as well as any active transfers.
Page 131: Priority Queue Allocation Register (Pqar)
EDMA Control Registers 4.7.2 Priority Queue Allocation Registers (PQAR0−3) The C64x DSP has four transfer request queues: Q0, Q1, Q2, and Q3. The different priority level transfer requests (PRI field in the EDMA channel options parameter) are sorted into Q0, Q1, Q2, and Q3. The queue length available to EDMA requests is programmable using the priority queue allocation registers (PQARn).
Page 132: Edma Channel Interrupt Pending Low Register (Ciprl) Field Descriptions
EDMA Control Registers 4.7.3 EDMA Channel Interrupt Pending Registers (CIPRL, CIPRH) The EDMA channel interrupt pending registers (CIPRL and CIPRH) are shown in Figure 4−5 and Figure 4−6 and described in Table 4−9 and Table 4−10. 4.7.3.1 EDMA Channel Interrupt Pending Low Register (CIPRL) Figure 4−5.
Page 133: Edma Channel Interrupt Pending High Register (Ciprh)
EDMA Control Registers 4.7.3.2 EDMA Channel Interrupt Pending High Register (CIPRH) Figure 4−6. EDMA Channel Interrupt Pending High Register (CIPRH) CIP63 CIP62 CIP61 CIP60 CIP59 CIP58 CIP57 CIP56 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CIP55 CIP54 CIP53 CIP52 CIP51 CIP50 CIP49...
Page 134: Edma Channel Interrupt Enable Low Register (Cierl) Field Descriptions
EDMA Control Registers 4.7.4 EDMA Channel Interrupt Enable Registers (CIERL, CIERH) The EDMA channel interrupt enable registers (CIERL and CIERH) are shown in Figure 4−7 and Figure 4−8 and described in Table 4−11 and Table 4−12. 4.7.4.1 EDMA Channel Interrupt Enable Low Register (CIERL) Figure 4−7.
Page 135: Edma Channel Interrupt Enable High Register (Cierh)
EDMA Control Registers 4.7.4.2 EDMA Channel Interrupt Enable High Register (CIERH) Figure 4−8. EDMA Channel Interrupt Enable High Register (CIERH) CIE63 CIE62 CIE61 CIE60 CIE59 CIE58 CIE57 CIE56 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CIE55 CIE54 CIE53 CIE52 CIE51 CIE50 CIE49...
Page 136: Edma Channel Chain Enable Low Register (Ccerl) Field Descriptions
EDMA Control Registers 4.7.5 EDMA Channel Chain Enable Registers (CCERL, CCERH) The EDMA channel chain enable registers (CCERL and CCERH) are shown in Figure 4−9 and Figure 4−10 and described in Table 4−13 and Table 4−14. 4.7.5.1 EDMA Channel Chain Enable Low Register (CCERL) Figure 4−9.
Page 137: Edma Channel Chain Enable High Register (Ccerh)
EDMA Control Registers 4.7.5.2 EDMA Channel Chain Enable High Register (CCERH) Figure 4−10. EDMA Channel Chain Enable High Register (CCERH) CCE63 CCE62 CCE61 CCE60 CCE59 CCE58 CCE57 CCE56 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CCE55 CCE54 CCE53 CCE52 CCE51 CCE50 CCE49...
Page 138: Edma Event Low Register (Erl)
EDMA Control Registers 4.7.6 EDMA Event Registers (ERL, ERH) All events are captured in the event low register (ERL) and event high register (ERH) for the 64 channels, even when the events are disabled. The ERL is shown in Figure 4−11 and described in Table 4−15, and the ERH is shown in Figure 4−12 and described in Table 4−16.
Page 139: Edma Event High Register (Erh)
EDMA Control Registers 4.7.6.2 EDMA Event High Register (ERH) Figure 4−12. EDMA Event High Register (ERH) EVT63 EVT62 EVT61 EVT60 EVT59 EVT58 EVT57 EVT56 EVT55 EVT54 EVT53 EVT52 EVT51 EVT50 EVT49 EVT48 EVT47 EVT46 EVT45 EVT44 EVT43 EVT42 EVT41 EVT40 EVT39 EVT38 EVT37...
Page 140 EDMA Control Registers 4.7.7 EDMA Event Enable Registers (EERL, EERH) Each event in the event registers (ERL and ERH) can be enabled or disabled using the event enable registers (EERL and EERH). Any of the event bits in EER can be set to 1 to enable that corresponding event or can be cleared to 0 to disable that corresponding event.
Page 141: Edma Event Enable Low Register (Eerl)
EDMA Control Registers Table 4−17. EDMA Event Enable Low Register (EERL) Field Descriptions Field symval † Value Description 31−0 OF(value) 0−FFFF FFFFh Event 0−31 enable. Used to enable or disable an event. DEFAULT EDMA event is not enabled. − EDMA event is enabled. †...
Page 142 EDMA Control Registers 4.7.8 Event Clear Registers (ECRL, ECRH) Once an event has been posted in the event registers (ERL and ERH), the event can be cleared in two ways. If the event is enabled in the event enable registers (EERL and EERH) and the EDMA submits a transfer request for that event, it clears the corresponding event bit in the event register.
Page 143: Edma Event Clear Low Register (Ecrl)
EDMA Control Registers Table 4−19. EDMA Event Clear Low Register (ECRL) Field Descriptions Field symval † Value Description 31−0 OF(value) 0−FFFF FFFFh Event 0−31 clear. Any of the event bits can be set to 1 to clear that event; a write of 0 has no effect. DEFAULT No effect.
Page 144 EDMA Control Registers 4.7.9 Event Set Registers (ESRL, ESRH) The CPU can set events using the event set registers (ESRL and ESRH). The ESRL is shown in Figure 4−17 and described in Table 4−21, and the ESRH is shown in Figure 4−18 and described in Table 4−22. Writing a 1 to one of the event bits causes a transfer request to be submitted.
Page 145: Edma Event Set Low Register (Esrl)
EDMA Control Registers Table 4−21. EDMA Event Set Low Register (ESRL) Field Descriptions Field symval † Value Description 31−0 OF(value) 0−FFFF FFFFh Event 0−31 set. Any of the event bits can be set to 1 to set the corresponding bit in the event low register (ERL); a write of 0 has no effect.
Page 146: Edma Event Polarity Low Register (Eprl)
EDMA Control Registers 4.7.10 Event Polarity Registers (EPRL, EPRH) An event is signaled to the EDMA controller by a positive-edge triggering (low- to-high transition) on one of its event inputs. The event polarity can be changed to a falling-edge triggering (high-to-low transition) by setting the corresponding bit in the event polarity low register (EPRL) or event polarity high register (EPRH).
Page 147: Edma Event Polarity High Register (Eprh)
EDMA Control Registers 4.7.10.2 EDMA Event Polarity High Register (EPRH) Figure 4−20. EDMA Event Polarity High Register (EPRH) EP63 EP62 EP61 EP60 EP59 EP58 EP57 EP56 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EP55 EP54 EP53 EP52 EP51 EP50 EP49 EP48 R/W-0...
Page 148: Edma Channel Options Parameter (Opt)
EDMA Channel Parameter Entries 4.8 EDMA Channel Parameter Entries See section 1.3 for an overview of the parameter RAM (PaRAM). Each param- eter set of an EDMA channel is organized into six 32-bit words or 24 bytes as listed in Table 4−25. See Table 4−1 (page 4-3) for the memory address of these registers.
Page 149: Edma Channel Options Parameter (Opt)
EDMA Channel Parameter Entries Figure 4−21. EDMA Channel Options Parameter (OPT) 29 28 25 24 22 21 ESIZE TCINT R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x 14 13 † † † Rsvd TCCM ATCINT Rsvd ATCC Rsvd PDTS PDTD LINK R/W-x R/W-x...
Page 150 EDMA Channel Parameter Entries Table 4−26. EDMA Channel Options Parameter (OPT) Field Descriptions (Continued) field † symval † Value Description 25−24 SUM OF(value) 0−3h Source address update mode. DEFAULT Fixed address mode. No source address modification. NONE Source address increment depends on the 2DS and FS bits. Source address decrement depends on the 2DS and FS bits.
Page 151 EDMA Channel Parameter Entries Table 4−26. EDMA Channel Options Parameter (OPT) Field Descriptions (Continued) field † symval † Value Description 19−16 TCC OF(value) 0−Fh Transfer complete code. This 4-bit value is used to set the bit in the EDMA channel interrupt pending register (CIPR[TCC] bit) provided.
Page 152 EDMA Channel Parameter Entries Table 4−26. EDMA Channel Options Parameter (OPT) Field Descriptions (Continued) field † symval † Value Description PDTS OF(value) Peripheral device transfer (PDT) mode for source. DEFAULT PDT read is disabled. DISABLE ENABLE PDT read is enabled. PDTD OF(value) Peripheral device transfer (PDT) mode for destination.
Page 153: Edma Channel Source Address Parameter (Src)
EDMA Channel Parameter Entries 4.8.2 EDMA Channel Source Address Parameter (SRC) The EDMA channel source address parameter (SRC) in the EDMA parameter entries specifies the starting byte address of the source. The SRC is shown in Figure 4−22 and described in Table 4−27. Use the SUM bits in the EDMA channel options parameter (OPT) to modify the source address.
Page 154: Edma Channel Transfer Count Parameter (Cnt)
EDMA Channel Parameter Entries 4.8.3 EDMA Channel Transfer Count Parameter (CNT) The EDMA channel transfer count parameter (CNT) in the EDMA parameter entries specifies the frame/array count and element count. The CNT is shown in Figure 4−23 and described in Table 4−28. The frame/array count (FRMCNT) is a 16-bit unsigned value plus 1 that speci- fies the number of frames in a 1D block or the number of arrays in a 2D block.
Page 155: Edma Channel Destination Address Parameter (Dst)
EDMA Channel Parameter Entries 4.8.4 EDMA Channel Destination Address Parameter (DST) The EDMA channel destination address parameter (DST) in the EDMA parameter entries specifies the starting byte address of the destination. The DST is shown in Figure 4−24 and described in Table 4−29. Use the DUM bits in the EDMA channel options parameter (OPT) to modify the destination address.
Page 156: Edma Channel Index Parameter (Idx)
EDMA Channel Parameter Entries 4.8.5 EDMA Channel Index Parameter (IDX) The EDMA channel index parameter (IDX) in the EDMA parameter entries specifies the frame/array index and element index used for address modifica- tion. The EDMA is shown in Figure 4−25 and described in Table 4−30. The EDMA uses the indexes for address updates, depending on the type of trans- fer (1D or 2D) selected, and the FS, SUM, and DUM bits in the EDMA channel options parameter (OPT).
Page 157: Edma Channel Count Reload/Link Address Parameter (Rld)
EDMA Channel Parameter Entries 4.8.6 EDMA Channel Count Reload/Link Address Parameter (RLD) The EDMA channel count reload/link address parameter (RLD) in the EDMA parameter entries specifies the value used to reload the element count field and the link address. The RLD is shown in Figure 4−26 and described in Table 4−31.
Page 158: Edma Channel Count Reload/Link Address Parameter (Rld)
EDMA Channel Parameter Entries Figure 4−26. EDMA Channel Count Reload/Link Address Parameter (RLD) 16 15 ELERLD LINK R/W-0 R/W-0 Legend: R/W = Read/Write; -n = value after reset Table 4−31. EDMA Channel Count Reload/Link Address Parameter (RLD) Field Descriptions field †...
Page 159: 4.9 Qdma Registers
QDMA Registers 4.9 QDMA Registers Since the QDMA is used for quick, one-time transfers it does not have the capability to reload a count or link. The count reload/link address register is therefore not available to the QDMA. The QDMA registers are not updated during or after a transfer by the hardware, they retain the submitted values.
Page 160: Qdma Registers
QDMA Registers Figure 4−27. QDMA Registers (a) QDMA registers Address QDMA register 0200 0000h QDMA Channel Options QOPT 0200 0004h QDMA Channel Source Address (SRC) QSRC 0200 0008h Array/frame count (FRMCNT) Element count (ELECNT) QCNT 0200 000Ch QDMA Channel Destination Address (DST) QDST 0200 0010h Array/frame index (FRMIDX)
Page 161 QDMA Registers 4.9.2 QDMA Channel Source Address Register (QSRC, QSSRC) Figure 4−29. QDMA Channel Source Address Register (QSRC) Source Address (SRC) R/W-0 Legend: R/W= Read/Write; -n = value after reset 4.9.3 QDMA Channel Transfer Count Register (QCNT, QSCNT) Figure 4−30. QDMA Channel Transfer Count Register (QCNT) 16 15 FRMCNT ELECNT...
Page 162 QDMA Registers SPRU234B 4-46 TMS320C64x EDMA...
Page 163 Appendix A Appendix A EDMA Transfers This appendix describes all of the different types of EDMA transfers. Topic Page Element Synchronized 1D-to-1D Transfers ..... Frame Synchronized 1D-to-1D Transfers .
Page 164: Element Synchronized (Fs = 0) 1D-To-1D Transfers
Element Synchronized 1D-to-1D Transfers A.1 Element Synchronized 1D-to-1D Transfers The possible 1D-to-1D transfers (2DS = 2DD = 0), along with the necessary parameters using element synchronization (FS = 0), are listed in Table A−1 and shown in Figure A−1 through Figure A−16. For each, only one element is transferred per synchronization event.
Page 165: Element Synchronized 1D-To-1D Transfer (Sum = 00, Dum = 00)
Element Synchronized 1D-to-1D Transfers Figure A−1. Element Synchronized 1D-to-1D Transfer (SUM = 00, DUM = 00) (a) Transfer Path Source Destination address address (b) EDMA Parameters Parameter Contents Parameter 2000 0000h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h 0004h EDMA Channel Transfer Count (CNT)
Page 166: Element Synchronized 1D-To-1D Transfer (Sum = 00, Dum = 01)
Element Synchronized 1D-to-1D Transfers Figure A−2. Element Synchronized 1D-to-1D Transfer (SUM = 00, DUM = 01) (a) Transfer Path Source Destination 0_2 0_3 0_4 1_1 1_2 1_3 address address 2_3 2_4 (b) EDMA Parameters Parameter Contents Parameter 2020 0000h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h...
Page 167: Element Synchronized 1D-To-1D Transfer (Sum = 00, Dum = 10)
Element Synchronized 1D-to-1D Transfers Figure A−3. Element Synchronized 1D-to-1D Transfer (SUM = 00, DUM = 10) (a) Transfer Path Source address 2_2 2_1 Destination address (b) EDMA Parameters Parameter Contents Parameter 2040 0000h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h 0004h...
Page 168: Element Synchronized 1D-To-1D Transfer (Sum = 00, Dum = 11)
Element Synchronized 1D-to-1D Transfers Figure A−4. Element Synchronized 1D-to-1D Transfer (SUM = 00, DUM = 11) (a) Transfer Path Source Destination address address (b) EDMA Parameters Parameter Contents Parameter 2060 0000h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h 0004h EDMA Channel Transfer Count (CNT)
Page 169: Element Synchronized 1D-To-1D Transfer (Sum = 01, Dum = 00)
Element Synchronized 1D-to-1D Transfers Figure A−5. Element Synchronized 1D-to-1D Transfer (SUM = 01, DUM = 00) (a) Transfer Path Source Destination 0_2 0_3 0_4 1_1 1_2 1_3 address address 2_3 2_4 (b) EDMA Parameters Parameter Contents Parameter 2100 0000h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h...
Page 170: Element Synchronized 1D-To-1D Transfer (Sum = 01, Dum = 01)
Element Synchronized 1D-to-1D Transfers Figure A−6. Element Synchronized 1D-to-1D Transfer (SUM = 01, DUM = 01) (a) Transfer Path Source Destination 0_1 0_2 0_2 0_3 0_4 1_1 1_2 1_3 address address 1_4 2_1 2_3 2_4 (b) EDMA Parameters Parameter Contents Parameter 2120 0000h EDMA Channel Options Parameter (OPT)
Page 171: Element Synchronized 1D-To-1D Transfer (Sum = 01, Dum = 10)
Element Synchronized 1D-to-1D Transfers Figure A−7. Element Synchronized 1D-to-1D Transfer (SUM = 01, DUM = 10) (a) Transfer Path Source address 0_1 0_2 0_3 0_4 1_1 1_2 1_3 2_3 2_4 Destination address (b) EDMA Parameters Parameter Contents Parameter 2140 0000h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC)
Page 172: Element Synchronized 1D-To-1D Transfer (Sum = 01, Dum = 11)
Element Synchronized 1D-to-1D Transfers Figure A−8. Element Synchronized 1D-to-1D Transfer (SUM = 01, DUM = 11) (a) Transfer Path Source Destination 0_1 0_2 address address 1_4 2_1 (b) EDMA Parameters Parameter Contents Parameter 2160 0000h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h...
Page 173: Element Synchronized 1D-To-1D Transfer (Sum = 10, Dum = 00)
Element Synchronized 1D-to-1D Transfers Figure A−9. Element Synchronized 1D-to-1D Transfer (SUM = 10, DUM = 00) (a) Transfer Path Destination address Source address (b) EDMA Parameters Parameter Contents Parameter 2200 0000h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h 0004h EDMA Channel Transfer Count (CNT)
Page 174: Element Synchronized 1D-To-1D Transfer (Sum = 10, Dum = 01)
Element Synchronized 1D-to-1D Transfers Figure A−10. Element Synchronized 1D-to-1D Transfer (SUM = 10, DUM = 01) (a) Transfer Path Destination 0_2 0_3 0_4 1_1 1_2 1_3 address 2_3 2_4 Source address (b) EDMA Parameters Parameter Contents Parameter 2220 0000h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h...
Page 175: Element Synchronized 1D-To-1D Transfer (Sum = 10, Dum = 10)
Element Synchronized 1D-to-1D Transfers Figure A−11. Element Synchronized 1D-to-1D Transfer (SUM = 10, DUM = 10) (a) Transfer Path 1_3 1_2 1_1 0_4 0_3 0_2 0_1 Source address Destination address (b) EDMA Parameters Parameter Contents Parameter 2240 0000h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h...
Page 176: Element Synchronized 1D-To-1D Transfer (Sum = 10, Dum = 11)
Element Synchronized 1D-to-1D Transfers Figure A−12. Element Synchronized 1D-to-1D Transfer (SUM = 10, DUM = 11) (a) Transfer Path Destination address Source address (b) EDMA Parameters Parameter Contents Parameter 2260 0000h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h 0004h EDMA Channel Transfer Count (CNT)
Page 177: Element Synchronized 1D-To-1D Transfer (Sum = 11, Dum = 00)
Element Synchronized 1D-to-1D Transfers Figure A−13. Element Synchronized 1D-to-1D Transfer (SUM = 11, DUM = 00) (a) Transfer Path Source Destination address address (b) EDMA Parameters Parameter Contents Parameter 2300 0000h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h 0004h EDMA Channel Transfer Count (CNT)
Page 178: Element Synchronized 1D-To-1D Transfer (Sum = 11, Dum = 01)
Element Synchronized 1D-to-1D Transfers Figure A−14. Element Synchronized 1D-to-1D Transfer (SUM = 11, DUM = 01) (a) Transfer Path Source Destination 0_1 0_2 address address 1_4 2_1 (b) EDMA Parameters Parameter Contents Parameter 2320 0000h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h...
Page 179: Element Synchronized 1D-To-1D Transfer (Sum = 11, Dum = 10)
Element Synchronized 1D-to-1D Transfers Figure A−15. Element Synchronized 1D-to-1D Transfer (SUM = 11, DUM = 10) (a) Transfer Path Source address Destination address (b) EDMA Parameters Parameter Contents Parameter 2340 0000h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h 0004h EDMA Channel Transfer Count (CNT)
Page 180: Element Synchronized 1D-To-1D Transfer (Sum = 11, Dum = 11)
Element Synchronized 1D-to-1D Transfers Figure A−16. Element Synchronized 1D-to-1D Transfer (SUM = 11, DUM = 11) (a) Transfer Path Source Destination address address (b) EDMA Parameters Parameter Contents Parameter 2360 0000h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h 0004h EDMA Channel Transfer Count (CNT)
Page 181: Frame Synchronized (Fs = 1) 1D-To-1D Transfers
Frame Synchronized 1D-to-1D Transfers A.2 Frame Synchronized 1D-to-1D Transfers The possible 1D-to-1D transfers (2DS = 2DD = 0), along with the necessary parameters using frame synchronization (FS = 1) are listed in Table A−2 and shown in Figure A−17 through Figure A−32. For each, an entire frame of elements is transferred per synchronization event.
Page 182: Frame Synchronized 1D-To-1D Transfer (Sum = 00, Dum = 00)
Frame Synchronized 1D-to-1D Transfers Figure A−17. Frame Synchronized 1D-to-1D Transfer (SUM = 00, DUM = 00) (a) Transfer Path Source Destination address address (b) EDMA Parameters Parameter Contents Parameter 2000 0001h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h 0004h EDMA Channel Transfer Count (CNT)
Page 183: Frame Synchronized 1D-To-1D Transfer (Sum = 00, Dum = 01)
Frame Synchronized 1D-to-1D Transfers Figure A−18. Frame Synchronized 1D-to-1D Transfer (SUM = 00, DUM = 01) (a) Transfer Path Source Destination 0_2 0_3 0_4 1_1 1_2 1_3 address address 2_3 2_4 (b) EDMA Parameters Parameter Contents Parameter 2020 0001h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h...
Page 184: Frame Synchronized 1D-To-1D Transfer (Sum = 00, Dum = 10)
Frame Synchronized 1D-to-1D Transfers Figure A−19. Frame Synchronized 1D-to-1D Transfer (SUM = 00, DUM = 10) (a) Transfer Path Source address 2_2 2_1 Destination address (b) EDMA Parameters Parameter Contents Parameter 2040 0001h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h 0004h...
Page 185: Frame Synchronized 1D-To-1D Transfer (Sum = 00, Dum = 11)
Frame Synchronized 1D-to-1D Transfers Figure A−20. Frame Synchronized 1D-to-1D Transfer (SUM = 00, DUM = 11) (a) Transfer Path Destination Source address address (b) EDMA Parameters Parameter Contents Parameter 2060 0001h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h 0004h EDMA Channel Transfer Count (CNT)
Page 186: Frame Synchronized 1D-To-1D Transfer (Sum = 01, Dum = 00)
Frame Synchronized 1D-to-1D Transfers Figure A−21. Frame Synchronized 1D-to-1D Transfer (SUM = 01, DUM = 00) (a) Transfer Path Source Destination 0_2 0_3 0_4 1_1 1_2 1_3 address address 2_3 2_4 (b) EDMA Parameters Parameter Contents Parameter 2100 0001h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h...
Page 187: Frame Synchronized 1D-To-1D Transfer (Sum = 01, Dum = 01)
Frame Synchronized 1D-to-1D Transfers Figure A−22. Frame Synchronized 1D-to-1D Transfer (SUM = 01, DUM = 01) (a) Transfer Path Source Destination 0_1 0_2 0_2 0_3 0_4 1_1 1_2 1_3 address address 1_4 2_1 2_3 2_4 (b) EDMA Parameters Parameter Contents Parameter 2120 0001h EDMA Channel Options Parameter (OPT)
Page 188: Frame Synchronized 1D-To-1D Transfer (Sum = 01, Dum = 10)
Frame Synchronized 1D-to-1D Transfers Figure A−23. Frame Synchronized 1D-to-1D Transfer (SUM = 01, DUM = 10) (a) Transfer Path Source 0_2 0_3 0_4 1_1 1_2 1_3 address 2_3 2_4 Destination address (b) EDMA Parameters Parameter Contents Parameter 2140 0001h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h...
Page 189: Frame Synchronized 1D-To-1D Transfer (Sum = 01, Dum = 11)
Frame Synchronized 1D-to-1D Transfers Figure A−24. Frame Synchronized 1D-to-1D Transfer (SUM = 01, DUM = 11) (a) Transfer Path Destination Source address 0_1 0_2 0_3 0_4 1_1 1_2 1_3 address 2_3 2_4 (b) EDMA Parameters Parameter Contents Parameter 2160 0001h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC)
Page 190: Frame Synchronized 1D-To-1D Transfer (Sum = 10, Dum = 00)
Frame Synchronized 1D-to-1D Transfers Figure A−25. Frame Synchronized 1D-to-1D Transfer (SUM = 10, DUM = 00) (a) Transfer Path Destination address Source address (b) EDMA Parameters Parameter Contents Parameter 2200 0001h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h 0004h EDMA Channel Transfer Count (CNT)
Page 191: Frame Synchronized 1D-To-1D Transfer (Sum = 10, Dum = 01)
Frame Synchronized 1D-to-1D Transfers Figure A−26. Frame Synchronized 1D-to-1D Transfer (SUM = 10, DUM = 01) (a) Transfer Path Destination address 0_1 0_2 0_3 0_4 1_1 1_2 1_3 2_3 2_4 Source address (b) EDMA Parameters Parameter Contents Parameter 2220 0001h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC)
Page 192: Frame Synchronized 1D-To-1D Transfer (Sum = 10, Dum = 10)
Frame Synchronized 1D-to-1D Transfers Figure A−27. Frame Synchronized 1D-to-1D Transfer (SUM = 10, DUM = 10) (a) Transfer Path 1_3 1_2 1_1 0_4 0_3 0_2 0_1 Source address Destination address (b) EDMA Parameters Parameter Contents Parameter 2240 0001h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h...
Page 193: Frame Synchronized 1D-To-1D Transfer (Sum = 10, Dum = 11)
Frame Synchronized 1D-to-1D Transfers Figure A−28. Frame Synchronized 1D-to-1D Transfer (SUM = 10, DUM = 11) (a) Transfer Path Destination address Source address (b) EDMA Parameters Parameter Contents Parameter 2260 0001h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h 0004h EDMA Channel Transfer Count (CNT)
Page 194: Frame Synchronized 1D-To-1D Transfer (Sum = 11, Dum = 00)
Frame Synchronized 1D-to-1D Transfers Figure A−29. Frame Synchronized 1D-to-1D Transfer (SUM = 11, DUM = 00) (a) Transfer Path Source address Destination address (b) EDMA Parameters Parameter Contents Parameter 2300 0001h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h 0004h EDMA Channel Transfer Count (CNT)
Page 195: Frame Synchronized 1D-To-1D Transfer (Sum = 11, Dum = 01)
Frame Synchronized 1D-to-1D Transfers Figure A−30. Frame Synchronized 1D-to-1D Transfer (SUM = 11, DUM = 01) (a) Transfer Path Source address Destination 0_1 0_2 0_3 0_4 1_1 1_2 1_3 address 2_3 2_4 (b) EDMA Parameters Parameter Contents Parameter 2320 0001h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC)
Page 196: Frame Synchronized 1D-To-1D Transfer (Sum = 11, Dum = 10)
Frame Synchronized 1D-to-1D Transfers Figure A−31. Frame Synchronized 1D-to-1D Transfer (SUM = 11, DUM = 10) (a) Transfer Path Source address Destination address (b) EDMA Parameters Parameter Contents Parameter 2340 0001h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h 0004h EDMA Channel Transfer Count (CNT)
Page 197: Frame Synchronized 1D-To-1D Transfer (Sum = 11, Dum = 11)
Frame Synchronized 1D-to-1D Transfers Figure A−32. Frame Synchronized 1D-to-1D Transfer (SUM = 11, DUM = 11) (a) Transfer Path Source Destination address address (b) EDMA Parameters Parameter Contents Parameter 2360 0001h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h 0004h EDMA Channel Transfer Count (CNT)
Page 198: Array Synchronized (Fs = 0) 2D-To-2D Transfers
Array Synchronized 2D-to-2D Transfers A.3 Array Synchronized 2D-to-2D Transfers The possible 2D-to-2D transfers (2DS = 2DD = 1), along with the necessary parameters using array synchronization (FS = 0), are listed in Table A−3 and shown in Figure A−33 through Figure A−41. For each, a single array of elements is transferred per synchronization event.
Page 199: Array Synchronized 2D-To-2D Transfer (Sum = 00, Dum = 00)
Array Synchronized 2D-to-2D Transfers Figure A−33. Array Synchronized 2D-to-2D Transfer (SUM = 00, DUM = 00) (a) Transfer Path Source Destination address address (b) EDMA Parameters Parameter Contents Parameter 4480 0000h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h 0004h EDMA Channel Transfer Count (CNT)
Page 200: Array Synchronized 2D-To-2D Transfer (Sum = 00, Dum = 01)
Array Synchronized 2D-to-2D Transfers Figure A−34. Array Synchronized 2D-to-2D Transfer (SUM = 00, DUM = 01) (a) Transfer Path Destination Source address 0_2 0_3 0_4 address 1_1 1_2 1_3 1_4 2_3 2_4 (b) EDMA Parameters Parameter Contents Parameter 44A0 0000h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC)
Page 201: Array Synchronized 2D-To-2D Transfer (Sum = 00, Dum = 10)
Array Synchronized 2D-to-2D Transfers Figure A−35. Array Synchronized 2D-to-2D Transfer (SUM = 00, DUM = 10) (a) Transfer Path Source 2_2 2_1 address Destination address (b) EDMA Parameters Parameter Contents Parameter 44C0 0000h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h 0004h...
Page 202: Array Synchronized 2D-To-2D Transfer (Sum = 01, Dum = 00)
Array Synchronized 2D-to-2D Transfers Figure A−36. Array Synchronized 2D-to-2D Transfer (SUM = 01, DUM = 00) (a) Transfer Path Source Destination address 0_2 0_3 0_4 address 1_1 1_2 1_3 1_4 2_3 2_4 (b) EDMA Parameters Parameter Contents Parameter 4580 0000h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC)
Page 203: Array Synchronized 2D-To-2D Transfer (Sum = 01, Dum = 01)
Array Synchronized 2D-to-2D Transfers Figure A−37. Array Synchronized 2D-to-2D Transfer (SUM = 01, DUM = 01) (a) Transfer Path Source Destination address address 0_2 0_3 0_4 1_1 1_2 1_3 1_4 2_3 2_4 (b) EDMA Parameters Parameter Contents Parameter 45A0 0000h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC)
Page 204: Array Synchronized 2D-To-2D Transfer (Sum = 01, Dum = 10)
Array Synchronized 2D-to-2D Transfers Figure A−38. Array Synchronized 2D-to-2D Transfer (SUM = 01, DUM = 10) (a) Transfer Path Destination address Source address 0_2 0_3 0_4 0_4 0_3 1_1 1_2 1_3 1_4 1_4 1_3 2_3 2_4 2_4 2_3 2_2 2_1 (b) EDMA Parameters Parameter Contents Parameter...
Page 205: Array Synchronized 2D-To-2D Transfer (Sum = 10, Dum = 00)
Array Synchronized 2D-to-2D Transfers Figure A−39. Array Synchronized 2D-to-2D Transfer (SUM = 10, DUM = 00) (a) Transfer Path Source address Destination 0_4 0_3 address 1_4 1_3 2_4 2_3 2_2 2_1 (b) EDMA Parameters Parameter Contents Parameter 4680 0000h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h...
Page 206: Array Synchronized 2D-To-2D Transfer (Sum = 10, Dum = 01)
Array Synchronized 2D-to-2D Transfers Figure A−40. Array Synchronized 2D-to-2D Transfer (SUM = 10, DUM = 01) (a) Transfer Path Source address Destination address 0_4 0_3 0_2 0_3 0_4 1_4 1_3 1_1 1_2 1_3 1_4 2_4 2_3 2_2 2_1 2_3 2_4 (b) EDMA Parameters Parameter Contents Parameter...
Page 207: Array Synchronized 2D-To-2D Transfer (Sum = 10, Dum = 10)
Array Synchronized 2D-to-2D Transfers Figure A−41. Array Synchronized 2D-to-2D Transfer (SUM = 10, DUM = 10) (a) Transfer Path Source address Destination address 0_4 0_3 1_4 1_3 1_4 1_3 2_4 2_3 2_2 2_1 2_4 2_3 (b) EDMA Parameters Parameter Contents Parameter 46C0 0000h EDMA Channel Options Parameter (OPT)
Page 208: Block Synchronized (Fs = 1) 2D-To-2D Transfers
Block Synchronized 2D-to-2D Transfers A.4 Block Synchronized 2D-to-2D Transfers The possible 2D-to-2D transfers (2DS = 2DD = 1), along with the necessary parameters using block synchronization (FS = 1), are listed in Table A−4 and shown in Figure A−42 through Figure A−50. For each, an entire block of arrays is transferred per synchronization event.
Page 209: Block Synchronized 2D-To-2D Transfer (Sum = 00, Dum = 00)
Block Synchronized 2D-to-2D Transfers Figure A−42. Block Synchronized 2D-to-2D Transfer (SUM = 00, DUM = 00) (a) Transfer Path Source Destination address address (b) EDMA Parameters Parameter Contents Parameter 4480 0001h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h 0004h EDMA Channel Transfer Count (CNT)
Page 210: Block Synchronized 2D-To-2D Transfer (Sum = 00, Dum = 01)
Block Synchronized 2D-to-2D Transfers Figure A−43. Block Synchronized 2D-to-2D Transfer (SUM = 00, DUM = 01) (a) Transfer Path Source Destination 0_2 0_3 0_4 address address 1_1 1_2 1_3 1_4 2_3 2_4 (b) EDMA Parameters Parameter Contents Parameter 44A0 0001h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC)
Page 211: Block Synchronized 2D-To-2D Transfer (Sum = 00, Dum = 10)
Block Synchronized 2D-to-2D Transfers Figure A−44. Block Synchronized 2D-to-2D Transfer (SUM = 00, DUM = 10) (a) Transfer Path Source 2_2 2_1 address Destination address (b) EDMA Parameters Parameter Contents Parameter 44C0 0001h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h 0004h...
Page 212: Block Synchronized 2D-To-2D Transfer (Sum = 01, Dum = 00)
Block Synchronized 2D-to-2D Transfers Figure A−45. Block Synchronized 2D-to-2D Transfer (SUM = 01, DUM = 00) (a) Transfer Path Source Destination 0_1 0_2 0_3 0_4 address address 1_1 1_2 1_3 1_4 2_3 2_4 (b) EDMA Parameters Parameter Contents Parameter 4580 0001h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC)
Page 213: Block Synchronized 2D-To-2D Transfer (Sum = 01, Dum = 01)
Block Synchronized 2D-to-2D Transfers Figure A−46. Block Synchronized 2D-to-2D Transfer (SUM = 01, DUM = 01) (a) Transfer Path Source Destination 0_1 0_2 0_3 0_4 0_1 0_2 0_3 0_4 address address 1_1 1_2 1_3 1_4 1_1 1_2 1_3 1_4 2_3 2_4 2_3 2_4 (b) EDMA Parameters Parameter Contents...
Page 214: Block Synchronized 2D-To-2D Transfer (Sum = 01, Dum = 10)
Block Synchronized 2D-to-2D Transfers Figure A−47. Block Synchronized 2D-to-2D Transfer (SUM = 01, DUM = 10) (a) Transfer Path Destination address Source 0_1 0_2 0_3 0_4 address 1_1 1_2 1_3 1_4 2_3 2_4 2_2 2_1 (b) EDMA Parameters Parameter Contents Parameter 45C0 0001h EDMA Channel Options Parameter (OPT)
Page 215: Block Synchronized 2D-To-2D Transfer (Sum = 10, Dum = 00)
Block Synchronized 2D-to-2D Transfers Figure A−48. Block Synchronized 2D-to-2D Transfer (SUM = 10, DUM = 00) (a) Transfer Path Source address Destination address 2_2 2_1 (b) EDMA Parameters Parameter Contents Parameter 4680 0001h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h 0004h...
Page 216: Block Synchronized 2D-To-2D Transfer (Sum = 10, Dum = 01)
Block Synchronized 2D-to-2D Transfers Figure A−49. Block Synchronized 2D-to-2D Transfer (SUM = 10, DUM = 01) (a) Transfer Path Source address Destination 0_1 0_2 0_3 0_4 address 1_1 1_2 1_3 1_4 2_2 2_1 2_3 2_4 (b) EDMA Parameters Parameter Contents Parameter 46A0 0001h EDMA Channel Options Parameter (OPT)
Page 217: Block Synchronized 2D-To-2D Transfer (Sum = 10, Dum = 10)
Block Synchronized 2D-to-2D Transfers Figure A−50. Block Synchronized 2D-to-2D Transfer (SUM = 10, DUM = 10) (a) Transfer Path Source address Destination address 1_4 1_3 2_2 2_1 2_4 2_3 (b) EDMA Parameters Parameter Contents Parameter 46C0 0001h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h...
Page 218: Array Synchronized (Fs = 0) 1D-To-2D Transfers
Array Synchronized 1D-to-2D Transfers A.5 Array Synchronized 1D-to-2D Transfers The possible 1D-to-2D transfers (2DS = 0, 2DD = 1), along with the necessary parameters using array synchronization (FS = 0), are listed in Table A−5 and shown in Figure A−51 through Figure A−59. For each, a single array of elements is transferred per synchronization event.
Page 219: Array Synchronized 1D-To-2D Transfer (Sum = 00, Dum = 00)
Array Synchronized 1D-to-2D Transfers Figure A−51. Array Synchronized 1D-to-2D Transfer (SUM = 00, DUM = 00) (a) Transfer Path Source Destination address address (b) EDMA Parameters Parameter Contents Parameter 4080 0000h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h 0004h EDMA Channel Transfer Count (CNT)
Page 220: Array Synchronized 1D-To-2D Transfer (Sum = 00, Dum = 01)
Array Synchronized 1D-to-2D Transfers Figure A−52. Array Synchronized 1D-to-2D Transfer (SUM = 00, DUM = 01) (a) Transfer Path Destination Source address 0_2 0_3 0_4 address 1_1 1_2 1_3 1_4 2_3 2_4 (b) EDMA Parameters Parameter Contents Parameter 40A0 0000h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC)
Page 221: Array Synchronized 1D-To-2D Transfer (Sum = 00, Dum = 10)
Array Synchronized 1D-to-2D Transfers Figure A−53. Array Synchronized 1D-to-2D Transfer (SUM = 00, DUM = 10) (a) Transfer Path Source 2_2 2_1 address Destination address (b) EDMA Parameters Parameter Contents Parameter 40C0 0000h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h 0004h...
Page 222: Array Synchronized 1D-To-2D Transfer (Sum = 01, Dum = 00)
Array Synchronized 1D-to-2D Transfers Figure A−54. Array Synchronized 1D-to-2D Transfer (SUM = 01, DUM = 00) (a) Transfer Path Source Destination 0_2 0_3 0_4 1_1 1_2 1_3 address address 2_3 2_4 (b) EDMA Parameters Parameter Contents Parameter 4180 0000h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h...
Page 223: Array Synchronized 1D-To-2D Transfer (Sum = 01, Dum = 01)
Array Synchronized 1D-to-2D Transfers Figure A−55. Array Synchronized 1D-to-2D Transfer (SUM = 01, DUM = 01) (a) Transfer Path Destination Source address 0_1 0_2 0_3 0_4 1_1 1_2 1_3 0_2 0_3 0_4 address 2_3 2_4 1_1 1_2 1_3 1_4 2_3 2_4 (b) EDMA Parameters Parameter Contents Parameter...
Page 224: Array Synchronized 1D-To-2D Transfer (Sum = 01, Dum = 10)
Array Synchronized 1D-to-2D Transfers Figure A−56. Array Synchronized 1D-to-2D Transfer (SUM = 01, DUM = 10) (a) Transfer Path Source 0_1 0_2 0_3 0_4 1_1 1_2 1_3 2_2 2_1 address 2_3 2_4 Destination address (b) EDMA Parameters Parameter Contents Parameter 41C0 0000h EDMA Channel Options Parameter (OPT) Source address...
Page 225: Array Synchronized 1D-To-2D Transfer (Sum = 10, Dum = 00)
Array Synchronized 1D-to-2D Transfers Figure A−57. Array Synchronized 1D-to-2D Transfer (SUM = 10, DUM = 00) (a) Transfer Path Destination address Source address (b) EDMA Parameters Parameter Contents Parameter 4280 0000h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h 0004h EDMA Channel Transfer Count (CNT)
Page 226: Array Synchronized 1D-To-2D Transfer (Sum = 10, Dum = 01)
Array Synchronized 1D-to-2D Transfers Figure A−58. Array Synchronized 1D-to-2D Transfer (SUM = 10, DUM = 01) (a) Transfer Path Destination address 0_2 0_3 0_4 1_1 1_2 1_3 1_4 2_3 2_4 Source address (b) EDMA Parameters Parameter Contents Parameter 42A0 0000h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC)
Page 227: Array Synchronized 1D-To-2D Transfer (Sum = 10, Dum = 10)
Array Synchronized 1D-to-2D Transfers Figure A−59. Array Synchronized 1D-to-2D Transfer (SUM = 10, DUM = 10) (a) Transfer Path 2_2 2_1 Source address Destination address (b) EDMA Parameters Parameter Contents Parameter 42C0 0000h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h 0004h...
Page 228: Block Synchronized (Fs = 1) 1D-To-2D Transfers
Block Synchronized 1D-to-2D Transfers A.6 Block Synchronized 1D-to-2D Transfers The possible 1D-to-2D transfers (2DS = 0, 2DD = 1), along with the necessary parameters using block synchronization (FS = 1), are listed in Table A−6 and shown in Figure A−60 through Figure A−68. For each, an entire block of arrays is transferred per synchronization event.
Page 229: Block Synchronized 1D-To-2D Transfer (Sum = 00, Dum = 00)
Block Synchronized 1D-to-2D Transfers Figure A−60. Block Synchronized 1D-to-2D Transfer (SUM = 00, DUM = 00) (a) Transfer Path Source Destination address address (b) EDMA Parameters Parameter Contents Parameter 4080 0001h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h 0004h EDMA Channel Transfer Count (CNT)
Page 230: Block Synchronized 1D-To-2D Transfer (Sum = 00, Dum = 01)
Block Synchronized 1D-to-2D Transfers Figure A−61. Block Synchronized 1D-to-2D Transfer (SUM = 00, DUM = 01) (a) Transfer Path Source Destination 0_1 0_2 0_3 0_4 address address 1_1 1_2 1_3 1_4 2_3 2_4 (b) EDMA Parameters Parameter Contents Parameter 40A0 0001h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC)
Page 231: Block Synchronized 1D-To-2D Transfer (Sum = 00, Dum = 10)
Block Synchronized 1D-to-2D Transfers Figure A−62. Block Synchronized 1D-to-2D Transfer (SUM = 00, DUM = 10) (a) Transfer Path Source 2_2 2_1 address Destination address (b) EDMA Parameters Parameter Contents Parameter 40C0 0001h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h 0004h...
Page 232: Block Synchronized 1D-To-2D Transfer (Sum = 01, Dum = 00)
Block Synchronized 1D-to-2D Transfers Figure A−63. Block Synchronized 1D-to-2D Transfer (SUM = 01, DUM = 00) (a) Transfer Path Source Destination address 0_1 0_2 0_3 0_4 1_1 1_2 1_3 address 2_3 2_4 (b) EDMA Parameters Parameter Contents Parameter 4180 0001h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC)
Page 233: Block Synchronized 1D-To-2D Transfer (Sum = 01, Dum = 01)
Block Synchronized 1D-to-2D Transfers Figure A−64. Block Synchronized 1D-to-2D Transfer (SUM = 01, DUM = 01) (a) Transfer Path Source Destination address 0_1 0_2 0_3 0_4 1_1 1_2 1_3 0_1 0_2 0_3 0_4 address 2_3 2_4 1_1 1_2 1_3 1_4 2_3 2_4 (b) EDMA Parameters Parameter Contents...
Page 234: Block Synchronized 1D-To-2D Transfer (Sum = 01, Dum = 10)
Block Synchronized 1D-to-2D Transfers Figure A−65. Block Synchronized 1D-to-2D Transfer (SUM = 01, DUM = 10) (a) Transfer Path Source address 0_1 0_2 0_3 0_4 1_1 1_2 1_3 2_2 2_1 2_3 2_4 Destination address (b) EDMA Parameters Parameter Contents Parameter 41C0 0001h EDMA Channel Options Parameter (OPT) Source address...
Page 235: Block Synchronized 1D-To-2D Transfer (Sum = 10, Dum = 00)
Block Synchronized 1D-to-2D Transfers Figure A−66. Block Synchronized 1D-to-2D Transfer (SUM = 10, DUM = 00) (a) Transfer Path Destination address Source address (b) EDMA Parameters Parameter Contents Parameter 4280 0001h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h 0004h EDMA Channel Transfer Count (CNT)
Page 236: Block Synchronized 1D-To-2D Transfer (Sum = 10, Dum = 01)
Block Synchronized 1D-to-2D Transfers Figure A−67. Block Synchronized 1D-to-2D Transfer (SUM = 10, DUM = 01) (a) Transfer Path Destination 0_1 0_2 0_3 0_4 address 1_1 1_2 1_3 1_4 2_3 2_4 Source address (b) EDMA Parameters Parameter Contents Parameter 42A0 0001h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC)
Page 237: Block Synchronized 1D-To-2D Transfer (Sum = 10, Dum = 10)
Block Synchronized 1D-to-2D Transfers Figure A−68. Block Synchronized 1D-to-2D Transfer (SUM = 10, DUM = 10) (a) Transfer Path 2_2 2_1 Source address Destination address (b) EDMA Parameters Parameter Contents Parameter 42C0 0001h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h 0004h...
Page 238: Array Synchronized (Fs = 0) 2D-To-1D Transfers
Array Synchronized 2D-to-1D Transfers A.7 Array Synchronized 2D-to-1D Transfers The possible 2D-to-1D transfers (2DS = 1, 2DD = 0), along with the necessary parameters using array synchronization (FS = 0), are listed in Table A−7 and shown in Figure A−69 through Figure A−77. For each, a single array of elements is transferred per synchronization event.
Page 239: Array Synchronized 2D-To-1D Transfer (Sum = 00, Dum = 00)
Array Synchronized 2D-to-1D Transfers Figure A−69. Array Synchronized 2D-to-1D Transfer (SUM = 00, DUM = 00) (a) Transfer Path Source Destination address address (b) EDMA Parameters Parameter Contents Parameter 4400 0000h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h 0004h EDMA Channel Transfer Count (CNT)
Page 240: Array Synchronized 2D-To-1D Transfer (Sum = 00, Dum = 01)
Array Synchronized 2D-to-1D Transfers Figure A−70. Array Synchronized 2D-to-1D Transfer (SUM = 00, DUM = 01) (a) Transfer Path Source Destination 0_2 0_3 0_4 1_1 1_2 1_3 address address 2_3 2_4 (b) EDMA Parameters Parameter Contents Parameter 4420 0000h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h...
Page 241: Array Synchronized 2D-To-1D Transfer (Sum = 00, Dum = 10)
Array Synchronized 2D-to-1D Transfers Figure A−71. Array Synchronized 2D-to-1D Transfer (SUM = 00, DUM = 10) (a) Transfer Path Source address 2_2 2_1 Destination address (b) EDMA Parameters Parameter Contents Parameter 4440 0000h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h 0004h...
Page 242: Array Synchronized 2D-To-1D Transfer (Sum = 01, Dum = 00)
Array Synchronized 2D-to-1D Transfers Figure A−72. Array Synchronized 2D-to-1D Transfer (SUM = 01, DUM = 00) (a) Transfer Path Source address Destination 0_2 0_3 0_4 address 1_1 1_2 1_3 1_4 2_3 2_4 (b) EDMA Parameters Parameter Contents Parameter 4500 0000h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC)
Page 243: Array Synchronized 2D-To-1D Transfer (Sum = 01, Dum = 01)
Array Synchronized 2D-to-1D Transfers Figure A−73. Array Synchronized 2D-to-1D Transfer (SUM = 01, DUM = 01) (a) Transfer Path Source address Destination 0_2 0_3 0_4 0_2 0_3 0_4 1_1 1_2 1_3 address 2_3 2_4 1_1 1_2 1_3 1_4 2_3 2_4 (b) EDMA Parameters Parameter Contents Parameter...
Page 244: Array Synchronized 2D-To-1D Transfer (Sum = 01, Dum = 10)
Array Synchronized 2D-to-1D Transfers Figure A−74. Array Synchronized 2D-to-1D Transfer (SUM = 01, DUM = 10) (a) Transfer Path Source address 0_2 0_3 0_4 1_1 1_2 1_3 1_4 2_2 2_1 2_3 2_4 Destination address (b) EDMA Parameters Parameter Contents Parameter 4540 0000h EDMA Channel Options Parameter (OPT) Source address...
Page 245: Array Synchronized 2D-To-1D Transfer (Sum = 10, Dum = 00)
Array Synchronized 2D-to-1D Transfers Figure A−75. Array Synchronized 2D-to-1D Transfer (SUM = 10, DUM = 00) (a) Transfer Path Destination 2_2 2_1 address Source address (b) EDMA Parameters Parameter Contents Parameter 4600 0000h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h 0004h...
Page 246: Array Synchronized 2D-To-1D Transfer (Sum = 10, Dum = 01)
Array Synchronized 2D-to-1D Transfers Figure A−76. Array Synchronized 2D-to-1D Transfer (SUM = 10, DUM = 01) (a) Transfer Path Destination 2_2 2_1 0_2 0_3 0_4 1_1 1_2 1_3 address 2_3 2_4 Source address (b) EDMA Parameters Parameter Contents Parameter 4620 0000h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC)
Page 247: Array Synchronized 2D-To-1D Transfer (Sum = 10, Dum = 10)
Array Synchronized 2D-to-1D Transfers Figure A−77. Array Synchronized 2D-to-1D Transfer (SUM = 10, DUM = 10) (a) Transfer Path 2_2 2_1 2_2 2_1 Source address Destination address (b) EDMA Parameters Parameter Contents Parameter 4640 0000h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h...
Page 248: Block Synchronized (Fs = 1) 2D-To-1D Transfers
Block Synchronized 2D-to-1D Transfers A.8 Block Synchronized 2D-to-1D Transfers The possible 2D-to-1D transfers (2DS = 1, 2DD = 0), along with the necessary parameters using block synchronization (FS = 1), are listed in Table A−8 and shown in Figure A−78 through Figure A−86. For each, an entire block of arrays is transferred per synchronization event.
Page 249: Block Synchronized 2D-To-1D Transfer (Sum = 00, Dum = 00)
Block Synchronized 2D-to-1D Transfers Figure A−78. Block Synchronized 2D-to-1D Transfer (SUM = 00, DUM = 00) (a) Transfer Path Source Destination address address (b) EDMA Parameters Parameter Contents Parameter 4400 0001h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h 0004h EDMA Channel Transfer Count (CNT)
Page 250: Block Synchronized 2D-To-1D Transfer (Sum = 00, Dum = 01)
Block Synchronized 2D-to-1D Transfers Figure A−79. Block Synchronized 2D-to-1D Transfer (SUM = 00, DUM = 01) (a) Transfer Path Source Destination 0_2 0_3 0_4 1_1 1_2 1_3 address address 2_3 2_4 (b) EDMA Parameters Parameter Contents Parameter 4420 0001h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h...
Page 251: Block Synchronized 2D-To-1D Transfer (Sum = 00, Dum = 10)
Block Synchronized 2D-to-1D Transfers Figure A−80. Block Synchronized 2D-to-1D Transfer (SUM = 00, DUM = 10) (a) Transfer Path Source address 2_2 2_1 Destination address (b) EDMA Parameters Parameter Contents Parameter 4440 0001h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h 0004h...
Page 252: Block Synchronized 2D-To-1D Transfer (Sum = 01, Dum = 00)
Block Synchronized 2D-to-1D Transfers Figure A−81. Block Synchronized 2D-to-1D Transfer (SUM = 01, DUM = 00) (a) Transfer Path Source Destination 0_1 0_2 0_3 0_4 address address 1_1 1_2 1_3 1_4 2_3 2_4 (b) EDMA Parameters Parameter Contents Parameter 4500 0001h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC)
Page 253: Block Synchronized 2D-To-1D Transfer (Sum = 01, Dum = 01)
Block Synchronized 2D-to-1D Transfers Figure A−82. Block Synchronized 2D-to-1D Transfer (SUM = 01, DUM = 01) (a) Transfer Path Source Destination 0_2 0_3 0_4 0_1 0_2 0_3 0_4 1_1 1_2 1_3 address address 2_3 2_4 1_1 1_2 1_3 1_4 2_3 2_4 (b) EDMA Parameters Parameter Contents Parameter...
Page 254: Block Synchronized 2D-To-1D Transfer (Sum = 01, Dum = 10)
Block Synchronized 2D-to-1D Transfers Figure A−83. Block Synchronized 2D-to-1D Transfer (SUM = 01, DUM = 10) (a) Transfer Path Source 0_1 0_2 0_3 0_4 address 1_1 1_2 1_3 1_4 2_2 2_1 2_3 2_4 Destination address (b) EDMA Parameters Parameter Contents Parameter 4540 0001h EDMA Channel Options Parameter (OPT)
Page 255: Block Synchronized 2D-To-1D Transfer (Sum = 10, Dum = 00)
Block Synchronized 2D-to-1D Transfers Figure A−84. Block Synchronized 2D-to-1D Transfer (SUM = 10, DUM = 00) (a) Transfer Path Destination 2_2 2_1 address Source address (b) EDMA Parameters Parameter Contents Parameter 4600 0001h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h 0004h...
Page 256: Block Synchronized 2D-To-1D Transfer (Sum = 10, Dum = 01)
Block Synchronized 2D-to-1D Transfers Figure A−85. Block Synchronized 2D-to-1D Transfer (SUM = 10, DUM = 01) (a) Transfer Path Destination 2_2 2_1 0_1 0_2 0_3 0_4 1_1 1_2 1_3 address 2_3 2_4 Source address (b) EDMA Parameters Parameter Contents Parameter 4620 0001h EDMA Channel Options Parameter (OPT) Source address...
Page 257: Block Synchronized 2D-To-1D Transfer (Sum = 10, Dum = 10)
Block Synchronized 2D-to-1D Transfers Figure A−86. Block Synchronized 2D-to-1D Transfer (SUM = 10, DUM = 10) (a) Transfer Path 2_2 2_1 2_2 2_1 Destination address Source address (b) EDMA Parameters Parameter Contents Parameter 4640 0001h EDMA Channel Options Parameter (OPT) Source address EDMA Channel Source Address (SRC) 0002h...
Page 258 Block Sychronized 2D-to-1D Transfers SPRU234B A-96 EDMA Transfers...
Page 259: Document Revision History
Appendix B Appendix A Revision History Table B−1 lists the changes made since the previous version of this document. Table B−1. Document Revision History Page Additions/Modifications/Deletions Changed Reload/link parameter descriptions in Table 1−2. Changed Reload/link parameter descriptions in Table 3−1. Changed Reload/link parameter descriptions in Table 4−1.
Page 260 Revision History SPRU234B Revision History...
Page 261 Index Index 1-dimensional transfers 1-11 element synchronized transfer 1-12 frame synchronized transfer 1-13 block diagram address generation/transfer logic 2-6 2-dimensional transfers 1-14 EDMA channel controller 1-4 array synchronized transfer 1-15 TMS320C621x DSP 1-3 block synchronized transfer 1-16 TMS320C64x DSP 1-3 2DD bit TMS320C671x DSP 1-3 in OPT...
Page 262 Index CIPRL 4-16 EDMA access into L2 control 4-12 EDMA channel chain enable high register (CCERH) 4-21 C621x/C671x DSP 3-26 C64x DSP 4-38 EDMA channel chain enable low register (CCERL) 4-20 contiguous elements 1-7 EDMA channel chain enable register (CCER) 3-17 CPU servicing of EDMA interrupts 1-38 EDMA channel controller event-to-channel mapping 1-19...
Page 263 Index EDMA event clear register (ECR) 3-20 in QCNT C621x/C671x DSP 3-33 EDMA event enable high register (EERH) 4-25 C64x DSP 4-45 EDMA event enable low register (EERL) 4-24 in QSCNT EDMA event enable register (EER) 3-19 C621x/C671x DSP 3-33 EDMA event high register (ERH) 4-23 C64x DSP 4-45 EDMA event low register (ERL) 4-22...
Page 264 Index ESRL 4-28 in QSIDX C621x/C671x DSP 3-33 event service priority C64x DSP 4-45 C621x/C671x DSP 3-2 FS bit C64x DSP 4-2 in OPT EVT bits C621x/C671x DSP 3-22 in ER 3-18 C64x DSP 4-33 in ERH 4-23 in QOPT in ERL 4-22 C621x/C671x DSP 3-32 EVTSEL0 bits 3-9...
Page 265 Index PRI bits in OPT C621x/C671x DSP 3-22 parameter entries C64x DSP 4-33 C621x/C671x DSP 3-22 in QOPT C64x DSP 4-32 C621x/C671x DSP 3-32 EDMA channel count reload/link address C64x DSP 4-44 parameter (RLD) in QSOPT C621x/C671x DSP 3-29 C621x/C671x DSP 3-32 C64x DSP 4-41 C64x DSP 4-44 EDMA channel destination address parameter...
Page 266 Index QDMA registers EDMA channel interrupt enable register C621x/C671x DSP 3-31 (CIER) 3-16 C64x DSP 4-43 EDMA channel interrupt pending high register (CIPRH) 4-17 QDST C621x/C671x DSP 3-33 EDMA channel interrupt pending low register C64x DSP 4-45 (CIPRL) 4-16 QIDX EDMA channel interrupt pending register C621x/C671x DSP 3-33 (CIPR) 3-15...
Page 267 QDMA channel transfer count register (QCNT) C621x/C671x DSP 3-32 C621x/C671x DSP 3-33 C64x DSP 4-44 C64x DSP 4-45 TCCM bits related documentation from Texas Instruments iii in OPT 4-33 in QOPT 4-44 reloading element count 1-26 in QSOPT 4-44 TCINT bit...
Page 268 Index transfer request queue length block synchronized C621x/C671x DSP 3-6 1D to 2D A-66 C64x DSP 4-9 2D to 1D A-86 2D to 2D A-46 transfer request submission 2-3 element synchronized A-2 transfers frame synchronized A-19 array synchronized 1D to 2D A-56 types of EDMA transfers 1-11 2D to 1D A-76 1-dimensional transfers 1-11...
Page 269 TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions:...

Texas Instruments TMS320C6000 DSP Reference Manual

1.2 EDMA Terminology

Quick DMA (QDMA)

1.3 Parameter RAM Overview

1.4 Types of EDMA Transfers

1.5 Initiating an EDMA Channel Controller Transfer

1.6 EDMA Channel Controller Event-To-Channel Mapping

1.7 Element Size and Alignment

Fixed-Mode Transfer Considerations

1.9 Parameter Set Updates

1.10 Channel Completion Conditions

1.11 Linking EDMA Transfers

1.12 Terminating an EDMA Transfer

Transfer Complete Code (TCC) Generation

1.17 Emulation Operation

1.18 Transfer Examples

Chapter 1 Topic Page

Chapter 3 . for Operation and Registers Unique to the Tms320C64X™ EDMA

Parameter RAM Overview

Chaining EDMA Channels

4.1 Event Service Priority

Parameter RAM (Param)

4.5 EDMA Transfer Controller Priority

EDMA Control Registers

4.8 EDMA Channel Parameter Entries

4.9 QDMA Registers

Quick Links

Need help?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for Texas Instruments TMS320C6000 DSP

Summary of Contents for Texas Instruments TMS320C6000 DSP