Texas Instruments TMS320C64x DSP Reference Manual page 133

Dsp video port/vcxo interpolated control (vic) port
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Table 3–23. Video Capture Channel B Control Register (VCBCTL)
Field Descriptions (Continued)
Bit
field
symval
10
RESMPL
DISABLE
ENABLE
9
Reserved –
8
SCALE
NONE
HALF
7
CON
DISABLE
ENABLE
6
FRAME
NONE
FRMCAP
5
CF2
NONE
FLDCAP
† For CSL implementation, use the notation VP_VCBCTL_field_symval
‡ For complete encoding of these bits, see Table 3–6, Table 3–11, and Table 3–12.
SPRU629
Value
BT.656 or Y/C Mode
Chroma resampling enable bit.
0
Chroma resampling is
disabled.
1
Chroma is horizontally
resampled from
4:2:2 co-sited to
4:2:0 interspersed
before saving to
chroma buffers.
0
Reserved. The reserved bit location is always read as 0. A value
written to this field has no effect.
Scaling select bit.
0
No scaling
½ scaling
1
Continuous capture enable bit.
0
Continuous capture is disabled.
1
Continuous capture is enabled.
Capture frame (data) bit.
0
Do not capture frame.
1
Capture frame.
Capture field 2 bit.
0
Do not capture field 2.
1
Capture field 2.
Video Capture Registers
Description
Raw Data Mode
TSI Mode
Not used.
Not used.
Not used.
Not used.
Not used.
Not used.
Not used.
Not used.
Do
not
capture
Do not capture
single data block.
single packet.
Capture single
Capture single
data block.
packet.
Not used.
Not used.
Not used.
Not used.
Video Capture Port
3-71

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