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Table 4–5. Video Display Control Registers (Continued)
Acronym
VDDEFVAL
VDVINT
VDFBIT
VDVBIT1
VDVBIT2
4.12.1 Video Display Status Register (VDSTAT)
The video display status register (VDSTAT) indicates the current display status
of the video port. The VDSTAT is shown in Figure 4–39 and described in
Table 4–6.
The VDXPOS and VDYPOS bits track the coordinates of the most-recently
displayed pixel. The F1D, F2D, and FRMD bits indicate the completion of fields
or frames and may need to be cleared by the DSP to prevent a DCNA interrupt
from being generated, depending on the selected frame operation. The F1D,
F2D, and FRMD bits are set when the final pixel from the appropriate field has
been sent to the output pad.
Figure 4–39. Video Display Status Register (VDSTAT)
31
30
29
—
FRMD
F2D
R-0
R/WC-0
R/WC-0
15
14
13
Reserved
VBLNK
R-0
R-0
Legend: R = Read only; WC = Write 1 to clear, write of 0 has no effect; -n = value after reset
SPRU629
Register Name
Video Display Default Display Value Register
Video Display Vertical Interrupt Register
Video Display Field Bit Register
Video Display Field 1 Vertical Blanking Bit Register
Video Display Field 2 Vertical Blanking Bit Register
28
27
F1D
R/WC-0
12
11
VDFLD
R-0
Video Display Registers
VDYPOS
R-0
VDXPOS
R-0
Video Display Port
Section
4.12.24
4.12.25
4.12.26
4.12.27
4.12.28
16
0
4-53
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