Texas Instruments TMS320C64x DSP Reference Manual page 55

Video Port Control Registers
Table 2–8. Video Port Interrupt Enable Register (VPIE) Field Descriptions (Continued)
†
Bit field symval
20 VINTB1
DISABLE
ENABLE
19 SERRB
DISABLE
ENABLE
18 CCMPB
DISABLE
ENABLE
17 COVRB
DISABLE
ENABLE
16 GPIO
DISABLE
ENABLE
15 Reserved –
14 DCNA
DISABLE
ENABLE
13 DCMP
DISABLE
ENABLE
12 DUND
DISABLE
ENABLE
11 TICK
DISABLE
ENABLE
† For CSL implementation, use the notation VP_VPIE_field_symval
2-22 Video Port
†
Value Description
Channel B field 1 vertical interrupt enable bit.
0 Interrupt is disabled.
1 Interrupt is enabled.
Channel B synchronization error interrupt enable bit.
0 Interrupt is disabled.
1 Interrupt is enabled.
Capture complete on channel B interrupt enable bit.
0 Interrupt is disabled.
1 Interrupt is enabled.
Capture overrun on channel B interrupt enable bit.
0 Interrupt is disabled.
1 Interrupt is enabled.
Video port general purpose I/O interrupt enable bit.
0 Interrupt is disabled.
1 Interrupt is enabled.
0 Reserved. The reserved bit location is always read as 0. A value
written to this field has no effect.
Display complete not acknowledged bit.
0 Interrupt is disabled.
1 Interrupt is enabled.
Display complete interrupt enable bit.
0 Interrupt is disabled.
1 Interrupt is enabled.
Display underrun interrupt enable bit.
0 Interrupt is disabled.
1 Interrupt is enabled.
System time clock tick interrupt enable bit.
0 Interrupt is disabled.
1 Interrupt is enabled.
SPRU629