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DMA Operation
Similarly if a subhorizontal line length is desired (½ line, for example), then the
line length and threshold must be chosen such that the threshold is divisible
by 2. (This can also be stated as the line length must be an even multiple of
#DMAs/line
8). For the subline case, consider the 8-bit BT.656 capture mode
with a line length of 624 (Y). If the threshold is set for ½ the line length, this
results in VCTHRLD = (624/2)/8 = 39 doublewords. The DMA logic would
calculate the Cb/Cr threshold as 39/2 = 20 doublewords. However, two such
Cb/Cr DMA events would result in a transfer of 40 doublewords, which is larger
than the actual Cb/Cr line length of (624/2)/8 = 39 doublewords. This can be
corrected by changing the line size to 640 pixels or 608 pixels, or by changing
the threshold to be 1/3 the line length (VCTHRLD = (624/3)/8 = 26 doublewords
and the Cb/Cr threshold is 26/2 = 13 doublewords. 3
13 = 39 doublewords,
which is exactly the Cb/Cr line length.)
2.3.4
DMA Interface Operation
When the video port is configured for capture (or TSI) mode, it only accepts
read requests from the DMA interface. Write requests are false acknowledged
(so the bus does not stall) and the data is discarded. When the video port is
configured for display mode, it only accepts write requests. Read requests are
false acknowledged (so the bus does not stall) and an arbitrary data value is
returned.
When the video port is in reset, is not enabled (PEREN bit cleared), halted
(VPHALT bit is set), or the active mode is not enabled (VCEN or VDEN bit is
cleared), then the port will false acknowledge all DMA accesses to prevent bus
lockup.
The video port DMA event generation logic is very tightly coupled to the DMA
interface accesses. An incorrectly programmed DMA size causes the DMA
and FIFO to become misaligned causing aberrations in the captured or
displayed data and likely resulting in an eventual FIFO overflow or underflow.
In the same manner, if another system DMA incorrectly addresses the video
port during active capture or display, the video port has no way of determining
that this is an errant DMA because all it monitors is a DMA access so it must
perform the FIFO read or write. Such an errant DMA eventually causes the
FIFO to be overread or overwritten.
SPRU629
Video Port
2-11
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