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5.1.11 Video Port Pin Interrupt Status Register (PISTAT)
The video port pin interrupt status register (PISTAT) is shown in Figure 5–11
and described in Table 5–12. PISTAT is a read-only register that indicates the
GPIO pin that has a pending interrupt.
A bit in PISTAT is set when the corresponding GPIO pin is configured as an
interrupt (the corresponding bit in PIEN is set, the pin is enabled for GPIO in
PFUNC, and the pin is configured as an input in PDIR) and the appropriate
transition (as selected by the corresponding PIPOL bit) occurs on the pin.
Whenever a PISTAT bit is set to 1, the GPIO bit in VPIS is set. The PISTAT bits
are cleared by writing a 1 to the corresponding bit in PICLR. Writing a 0 has
no effect. Clearing all the PISTAT bits does not clear the GPIO bit in VPIS, it
must be explicitly cleared. If any bits in PISTAT are still set when the GPIO bit
is cleared, the GPIO bit is set again.
Figure 5–11.Video Port Pin Interrupt Status Register (PISTAT)
31
23
22
Reserved
PISTAT22
R-0
R-0
15
14
PISTAT15
PISTAT14
R-0
R-0
7
6
PISTAT7
PISTAT6
R-0
R-0
Legend: R = Read only; -n = value after reset
SPRU629
Reserved
R-0
21
20
PISTAT21
PISTAT20
PISTAT19
R-0
R-0
13
12
PISTAT13
PISTAT12
PISTAT11
R-0
R-0
5
4
PISTAT5
PISTAT4
PISTAT3
R-0
R-0
19
18
17
PISTAT18
PISTAT17
R-0
R-0
R-0
11
10
9
PISTAT10
PISTAT9
R-0
R-0
R-0
3
2
1
PISTAT2
PISTAT1
R-0
R-0
R-0
General Purpose I/O Operation
GPIO Registers
24
16
PISTAT16
R-0
8
PISTAT8
R-0
0
PISTAT0
R-0
5-23
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