Video Capture Channel X Vertical Interrupt Register (Vcxvint) Field Descriptions - Texas Instruments TMS320C64x DSP Reference Manual

Video Capture Registers
Table 3–20. Video Capture Channel x Vertical Interrupt Register (VCxVINT)
Field Descriptions
†
Bit field symval
31 VIF2
DISABLE
ENABLE
30 FSCL2
NONE
FIELD2
29–28 Reserved –
27–16 VINT2 OF(value)
15 VIF1
DISABLE
ENABLE
14–12 Reserved –
11–0 VINT1 OF(value)
† For CSL implementation, use the notation VP_VCxVINT_field_symval
3-64 Video Capture Port
†
Value BT.656 or Y/C Mode
Setting of VINT in field 2 enable bit.
0 Setting of VINT in field 2 is
disabled.
1 Setting of VINT in field 2 is
enabled.
FSYNC bit cleared in field 2 enable bit.
0 FSYNC bit is not cleared.
1 FSYNC bit is cleared in
field 2 instead of field 1.
0 Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
0–FFFh Line that vertical interrupt
occurs if VIF2 bit is set.
Setting of VINT in field 1 enable bit.
0 Setting of VINT in field 1 is
disabled.
1 Setting of VINT in field 1 is
enabled.
0 Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
0–FFFh Line that vertical interrupt
occurs if VIF1 bit is set.
Description
Raw Data Mode TSI Mode
Not used. Not used.
Not used. Not used.
Not used. Not used.
Not used. Not used.
Not used. Not used.
Not used. Not used.
Not used. Not used.
Not used. Not used.
SPRU629