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22) If continuous display is enabled, the video port begins displaying again at
4.11.1 Handling Underrun Condition of the Display FIFO
A FIFO underrun occurs when the display FIFO is empty during an active
display line because a pending DMA request failed to load the data in time. In
case of a FIFO underrun condition, the DUND bit in VPIS is set. This condition
initiates an interrupt to the DSP, if the underrun interrupt is enabled (the DUND
bit in VPIE is set).
Because video display is typically a continuous real-time output, data output
is not halted when a FIFO underrun occurs. (To output a blanking of default
value is just as catastrophic to a display as outputting an old data value.)
Instead, the FIFO read pointer continues to advance and (old) data continues
to be output from the FIFO. This means that if the pending DMA is only slightly
late, the data transfer has a chance to catch the FIFO back up to the read
pointer and correct data output resumes. If the pending DMA does not
complete service within a threshold's worth of output data, then the DMA
request sequence is broken and the remainder of the display field is corrupted.
The underrun interrupt routine should set the BLKDIS bit in VDCTL and it
should reconfigure the DMA channel settings. Setting the BLKDIS bit flushes
the channel display FIFO and prevents channel DMA events from reaching the
DMA controller. The DMA must be reconfigured correctly for the next frame
display since the current frame transfer failed. The frame line and frame pixel
counters continue counting and, from a pin standpoint, the video display module
appears to continue to function normally (SAV/EAV codes are generated in the
BT.656 or Y/C mode and the default data value is sent out). The BLKDIS bit
should then be cleared to reenable DMA events. Clearing the BLKDIS bit does
not enable DMA events during the frame where the bit is cleared. Clearing this
bit to zero enables DMA events in the frame that follows the frame where the
bit is cleared.
SPRU629
the start of the next field or frame. If noncontinuous field 1 and field 2 or
frame display is enabled, the next field or frame is displayed, during which
the DSP must clear the appropriate completion status bit or a DCNA
interrupt occurs and incorrect data may be output.
Displaying Video in Raw Data Mode
Video Display Port
4-51
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