Video Display Field 2 Vertical Blanking End Register (Vdvblke2); Video Display Field 2 Vertical Blanking End Register (Vdvblke2) Field Descriptions - Texas Instruments TMS320DM648 User Manual

Video port/vcxo interpolated control (vic) port
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Table 4-12. Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2) Field Descriptions
(1)
Bit
field
symval
11-0
VBLNKXSTART2
OF(value)
DEFAULT

4.12.8 Video Display Field 2 Vertical Blanking End Register (VDVBLKE2)

The video display field 2 vertical blanking end register (VDVBLKE2) controls the end of vertical blanking in
field 2.
In raw data mode, VBLNK is de-asserted whenever the frame line counter (FLCOUNT) is equal to
VBLNKYSTOP2 and the frame pixel counter (FPCOUNT) is equal to VBLNKXSTOP2 (this is shown in
Figure
4-6.
In BT.656 and Y/C mode, VBLNK is de-asserted whenever FLCOUNT = VBLNKYSTOP2 and FPCOUNT
= VBLNKXSTOP2. This VBLNK output control is completely independent of the timing control codes. The
V bit in the EAV/SAV codes for field 2 is controlled by the VDVBIT2 register.
The video display field 2 vertical blanking end register (VDVBLKE2) is shown in
in
Table
4-13.
Figure 4-38. Video Display Field 2 Vertical Blanking End Register (VDVBLKE2)
31
28
Reserved
R-0
15
12
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-13. Video Display Field 2 Vertical Blanking End Register (VDVBLKE2) Field Descriptions
(1)
Bit
field
symval
31-28 Reserved
-
27-16 VBLNKYSTOP2
OF(value)
DEFAULT
15-12 Reserved
-
11-0
VBLNKXSTOP2
OF(value)
DEFAULT
(1)
For CSL implementation, use the notation VP_VDVBLKE2_field_symval
SPRUEM1 – May 2007
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(continued)
(1)
Value
BT.656 and Y/C Mode
0-FFFh
Specifies the pixel (in FPCOUNT)
where VBLNK active edge occurs for
field 2.
0
27
11
(1)
Value
BT.656 and Y/C Mode
0
Reserved. The reserved bit location is always read as 0. A value written to this
field has no effect.
0-FFFh
Specifies the line (in FLCOUNT) where Specifies the line (in FLCOUNT) where
VBLNK inactive edge occurs for field 2. vertical blanking ends (VBLNK inactive
Does not affect EAV/SAV V bit
operation.
0
0
Reserved. The reserved bit location is always read as 0. A value written to this
field has no effect.
0-FFFh
Specifies the pixel (in FPCOUNT)
where VBLNK inactive edge occurs for where vertical blanking ends (VBLNK
field 2.
0
Description
Raw Data Mode
Specifies the pixel (in FPCOUNT)
where vertical blanking begins (VBLNK
active edge) for field 2.
Figure 4-38
VBLNKYSTOP2
R/W-0
VBLNKXSTOP2
R/W-0
Description
Raw Data Mode
edge) for field 2.
Specifies the pixel (in FPCOUNT)
inactive edge) for field 2.
Video Display Registers
and described
16
0
Video Display Port
131

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