Writing To The Fifo; Tsi Fifo Packing; Tsi Timestamp Format (Little Endian) - Texas Instruments TMS320C64x DSP Reference Manual

3.8.6

Writing to the FIFO

The captured TSI packet data and the associated timestamps are written into
the receive FIFO. The packet data is written first, followed by the timestamp.
The FIFO controller controls both data writes and timestamp writes into the
FIFO. The FIFO data packing is shown in Figure 3–25.
Figure 3–25. TSI FIFO Packing
VCLKIN
VDIN[9–2]
63 56 55
TSI 15 TSI 14
TSI 7 TSI 6
TSI FIFO
63 56 55
TSI 8 TSI 9
TSI 0 TSI 1
TSI FIFO
The data capture circuitry signals to the synchronizing circuit when to take a
timestamp of the hardware counters. The FIFO write controller keeps track of
number of bytes received in a packet. It multiplexes the timestamp data and
the packet data onto the FIFO write data bus. The timestamp and packet error
information are inserted after each packet in the FIFO and must use the correct
endian byte ordering. The format for the timestamp is shown in Figure 3–26
and Figure 3–27.
Figure 3–26. TSI Timestamp Format (Little Endian)
63 62 61
PERR PSTERR
31
SPRU629
TSI 0 TSI 1 TSI 2 TSI 3 TSI 4
48 47 40 39 32
TSI 13 TSI 12
TSI 5 TSI 4
Little-Endian Packing
48 47 40 39 32
TSI 10 TSI 11
TSI 2 TSI 3
Big-Endian Packing
Reserved
PCR
TSI 5 TSI 6 TSI 7 TSI 8 TSI 9
31 24 23 16 15
TSI 11 TSI 10 TSI 9
TSI 3 TSI 2 TSI 1
31 24 23 16 15
TSI 12 TSI 13 TSI 14
TSI 4 TSI 5 TSI 6
42 41
PCR extension
Video Capture Port
TSI Capture Mode
TSI 10 TSI 11
8 7 0
TSI 8
TSI 0
8 7 0
TSI 15
TSI 7
33 32
PCR
0
3-41