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TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689D—March 2012
7.10.2.2 Programmable Range n - End Address Register (PROGn_MPEAR)
The programmable address end register holds the end address for the range. This register is writeable by a supervisor
entity only. If NS = 0 (non-secure mode) in the associated MPPA register then the register is also writeable only by
a secure entity.
The end address must be aligned on a page boundary. The size of the page depends on the MPU number. The page
size for MPU1 is 1K byte and for MPU2 it is 64K bytes. The size of the page determines the width of the address field
in MPSAR and MPEAR
Figure 7-33
Programmable Range n End Address Register (PROGn_MPEAR)
31
Legend: R = Read only; R/W = Read/Write
Table 7-61
Programmable Range n End Address Register Field Descriptions
Bit
Field
31 – 10
END_ADDR
9 – 0
Reserved
End of Table 7-61
Table 7-62
Programmable Range n End Address Register (PROGn_MPEAR) Reset Values
Register
MPU0
PROG0_MPEAR
0x01D8_03FF
PROG1_MPEAR
0x01F7_FFFF
PROG2_MPEAR
0x0209_FFFF
PROG3_MPEAR
0x021A_FFFF
PROG4_MPEAR
0x021E_0FFF
PROG5_MPEAR
0x021F_7FFF
PROG6_MPEAR
0x022F_03FF
PROG7_MPEAR
0x0231_03FF
PROG8_MPEAR
0x0232_03FF
PROG9_MPEAR
0x0233_03FF
PROG10_MPEAR
0x0235_0FFF
PROG11_MPEAR
0x024B_3FFF
PROG12_MPEAR
0x0252_03FF
PROG13_MPEAR
0x0254_03FF
PROG14_MPEAR
0x0260_FFFF
PROG15_MPEAR
0x0262_07FF
End of Table 7-62
190
TMS320C6670 Peripheral Information and Electrical Specifications
END_ADDR
R/W
Description
End address for range n
Reserved. Always read as 3FFh.
MPU1
MPU2
0x3401_FFFF
0x02A1_FFFF
0x3405_FFFF
0x02A3_FFFF
0x3406_7FFF
0x02A5_FFFF
0x340B_7FFF
0x02A6_7FFF
0x340B_FFFF
0x02A6_8FFF
N/A
0x02A6_9FFF
N/A
0x02A6_AFFF
N/A
0x02A6_BFFF
N/A
0x02A6_DFFF
N/A
0x02A6_FFFF
N/A
0x02A8_FFFF
N/A
0x02A9_FFFF
N/A
0x02AA_7FFF
N/A
0x02AA_FFFF
N/A
0x02AB_7FFF
N/A
0x02AB_FFFF
10
9
Reserved
MPU3
MPU4
0x0264_07FF
0x0215_FFFF
N/A
0x01FD_FFFF
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Copyright 2012 Texas Instruments Incorporated
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0
R
MPU5
0x3502_03FF
0x3504_07FF
0x3521_FFFF
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