Scaled Co-Sited Filtering; Scaled Chrominance Resampled Filtering - Texas Instruments TMS320C64x DSP Reference Manual

Dsp video port/vcxo interpolated control (vic) port
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Video Input Filtering
Figure 3–13. 1/2 Scaled Co-Sited Filtering
a
YCbCr 4:2:2 co-sited
input samples
1/2 scaled co-sited
capture results
Luma (Y)
sample
Figure 3–14. 1/2 Scaled Chrominance Resampled Filtering
a
YCbCr 4:2:2 co-sited
input samples
1/2 scaled
chroma-resampled
capture results
Luma (Y)
sample
Note that because input scaling is limited to ½, true CIF horizontal resolution
is not achieved if the full BT.656 horizontal line (720 pixels) is captured. A CIF
size line can be captured by selecting a 704 pixel-sized window within the
BT.656 line. This window size and location on the line are programmed using
the VCXSTARTn and VCXSTOPn bits.
Note that when ½ scaling is selected, horizontal timing applies to the incoming
data (before scaling). The VCTHRLD value applies to the data written into the
FIFO after scaling.
3-28
Video Capture Port
b
c
d
e
f
g
Chroma (Cb/Cr)
samples
Y'
= (–3Y
f
Cb'
= (–1Cb
f
Cr'
= (–1Cr
f
b
c
d
e
f g
Chroma (Cb/Cr)
samples
Cb'
Cr'
h
i
j
k
l
Y'
= (–3Y
+ 32Y
+ 70Y
h
e
g
+ 32Y
+ 70Y
+ 32Y
– 3Y
c
e
f
g
+ 17Cb
+ 17Cb
– 1Cb
c
e
g
+ 17Cr
+ 17Cr
– 1Cr
) / 32
c
e
g
i
h
i
j
k
Y'
= (–3Y
+ 32Y
+ 70Y
g
d
f
g
= (–1Cb
+ 17Cb
+ 17Cb
f
c
e
g
= (–1Cr
+ 17Cr
+ 17Cr
– 1Cr
f
c
e
g
+ 32Y
– 3Y
) / 128
h
i
k
) / 128
i
) / 32
i
l
+ 32Y
–3Y
) / 128
h
j
– 1Cb
) / 32
i
) / 32
i
SPRU629

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