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Video Display Registers
4.12.25 Video Display Vertical Interrupt Register (VDVINT)
The video display vertical interrupt register (VDVINT) controls the generation
of vertical interrupts in field 1 and field 2. The VDVINT is shown in Figure 4–64
and described in Table 4–30.
An interrupt can be generated upon completion of the specified line in a field
(when FLCOUNT = VINTn). This allows the software to synchronize itself to
the frame or field. The interrupt can be programmed to occur in one, both, or
no fields using the VIF1 and VIF2 bits.
Figure 4–64. Video Display Vertical Interrupt Register (VDVINT)
31
30
28 27
VIF2
Reserved
R/W-0
R-0
15
14
12 11
VIF1
Reserved
R/W-0
R-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 4–30. Video Display Vertical Interrupt Register (VDVINT) Field Descriptions
†
Bit
field
symval
31
VIF2
DISABLE
ENABLE
30–28 Reserved –
27–16 VINT2
OF(value)
15
VIF1
DISABLE
ENABLE
14–12 Reserved –
11–0
VINT1
OF(value)
† For CSL implementation, use the notation VP_VDVINT_field_symval
4-88
Video Display Port
†
Value
Vertical interrupt (VINT) in field 2 enable bit.
0
Vertical interrupt (VINT) in field 2 is disabled.
1
Vertical interrupt (VINT) in field 2 is enabled.
0
Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
0–FFFh
Line where vertical interrupt (VINT) occurs, if VIF2 bit is set.
Vertical interrupt (VINT) in field 1 enable bit.
0
Vertical interrupt (VINT) in field 1 is disabled.
1
Vertical interrupt (VINT) in field 1 is enabled.
0
Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
0–FFFh
Line where vertical interrupt (VINT) occurs, if VIF1 bit is set.
VINT2
R/W-0
VINT1
R/W-0
Description
16
0
SPRU629
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