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Table 4–4. Display Operation
VDCTL Bit
CON
FRAME
DF2
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
SPRU629
DF1
Operation
0
Reserved
1
Noncontinuous field 1 display. Display only field 1. F1D is set after
field 1 display and causes DCMPx to be set. The F1D bit must be
cleared by the DSP or a DCNA interrupt occurs. (The DSP has the en-
tire field 2 time to clear F1D before next field 1 begins.) Can also be
used for single progressive frame display (internal timing codes only).
(The DSP has vertical blanking time to clear F1D before next frame
begins.)
0
Noncontinuous field 2 display. Display only field 2. F2D is set after
field 2 display and causes DCMPx to be set. The F2D bit must be
cleared by the DSP or a DCNA interrupt occurs. (The DSP has the en-
tire field 1 time to clear F2D before next field 2 begins.)
1
Noncontinuous field 1 and field 2 display. Display both fields. F1D is set
after field 1 display and causes DCMPx to be set. The F1D bit must be
cleared by the DSP before the next field 1 display or a DCNA interrupt
occurs. (The DSP has the entire field 2 time to clear F1D before next
field 1 begins.) F2D is set after field 2 display and also causes DCMPx
to be set. The F2D bit must be cleared by the DSP before the next
field 2 display or a DCNA interrupt occurs. (The DSP has the entire
field 1 time to clear F2D before next field 2 begins.)
0
Noncontinuous frame display. Display both fields. FRMD is set after
field 2 display and causes DCMPx to be set. A DCNA interrupt occurs
upon completion of the next frame unless the FRMD bit is cleared. (The
DSP has the entire next frame time to clear FRMD.)
1
Noncontinuous progressive frame display. Display field 1. FRMD is set
after field 1 display and causes DCMPx to be set. A DCNA interrupt
occurs upon completion of the next frame unless the FRMD bit is
cleared. (The DSP has the entire next frame time to clear FRMD.) If
external control signals are used, they must follow progressive format.
0
Reserved
1
Single frame display. Display both fields. FRMD is set after field 2 dis-
play and causes DCMPx to be set. A DCNA interrupt occurs unless the
FRMD bit is cleared. (The DSP has the field 2 to field 1 vertical blank-
ing time to clear FRMD.)
0
Reserved
1
Continuous field 1 display. Display only field 1. F1D is set after field 1
display and causes DCMPx to be set (DCMPx interrupt can be dis-
abled). No DCNA interrupt occurs, regardless of the state of F1D.
Video Display Field and Frame Operation
Video Display Port
4-31
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