Texas Instruments TMS320C64x DSP Reference Manual page 201

Video Display Registers
Table 4–7. Video Display Control Register (VDCTL) Field Descriptions (Continued)
† †
Bit Bit field field symval symval
30 BLKDIS
CLEAR
BLOCK
29 Reserved –
28 PVPSYN
DISABLE
ENABLE
27–24 Reserved –
23 FXS
OUTPUT
FSINPUT
22 VXS
OUTPUT
VSINPUT
† For CSL implementation, use the notation VP_VDCTL_field_symval
‡ For complete encoding of these bits, see Table 4–4.
4-56 Video Display Port
BT.656 and Y/C Mode
† †
Value Value
Block display events bit. BLKDIS functions as a display FIFO reset
without affecting the current programmable register values.
The video display module continues to function normally, the
counters count, control outputs are generated, EAV/SAV codes are
generated for BT.656 and Y/C modes, and default or blanking data
is output during active display time. No data is moved to the
display FIFOs because no events occur. The F1D, F2D, and
FRMD bits in VDSTAT are still set when fields or frames are
complete.
0 Clearing BLKDIS does not enable DMA events during the field in
which the bit is cleared. DMA events are enabled at the start of the
next frame after the one in which the bit is cleared. This allows the
DMA to always be synced to the proper field.
1 Blocks DMA events and flushes the display FIFOs.
0 Reserved. The reserved bit location is always read as 0. A value
written to this field has no effect.
Previous video port synchronization enable bit.
0
1 Output timing is locked to preceding video port (VP2 is locked to
VP1 or VP1 is locked to VP0, see Figure 4–7 on page 4-8).
0 Reserved. The reserved bit location is always read as 0. A value
written to this field has no effect.
Field external synchronization enable bit.
0 VCTL3 is an output.
1 VCTL3 is an external field sync input.
Vertical external synchronization enable bit.
0 VCTL2 is an output.
1 VCTL2 is an external vertical sync input.
Description
Raw Data Mode
SPRU629