Texas Instruments TMS320C64x DSP Reference Manual page 203

Video Display Registers
Table 4–7. Video Display Control Register (VDCTL) Field Descriptions (Continued)
† †
Bit Bit field field symval symval
13 RGBX
DISABLE
ENABLE
12 RSYNC
DISABLE
ENABLE
11 DVEN
BLANKING
DV
10 RESMPL
DISABLE
ENABLE
9 Reserved –
8 SCALE
NONE
X2
‡
7 CON
DISABLE
ENABLE
† For CSL implementation, use the notation VP_VDCTL_field_symval
‡ For complete encoding of these bits, see Table 4–4.
4-58 Video Display Port
BT.656 and Y/C Mode
† †
Value Value
RGB extract enable bit.
0 Not used.
1 Not used.
Second, synchronized raw data channel enable bit.
0 Not used.
1 Not used.
Default value enable bit.
0 Blanking value is output during
non-sourced active pixels.
1 Default value is output during
non-sourced active pixels.
Chroma resampling enable bit.
0 Chroma resampling is disabled.
1 Chroma is horizontally
resampled from 4:2:0
interspersed to 4:2:2 co-sited
before output.
0 Reserved. The reserved bit location is always read as 0. A value
written to this field has no effect.
Scaling select bit.
0 No scaling
1 2 scaling
Continuous display enable bit.
0 Continuous display is disabled.
1 Continuous display is enabled.
Description
Raw Data Mode
Perform ¾ FIFO unpacking.
Second, synchronized raw data
channel is disabled.
Second, synchronized raw data
channel is enabled.
Not used.
Not used.
Not used.
Not used.
Not used.
Not used.
SPRU629