Video Display Status Register (Vdstat) Field Descriptions - Texas Instruments TMS320C64x DSP Reference Manual

Video Display Registers
Table 4–6. Video Display Status Register (VDSTAT) Field Descriptions
†
Bit
field symval
31 Reserved –
30 FRMD
NONE
DISPLAYED
29 F2D
NONE
DISPLAYED
28 F1D
NONE
DISPLAYED
27–16 VDYPOS OF(value)
15–14 Reserved –
13 VBLNK
EMPTY
NOTEMPTY
12 VDFLD
FIELD1ACT
FIELD2ACT
11–0 VDXPOS OF(value)
† For CSL implementation, use the notation VD_VDSTAT_field_symval
4-54 Video Display Port
†
Value Description
0 Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
Frame displayed bit. Write 1 to clear the bit, a write of 0 has
no effect.
0 Complete frame has not been displayed.
1 Complete frame has been displayed.
Field 2 displayed bit. Write 1 to clear the bit, a write of 0 has
no effect.
0 Field 2 has not been displayed.
1 Field 2 has been displayed.
Field 1 displayed bit. Write 1 to clear the bit, a write of 0 has
no effect.
0 Field 1 has not been displayed.
1 Field 1 has been displayed.
0–FFFh Current frame line counter (FLCOUNT) value. Index of the
current line in the current field being displayed by the
module.
0 Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
Vertical blanking bit.
0 Video display is not in a vertical-blanking interval.
1 Video display is in a vertical-blanking interval.
VDFLD bit indicates which field is currently being displayed.
The VDFLD bit is updated at the start of the vertical blanking
interval of the next field.
0 Field 1 is active.
1 Field 2 is active.
0–FFFh Current frame pixel counter (FPCOUNT) value. Index of the
most recently output pixel.
SPRU629