Page 1 TMS320C6000 Chip Support Library API Reference Guide Literature Number SPRU401 March 2000 Printed on Recycled Paper...
Page 2 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete.
Page 3 Read This First About This Manual Welcome to the TMS320C6000 Chip Support Library, or CSL for short. The CSL is a set of application programming interfaces (APIs) used to configure and control all on-chip peripherals. It is intended to make it easier for develop- ers by eliminating much of the tedious grunt-work usually needed to get algo- rithms up and running in a real system.
Page 4 Macro names are written in uppercase text; function names are written in lowercase. TMS320C6000 devices are referred to throughout this reference guide as ’C6201, ’C6202, etc. Related Documentation From Texas Instruments The following books describe the TMS320C6x devices and related support tools.
Page 5 DMA (EDMA), expansion bus, clocking and phase-locked loop (PLL), and the power-down modes. TMS320C6000 Programmer’s Guide (literature number SPRU198) describes ways to optimize C and assembly code for the TMS320C6000 DSPs and includes application program examples. TMS320C6000 Assembly Language Tools User’s Guide (literature number...
Page 6: Table Of Contents
Contents Contents Introduction ..............Provides an overview of the chip support library (CSL) and its two-layer architecture.
Page 7 Contents CSL API Reference ............. . Provides an alphabetical list of the CSL service layer API functions.
Page 8 Figures Figures 1–1 CSL Layers ..............1–2 API Modules within Service Layer .
Page 9 ..............3-11 4–1 CSL API Module Support for TMS320C6000 Devices ......
Page 10: Introduction
Chapter 1 Introduction This chapter provides an overview of the chip support library (CSL) and its two- layer architecture. Topic Page CSL Overview ..........HAL Overview .
Page 11: Csl Overview
CSL Overview 1.1 CSL Overview The CSL is written primarily in C with some assembly language where needed. The library is made up of discrete modules that are built and archived into a library file. Each module represents an individual API and is referred to simply as an API module.
Page 12: Csl Layers
CSL Overview Figure 1–1. CSL Layers Service Layer Chip Support Library (CSL) Introduction...
Page 13: Hal Overview
HAL Overview 1.2 HAL Overview The hardware abstraction layer, or HAL, is a set of constants and macros that fully describes the peripheral registers by way of symbols. It is capable of hid- ing subtle differences between devices such as bit-fields changing size or position within a register.
Page 14: Service Layer Overview
Service Layer Overview 1.3 Service Layer Overview The service layer is where the actual APIs are defined and is the layer the user interfaces to. It is possible for the user to interface directly into the HAL but this is not advisable because it could have undesired side effects on the operation of the service layer APIs.
Page 15: Csl Api Module Descriptions
Chapter 2 CSL API Module Descriptions This chapter describes the purpose of the individual CSL API modules within the chip support library (CSL) and explains how they work. This information is intended for those who want to understand the internal workings of the ser- vice layer APIs.
Page 16: Csl Api Module Introduction
CSL API Module Introduction 2.1 CSL API Module Introduction There are certain methods used across different modules that are worth men- tioning at the global level. OPEN and CLOSE Functions Peripherals that have multiple channels, ports, etc. must be managed as resources in a shared environment.
Page 17 CSL API Module Introduction val = PER_MK_REG(0,4,1,3,8); or, to make your code more readable and self-documenting, you can use the symbolic constants for the field values like this: val = PER_MK_REG( PER_REG_F0_VAL0, PER_REG_F1_VAL1, PER_REG_F2_VAL1, PER_REG_F3_VAL0, PER_REG_F4_VAL3 You could just as well use variables for the field values. If you used all constants for the field values, the whole macro resolves down to a single constant number at compile time.
Page 18 CSL API Module Introduction A couple rules apply to these macros: Only writeable register fields are arguments, no read-only fields The register field arguments are specified least-significant first If a field is not implemented for a particular device, use the PER_REG_FIELD_NA value Initializing the Registers of a Peripheral Related to the MK macros is a pair of functions and a structure definition that...
Page 19 CSL API Module Introduction enabling inlining when the functions are very small. This is because the size of the function is smaller than the state saving code required to call the function if it were not inlined. The API reference does not state which functions are in- lined and which are not: this allows for future changes.
Page 20: Cache
CACHE 2.2 CACHE The CACHE module offers a small set of API functions for managing data and program cache. The CACHE module includes: Constant CACHE_SUPPORT Functions CACHE_Clean CACHE_EnableCaching CACHE_Flush CACHE_GetL2SramSize CACHE_Invalidate CACHE_Reset CACHE_SetL2Mode CACHE_SetPccMode CACHE Architectures Currently, there are two cache architectures used on ’C6x devices. The first type, which is present on the ’6201device, provides program cache by disab- ling on-chip program RAM and turning it into cache.
Page 21: Csl
2.3 CSL The CSL module is the top-level API module whose primary purpose is to ini- tialize the library. Only one function is exported: CSL_Init() The CSL_Init() function must be called once at the beginning of your program before calling any other CSL API functions. For additional information about the CSL module, refer to Table 3–2 on page 3-2 and Section 4.3 on page 4-10.
Page 22: Dat
2.4 DAT The DAT module, which stands for data, is used to move data around by means of DMA/EDMA hardware. This module serves as a level of abstraction such that it works the same for devices that have the DMA peripheral and de- vices that have the EDMA peripheral.
Page 23 Note: For devices that have EDMA, the DAT module uses the quick DMA feature. This means that the module doesn’t have to internally allocate a DMA chan- nel. However, you are still required to open the DAT module before use. Devices With DMA On devices such as the ’6201 that have the DMA peripheral, only one request may be active at once since only one DMA channel is used.
Page 24: Chip
CHIP 2.5 CHIP The CHIP module is where chip-specific and chip-related code resides. This module has the potential to grow in the future as more devices are placed on the market. Currently, CHIP has some API functions for obtaining device en- dianess, memory map mode if applicable, and CPU and REV IDs.
Page 25: Dma
2.6 DMA Currently, there are two DMA architectures used on ’C6x devices: DMA and EDMA (enhanced DMA). Devices such as the ’6201 have the DMA peripheral, whereas the ’6211 has the EDMA peripheral. The two architectures are differ- ent enough to warrant a separate API module for each. The DMA module in- cludes: Constants DMA_CHA_CNT...
Page 26 DMA_MK_AUXCTL DMA_MK_DST DMA_MK_GBLADDR DMA_MK_GBLCNT DMA_MK_GBLIDX DMA_MK_PRICTL DMA_MK_SECCTL DMA_MK_SRC DMA_MK_XFRCNT Structure DMA_CONFIG Using a DMA Channel To use a DMA channel, you must first open it and obtain a device handle using DMA_Open(). Once opened, you use the device handle to call the other API functions.
Page 27: Edma
EDMA 2.7 EDMA Currently, there are two DMA architectures used on ’C6x devices, DMA and EDMA (enhanced DMA). Devices such as the ’6201 have the DMA peripheral whereas the ’6211 has the EDMA peripheral. The two architectures are differ- ent enough to warrant a separate API module for each. The EDMA module in- cludes: Constants EDMA_CHA_CNT...
Page 28 EDMA EDMA_MK_IDX EDMA_MK_OPT EDMA_MK_RLD EDMA_MK_SRC Structure EDMA_CONFIG Using an EDMA Channel To use an EDMA channel, you must first open it and obtain a device handle using EDMA_Open(). Once opened, use the device handle to call the other API functions. The channel may be configured by passing an EDMA_CONFIG structure to EDMA_ConfigA() or by passing register values to the EDMA_ConfigB() function.
Page 29: Emif
EMIF 2.8 EMIF The EMIF module has a simple API for configuring the EMIF registers. The EMIF may be configured by passing an EMIF_CONFIG structure to EMIF_ConfigA() or by passing register values to the EMIF_ConfigB() function. To assist in creating register values, there are EMIF_MK (make) mac- ros that construct register values based on field values.
Page 30: Hpi
2.9 HPI The HPI module has a simple API for configuring the HPI registers. Functions are provided for reading HPI status bits and setting interrupt events. The HPI module includes: Constant HPI_SUPPORT Functions HPI_GetDspint HPI_GetEventId HPI_GetFetch HPI_GetHint HPI_GetHrdy HPI_GetHwob HPI_SetDspint HPI_SetHint For additional information about the HPI module, refer to Table 3–8 on page 3-8 and Section 4.9 on page 4-81.
Page 31: Irq
2.10 IRQ The IRQ module manages CPU interrupts. The IRQ module includes: Constants IRQ_EVT_NNNN IRQ_SUPPORT Functions IRQ_Clear IRQ_Disable IRQ_Enable IRQ_Map IRQ_Set IRQ_Test CSL API Module Descriptions 2-17...
Page 32: Mcbsp
MCBSP 2.11 MCBSP The MCBSP module contains a set of API functions for configuring the McBSP registers. The MCBSP module includes: Constants MCBSP_PORT_CNT MCBSP_SUPPORT Functions MCBSP_Close MCBSP_ConfigA MCBSP_ConfigB MCBSP_EnableFsync MCBSP_EnableRcv MCBSP_EnableSrgr MCBSP_EnableXmt MCBSP_GetPins MCBSP_GetRcvAddr MCBSP_GetRcvEventId MCBSP_GetXmtAddr MCBSP_GetXmtEventId MCBSP_Open MCBSP_Read MCBSP_Reset MCBSP_Rfull MCBSP_Rrdy MCBSP_RsyncErr...
Page 33 MCBSP MCBSP_XsyncErr Macros MCBSP_MK_MCR MCBSP_MK_PCR MCBSP_MK_RCER MCBSP_MK_RCR MCBSP_MK_SPCR MCBSP_MK_SRGR MCBSP_MK_XCER MCBSP_MK_XCR Structure MCBSP_CONFIG Using a MCBSP Port To use a MCBSP port, you must first open it and obtain a device handle using MCBSP_Open(). Once opened, use the device handle to call the other API functions.
Page 34: Pwr
2.12 PWR The PWR module is used to configure the power-down control registers, if ap- plicable, and to invoke various power-down modes. The PWR module in- cludes: Constant PWR_SUPPORT Functions PWR_ConfigB PWR_PowerDown Macro PWR_MK_PDCTL For additional information about the PWR module, refer to Table 3–11 on page 3-10 and Section 4.12 on page 4-114.
Page 35: Stdinc
STDINC 2.13 STDINC The STDINC module defines some identifiers that are globally useful to every- one and are used throughout the CSL source code. The application is free to use any identifiers defined here. The main set of identifiers are type definitions for integer data types.
Page 36: Timer
TIMER 2.14 TIMER The TIMER module has a simple API for configuring the timer registers. The TIMER module includes: Constants TIMER_DEVICE_CNT TIMER_SUPPORT Functions TIMER_Close TIMER_ConfigA TIMER_ConfigB TIMER_GetCount TIMER_GetDatin TIMER_GetEventId TIMER_GetPeriod TIMER_GetTstat TIMER_Open TIMER_Pause TIMER_Reset TIMER_Resume TIMER_SetCount TIMER_SetDatout TIMER_SetPeriod TIMER_Start Macro TIMER_MK_CTL Structure TIMER_CONFIG...
Page 37 TIMER functions. The timer device may be configured by passing a TIMER_CONFIG structure to TIMER_ConfigA() or by passing register values to the TIM- ER_ConfigB() function. To assist in creating register values, there are TIM- ER_MK (make) macros that construct register values based on field values. In addition, there are symbol constants that may be used for the field values.
Page 38 Chapter 3 CSL API Function Tables This chapter provides tables containing all CSL API functions, a brief descrip- tion of each, and a page reference for more detailed information. Topic Page CSL Function Tables ......... . Table 3–1 CACHE .
Page 39 CSL Function Tables 3.1 CSL Function Tables Each of the tables in this section contains information about a specific CSL module and its APIs. The syntax is shown next to a column indicating the type of API: Function, Constant, Macro, or Structure. A brief description of each is provided along with a page reference for more detailed information.
Page 40: Csl Api Function Tables
CSL Function Tables Table 3–3. DAT Syntax Type Description Page Closes the DAT module 4-11 DAT_Close Copies a linear block of data from Src to Dst using DMA 4-11 DAT_Copy or EDMA hardware Performs a 2-dimensional data copy using DMA or EDMA 4-13 DAT_Copy2D hardware.
Page 41 CSL Function Tables Table 3–5. DMA Syntax Type Description Page Starts a DMA channel with autoinitialization 4-23 DMA_AutoStart Provides resource management for the DMA global 4-22 DMA_AllocGlobalReg registers Number of DMA channels for the current device 4-23 DMA_CHA_CNT Clears one of the condition flags in the DMA secondary 4-24 DMA_CLEAR_CONDITION control register...
Page 42 CSL Function Tables Table 3–5. DMA (Continued) Syntax Type Description Page Opens a DMA channel for use 4-46 DMA_Open Pauses the DMA channel by setting the START bits in the 4-47 DMA_Pause primary control register appropriately Resets the DMA channel by setting its registers to power-on 4-47 DMA_Reset defaults...
Page 43 CSL Function Tables Table 3–6. EDMA Syntax Type Description Page Allocates a parameter RAM table from PRAM 4-51 EDMA_AllocTable Number of EDMA channels 4-51 EDMA_CHA_CNT Clears the EDMA event flag in the EDMA channel event 4-52 EDMA_ClearChannel register Closes a previously opened EDMA channel 4-52 EDMA_Close The EDMA configuration structure used to set up an EDMA...
Page 44 CSL Function Tables Table 3–6. EDMA (Continued) Syntax Type Description Page Triggers an EDMA channel by writing to the appropriate bit 4-68 EDMA_SetChannel in the event set register (ESR) A compile time constant whose value is 1 if the device 4-68 EDMA_SUPPORT supports the EDMA module...
Page 45 CSL Function Tables Table 3–8. HPI Syntax Type Description Page Reads the DSPINT bit from the HPIC register 4-81 HPI_GetDspint Obtain the IRQ event associated with the HPI device 4-81 HPI_GetEventId Reads the FETCH flag from the HPIC register and returns 4-81 HPI_GetFetch its value.
Page 46 CSL Function Tables Table 3–10. MCBSP Syntax Type Description Page 4-87 MCBSP_Close Closes MCBSP port previously opened MCBSP_Open() Used to setup a MCBSP port 4-87 MCBSP_CONFIG Sets up the MCBSP port using the configuration structure 4-88 MCBSP_ConfigA Sets up the MCBSP port using the register values passed 4-89 MCBSP_ConfigB Enables the frame sync generator for the given port...
Page 47 CSL Function Tables Table 3–10. MCBSP (Continued) Syntax Type Description Page Performs a direct 32-bit read of the data receive register 4-109 MCBSP_Read Resets the given serial port 4-109 MCBSP_Reset Reads the RFULL bit of the serial port control register 4-110 MCBSP_Rfull Reads the RRDY status bit of the SPCR register...
Page 48 CSL Function Tables Table 3–12. TIMER Syntax Type Description Page Closes a previously opened timer device 4-119 TIMER_Close Structure used to set up a timer device 4-119 TIMER_CONFIG Configure timer using configuration structure 4-120 TIMER_ConfigA Sets up the timer using the register values passed in 4-120 TIMER_ConfigB A compile time constant;...
Page 49: Csl Api Reference
Chapter 4 CSL API Reference This chapter provides an alphabetical list of the chip support library (CSL) ser- vice layer API functions, enumerations, type definitions, macros, structures, constants, and global variables. Topic Page CSL API Reference Introduction ....... . CACHE .
Page 50: Csl Api Module Support For Tms320C6000 Devices
Because of this, calling an EDMA API function on devices not supporting EDMA will result in a compiler and/or linker error. Table 4–1 shows which devices each API module is supported on: Table 4–1. CSL API Module Support for TMS320C6000 Devices Module ’6201 ’6202...
Page 51: Cache
CACHE 4.2 CACHE 4.2.1 Cleans a range of L2 cache CACHE_Clean Function void CACHE_Clean( CACHE_REGION Region, UINT32 Addr, UINT32 WordCt Arguments Specifies which cache region to clean; must be one of the Region following: CACHE_L2 CACHE_L2ALL Beginning address of range to clean; word aligned Addr Number of 4-byte words to clean WordCt...
Page 52 CACHE 4.2.2 CACHE_EnableCaching Specifies block of ext. memory for caching Function void CACHE_EnableCaching( UINT32 Block Arguments Specifies a block of external memory to enable caching for; Block must one of the following: CACHE_CE33 –(0xB3000000 to 0xB3FFFFFF) CACHE_CE32 –(0xB2000000 to 0xB2FFFFFF) CACHE_CE31 –(0xB1000000 to 0xB1FFFFFF) CACHE_CE30 –(0xB0000000 to 0xB0FFFFFF) CACHE_CE23 –(0xA3000000 to 0xA3FFFFFF)
Page 53 CACHE 4.2.3 CACHE_Flush Flushes a region of cache Function void CACHE_Flush( CACHE_REGION Region, UINT32 Addr, UINT32 WordCt Arguments Specifies which cache region to flush from; must be one Region of the following: CACHE_L2 CACHE_L2ALL CACHE_L1D Starting address of memory range to flush Addr Beginning address of range to flush;...
Page 54 CACHE 4.2.5 CACHE_Invalidate Invalidates a region of cache Function void CACHE_Invalidate( CACHE_REGION Region, UINT32 Addr, UINT32 ByteCt Arguments Specifies which cache region to invalidate; must be one Region of the following: Invalidate L1P CACHE_L1P Invalidate all of L1P CACHE_L1PALL Invalidate all of L1D CACHE_L1DALL Beginning address of range to invalidate;...
Page 55 CACHE 4.2.6 CACHE_Reset Resets cache to power-on default Function void CACHE_Reset(); Arguments none Return Value none Description Resets cache to power-on default. Devices with L2 Cache: PCC and DCC fields of CSR are set to zero (mapped) All MAR bits are cleared L2 mode set to all SRAM Devices without L2 Cache: PCC field of CSR set to zero (mapped)
Page 56 CACHE Return Value Returns old cache mode; will be one of the following: OldMode CACHE_0KSRAM CACHE_16KSRAM CACHE_32KSRAM CACHE_48KSRAM CACHE_64KSRAM CACHE_0KCACHE CACHE_16KCACHE CACHE_32KCACHE CACHE_48KCACHE CACHE_64KCACHE Description Sets the mode of the L2 cache. There are three conditions that may occur as a result of changing cache modes: 1.
Page 57 This function sets the program cache mode for devices that don’t have an L2 cache. For devices that do have an L2 cache such as the ’6211, this function does nothing. See the TMS320C6000 Peripherals Refer- ence Guide (literature number SPRU190) for the meaning of the cache modes.
Page 58: Csl
4.3 CSL 4.3.1 CSL_Init Calls the initialization function of all CSL API modules Function void CSL_Init(); Arguments none Return Value none Description The CSL module is the top-level API module whose primary purpose is to initialize the library. Only one function is exported: CSL_Init() The CSL_Init() function must be called once at the beginning of your pro- gram before calling any other CSL API functions.
Page 59: Dat
4.4 DAT 4.4.1 DAT_Close Closes the DAT module Function void DAT_Close(); Arguments none Return Value none Description Closes the DAT module. First, any pending requests are allowed to complete; then if applicable, any DMA channels are closed. Example DAT_Close(); 4.4.2 DAT_Copy Copies a linear block of data from Src to Dst using DMA or EDMA hardware...
Page 60 Example #define DATA_SIZE 256 UINT32 BuffA[DATA_SIZE/sizeof(UINT32)]; UINT32 BuffB[DATA_SIZE/sizeof(UINT32)]; DAT_Open(DAT_CHAANY,DAT_PRI_LOW,0); DAT_Copy(BuffA,BuffB,DATA_SIZE); 4-12...
Page 61 4.4.3 DAT_Copy2D Perform 2-dimensional data copy Function UINT32 DAT_Copy2D( UINT32 Type, void *Src, void *Dst, UINT16 LineLen, UINT16 LineCnt, UINT16 LinePitch Arguments Transfer type: Type DAT_1D2D DAT_2D1D DAT_2D2D Pointer to source data Pointer to destination location Number of bytes per line LineLen Number of lines LineCnt...
Page 62 Figure 4–1. 2D Transfer LineLen LineLen = 5 LineCnt = 6 LinePitch = 8 LineCnt LinePitch If a 2D to 2D transfer is specified, both the source and destination have the same LineLen, LineCnt, and LinePitch. The return value is a transfer identifier that may be used later on to wait for completion.
Page 63 Description Fills a linear block of memory with the specified fill value using DMA hardware. The arguments are checked for alignment and the DMA is submitted accordingly. For best performance, you should ensure that the destination address is aligned on a 4-byte boundary and the trans- fer length is a multiple of 4.
Page 64 4.4.5 DAT_Open Opens the DAT module Function void DAT_Open( int ChaNum, int Priority, UINT32 Flags Arguments Specifies which DMA channel to allocate; must be one ChaNum of the following: DAT_CHAANY DAT_CHA0 DAT_CHA1 DAT_CHA2 DAT_CHA3 Specifies the priority of the DMA channel; must be one Priority of the following: DAT_PRI_LOW...
Page 65 Description This function opens up the DAT module and must be called before call- ing any of the other DAT API functions. The ChaNum argument speci- fies which DMA channel to open for exclusive use by the DAT module. For devices with EDMA, the ChaNum argument is ignored because the quick DMA is used which doesn’t have a channel associated with it.
Page 66 4.4.6 DAT_Support A compile time constant whose value is 1 if the device supports the DAT module Constant DAT_SUPPORT Description Compile time constant that has a value of 1 if the device supports the DAT module and 0 otherwise. You are not required to use this constant. Currently, all devices support this module.
Page 67: Chip
CHIP 4.5 CHIP 4.5.1 CHIP_6XXX Current chip identification symbols Constant CHIP_6201 CHIP_6202 CHIP_6203 CHIP_6204 CHIP_6205 CHIP_6211 CHIP_6211X CHIP_6701 CHIP_6711 Description These are the current chip identification symbols. They are used throughout the CSL code to make compile-time decisions. When using the CSL, it is up to the user to define one and only one of these sym- bols.
Page 68 CHIP 4.5.2 CHIP_GetCpuId Returns the CPU ID field of the CSR register Function UINT32 CHIP_GetCpuId(); Arguments none Return Value Returns the CPU ID CPU ID Description This function returns the CPU ID field of the CSR register. Example UINT32 CpuId; CpuId = CHIP_GetCpuId();...
Page 69 CHIP 4.5.4 CHIP_GetMapMode Returns the current map mode of the device Function int CHIP_GetMapMode(); Arguments none Return Value Returns current device MAP mode; will be one of the map mode following: _MAP_0 CHIP _MAP_1 CHIP Description Returns the current MAP mode of the device as determined by the MAP bit of the EMIF global control register.
Page 70: Dma
4.6 DMA 4.6.1 DMA_AllocGlobalReg Allocates a global DMA register Function UINT32 DMA_AllocGlobalReg( DMA_GBL RegType, UINT32 InitVal Arguments Global register type; must be one of the RegType following: DMA_GBL_ADDRRLD DMA_GBL_INDEX DMA_GBL_CNTRLD DMA_GBL_SPLIT Value to initialize the register to InitVal Return Value Unique ID number for the global register Global Register ID Description...
Page 71 DMA_GBL_CNTRLD Allocate global count reload register for use as DMA CNT RE- LOAD. Will allocate one of the following DMA registers: Global Count Reload Register A Global Count Reload Register B DMA_GBL_SPLIT Allocate global address register for use as DMA SPLIT. Will allo- cated one of the following DMA registers: Global Address Register A Global Address Register B...
Page 72 DMA_SECCTL_WSYNCSTAT Return Value none Description This macro clears one of the condition flags in the DMA secondary con- trol register. See the TMS320C6000 Peripherals Reference Guide (liter- ature number SPRU190) for a description of the condition flags. Example DMA_CLEAR_CONDITION(hDma,DMA_SECCTL_BLOCKCOND); 4.6.5...
Page 73 4.6.6 DMA_CONFIG The DMA configuration structure used to set up a DMA channel Structure DMA_CONFIG Members DMA primary control register value UINT32 prictl DMA secondary control register value UINT32 secctl DMA source address register value UINT32 src DMA destination address register value UINT32 dst DMA transfer count register value UINT32 xfrcnt...
Page 74 Example DMA_CONFIG MyConfig = { 0x00000050, /* prictl */ 0x00000080, /* secctl */ 0x80000000, /* src 0x80010000, /* dst 0x00200040 /* xfrcnt */ DMA_ConfigA(hDma,&MyConfig); 4.6.8 DMA_ConfigB Sets up the DMA channel using the register values passed in Function void DMA_ConfigB( DMA_HANDLE hDma, UINT32 prictl, UINT32 secctl,...
Page 75 4.6.9 DMA_FreeGlobalReg Frees a global DMA register previously allocated by calling DMA_AllocGlobalReg() Function void DMA_FreeGlobalReg( UINT32 RegId Arguments Global register ID obtained RegId from DMA_AllocGlobal- Reg(). Return Value none Description This function frees a global DMA register that was pre- viously allocated by calling DMA_AllocGlobalReg().
Page 76 Condition, 0 if clear, 1 if set Condtion Description This macro gets one of the condition flags in the DMA secondary con- trol register. See the TMS320C6000 Peripherals Reference Guide (liter- ature number SPRU190) for a description of the condition flags. Example if (DMA_GET_CONDITION(hDma,DMA_SECCTL_BLOCKCOND)) { /* user DMA configuration */ 4.6.11...
Page 77 4.6.12 DMA_GetGlobalReg Reads a global DMA register that was previously allocated by calling DMA_AllocGlobalReg() Function UINT32 DMA_GetGlobalReg( UINT32 RegId Arguments Global register ID obtained from DMA_Alloc- RegId GlobalReg(). Return Value Value read from register Register Value Description This function returns the register value of the global DMA register that was previously allocated by calling DMA_AllocGlobalReg().
Page 78 4.6.13 DMA_GetStatus Reads the status bits of the DMA channe Function UINT32 DMA_GetStatus( DMA_HANDLE hDma Arguments Handle to DMA channel, see DMA_Open() hDma Return Value Current DMA channel status: Status Value DMA_STATUS_STOPPED DMA_STATUS_RUNNING DMA_STATUS_PAUSED DMA_STATUS_AUTORUNNING Description This function reads the STATUS bits of the DMA channel Example while (DMA_Status(hDma)==DMA_STATUS_RUNNING);...
Page 79 You have a choice of using integer constants, integer variables, or the symbolic constants for arguments. All field values are right justified. Refer to the TMS320C6000 Peripherals Reference Guide (literature number SPRU190) for descriptions of the arguments. Example UINT32 AuxCtl;...
Page 80 You have a choice of using integer constants, integer variables, or the symbolic constants for arguments. All field values are right justified. Refer to the TMS320C6000 Peripherals Reference Guide (literature number SPRU190) for descriptions of the arguments. Example UINT32 Dst;...
Page 81 You have a choice of using integer constants, integer variables, or the symbolic constants for arguments. All field values are right justified. Refer to the TMS320C6000 Peripherals Reference Guide (literature number SPRU190) for descriptions of the arguments. Example UINT32 GblAddr;...
Page 82 You have a choice of using integer constants, integer variables, or the symbolic constants for arguments. All field values are right justified. Refer to the TMS320C6000 Peripherals Reference Guide (literature number SPRU190) for descriptions of the arguments. Example UINT32 GblCnt;...
Page 83 You have a choice of using integer constants, integer variables, or the symbolic constants for arguments. All field values are right justified. Refer to the TMS320C6000 Peripherals Reference Guide (literature number SPRU190) for descriptions of the arguments. Example UINT32 GblIdx;...
Page 84 4.6.19 DMA_MK_PRICTL Makes a value suitable for a primary control register Macro DMA_MK_PRICTL( start, srcdir, dstdir, esize, split, cntrld, index, rsync, wsync, pri, tcint, emod, srcrld, dstrld Arguments Start bits: start DMA_PRICTL_START_STOP DMA_PRICTL_START_NORMAL DMA_PRICTL_START_PAUSE DMA_PRICTL_START_AUTOINIT Source modification: srcdir DMA_PRICTL_SRCDIR_NONE DMA_PRICTL_SRCDIR_INC DMA_PRICTL_SRCDIR_DEC DMA_PRICTL_SRCDIR_IDX Destination modification:...
Page 85 Split channel mode: split DMA_PRICTL_SPLIT_DISABLE DMA_PRICTL_SPLIT_A DMA_PRICTL_SPLIT_B DMA_PRICTL_SPLIT_C DMA_GBL_SPLIT register ID. See DMA_Al- locGlobalReg(). Count reload: cntrld DMA_PRICTL_CNTRLD_NA DMA_PRICTL_CNTRLD_A DMA_PRICTL_CNTRLD_B DMA_GBL_CNTRLD register ID. See DMA_Al- locGlobalReg(). Index: index DMA_PRICTL_INDEX_NA DMA_PRICTL_INDEX_A DMA_PRICTL_INDEX_B DMA_GBL_INDEX register ID. See DMA_Al- locGlobalReg(). CSL API Reference 4-37...
Page 86 Read synchronization: rsync DMA_PRICTL_RSYNC_NONE DMA_PRICTL_RSYNC_TINT0 DMA_PRICTL_RSYNC_TINT1 DMA_PRICTL_RSYNC_SDINT DMA_PRICTL_RSYNC_EXTINT4 DMA_PRICTL_RSYNC_EXTINT5 DMA_PRICTL_RSYNC_EXTINT6 DMA_PRICTL_RSYNC_EXTINT7 DMA_PRICTL_RSYNC_DMAINT0 DMA_PRICTL_RSYNC_DMAINT1 DMA_PRICTL_RSYNC_DMAINT2 DMA_PRICTL_RSYNC_DMAINT3 DMA_PRICTL_RSYNC_XEVT0 DMA_PRICTL_RSYNC_REVT0 DMA_PRICTL_RSYNC_XEVT1 DMA_PRICTL_RSYNC_REVT1 DMA_PRICTL_RSYNC_DSPINT DMA_PRICTL_RSYNC_XEVT2 DMA_PRICTL_RSYNC_REVT2 4-38...
Page 87 Write synchronization: wsync DMA_PRICTL_WSYNC_NONE DMA_PRICTL_WSYNC_TINT0 DMA_PRICTL_WSYNC_TINT1 DMA_PRICTL_WSYNC_SDINT DMA_PRICTL_WSYNC_EXTINT4 DMA_PRICTL_WSYNC_EXTINT5 DMA_PRICTL_WSYNC_EXTINT6 DMA_PRICTL_WSYNC_EXTINT7 DMA_PRICTL_WSYNC_DMAINT0 DMA_PRICTL_WSYNC_DMAINT1 DMA_PRICTL_WSYNC_DMAINT2 DMA_PRICTL_WSYNC_DMAINT3 DMA_PRICTL_WSYNC_XEVT0 DMA_PRICTL_WSYNC_REVT0 DMA_PRICTL_WSYNC_XEVT1 DMA_PRICTL_WSYNC_REVT1 DMA_PRICTL_WSYNC_DSPINT DMA_PRICTL_WSYNC_XEVT2 DMA_PRICTL_WSYNC_REVT2 Priority: DMA_PRICTL_PRI_CPU DMA_PRICTL_PRI_DMA Transfer complete interrupt: tcint DMA_PRICTL_TCINT_DISABLE DMA_PRICTL_TCINT_ENABLE Frame sync: DMA_PRICTL_FS_DISABLE DMA_PRICTL_FS_RSYNC Emulation mode: emod DMA_PRICTL_EMOD_NOHALT DMA_PRICTL_EMOD_HALT CSL API Reference 4-39...
Page 88 You have a choice of using integer constants, integer variables, or the symbolic constants for arguments. All field values are right justified. Refer to the TMS320C6000 Peripherals Reference Guide (literature number SPRU190) for descriptions of the arguments. 4-40...
Page 89 Example UINT32 PriCtl; /* you can do this / PriCtl = DMA_MK_PRICTL(0,1,1,0,0,0,0,0,0,0,0,0,0,0,0); / or to be more readable, you can do this */ PriCtl = DMA_MK_PRICTL( DMA_PRICTL_START_STOP, DMA_PRICTL_SRCDIR_INC, DMA_PRICTL_DSTDIR_INC, DMA_PRICTL_ESIZE_32BIT, DMA_PRICTL_SPLIT_DISABLE, DMA_PRICTL_CNTRLD_NA, DMA_PRICTL_INDEX_NA, DMA_PRICTL_RSYNC_NONE, DMA_PRICTL_WSYNC_NONE, DMA_PRICTL_PRI_CPU, DMA_PRICTL_TCINT_DISABLE, DMA_PRICTL_FS_DISABLE, DMA_PRICTL_EMOD_NOHALT, DMA_PRICTL_SRCRLD_NONE, DMA_PRICTL_DSTRLD_NONE 4.6.20 DMA_MK_SECCTL...
Page 90 Frame complete interrupt enable: frameie DMA_SECCTL_FRAMEIE_DISABLE DMA_SECCTL_FRAMEIE_ENABLE Last frame interrupt enable: lastie DMA_SECCTL_LASTIE_DISABLE DMA_SECCTL_LASTIE_ENABLE Block transfer complete interrupt enable: blockie DMA_SECCTL_BLOCKIE_DISABLE DMA_SECCTL_BLOCKIE_ENABLE Dropped read sync interrupt enable: rdropie DMA_SECCTL_RDROPIE_DISABLE DMA_SECCTL_RDROPIE_ENABLE Dropped write sync interrupt enable: wdropie DMA_SECCTL_WDROPIE_DISABLE DMA_SECCTL_WDROPIE_ENABLE DMAC pin control: dmacen DMA_SECCTL_DMACEN_LOW DMA_SECCTL_DMACEN_HIGH...
Page 91 You have a choice of using integer constants, integer variables, or the symbolic constants for arguments. All field values are right justified. Refer to the TMS320C6000 Peripherals Reference Guide (literature number SPRU190) for descriptions of the arguments. Example UINT32 SecCtl;...
Page 92 You have a choice of using integer constants, integer variables, or the symbolic constants for arguments. All field values are right justified. Refer to the TMS320C6000 Peripherals Reference Guide (literature number SPRU190) for descriptions of the arguments. Example UINT32 Src;...
Page 93 You have a choice of using integer constants, integer variables, or the symbolic constants for arguments. All field values are right justified. Refer to the TMS320C6000 Peripherals Reference Guide (literature number SPRU190) for descriptions of the arguments. Example UINT32 XfrCnt;...
Page 94 4.6.23 DMA_Open Opens a DMA channel for use Function DMA_HANDLE DMA_Open( int ChaNum, UINT32 Flags Arguments DMA channel to open: ChaNum DMA_CHAANY DMA_CHA0 DMA_CHA1 DMA_CHA2 DMA_CHA3 Open flags (logical OR of any of the following): Flags DMA_OPEN_RESET Return Value Handle to newly opened device Device Handle Description Before a DMA channel can be used, it must first be opened by this...
Page 95 4.6.24 DMA_Pause Pauses the DMA channel by setting the START bits in the primary control register accordingly Function void DMA_Pause( DMA_HANDLE hDma Arguments Handle to DMA channel. See DMA_Open() hDma Return Value none Description This function pauses the DMA channel by setting the START bits in the primary control register accordingly.
Page 96 4.6.26 DMA_SetAuxCtl Sets the DMA AUXCTL register Function void DMA_SetAuxCtl( UINT32 AuxCtl Arguments Value to set AUXCTL regis- AuxCtl ter to Return Value none Description This function sets the DMA AUXCTL register. You may use the DMA_MK_AUXCTL macro to construct the register value based on field values.
Page 97 4.6.28 DMA_Start Starts a DMA channel running without autoinitialization Function void DMA_Start( DMA_HANDLE hDma Arguments Handle to DMA channel, see DMA_Open() hDma Return Value none Description Starts a DMA channel running without autoinitialization by setting the START bits in the primary control register accordingly. See also DMA_Pause(), DMA_Stop(), and DMA_AutoStart().
Page 98 4.6.31 DMA_Wait Enters a spin loop that polls the DMA status bits until the DMA completes Function void DMA_Wait( DMA_HANDLE hDma Arguments Handle to DMA channel. See DMA_Open() hDma Return Value none Description This function enters a spin loop that polls the DMA status bits until the DMA completes.
Page 99: Edma
EDMA 4.7 EDMA 4.7.1 EDMA_AllocTable Allocates a parameter RAM table from PRAM Function EDMA_HANDLE EDMA_AllocTable( int TableNum Arguments Table number to allocate. Valid values are 0 to TableNum DMA_TABLE_CNT–1; –1 for any. Return Value Returns a device handle Device Handle Description This function allocates a parameter RAM table from PRAM.
Page 100 EDMA 4.7.3 EDMA_ClearChannel Clears the EDMA event flag in the EDMA channel event register Function void EDMA_ClearChannel( EDMA_HANDLE hEdma Arguments Device handle, see EDMA_Open(). hEdma Return Value none Description This function clears the EDMA event flag in the EDMA channel event register by writing to the appropriate bit in the EDMA event clear regis- ter (ECR).
Page 101 EDMA 4.7.5 EDMA_CONFIG The EDMA configuration structure used to set up an EDMA channel Structure EDMA_CONFIG Members Options UINT32 opt Source address UINT32 src Transfer count UINT32 cnt Destination address UINT32 dst Index UINT32 idx Element count reload and link address UINT32 rld Description This is the EDMA configuration structure used to set up an EDMA chan-...
Page 102 EDMA 4.7.6 EDMA_ConfigA Sets up the EDMA channel using the configuration structure Function void EDMA_ConfigA( EDMA_HANDLE hDma, EDMA_CONFIG *Config Arguments Device handle. See EDMA_Open() and EDMA_Al- hEdma locTable(). Pointer to an initialized configuration structure Config Return Value none Description Sets up the EDMA channel using the configuration structure. The val- ues of the structure are written to the EDMA PRAM entries.
Page 103 EDMA 4.7.7 EDMA_ConfigB Sets up the EDMA channel using the EDMA parameter arguments Function void EDMA_ConfigB( EDMA_HANDLE hEdma, UINT32 opt, UINT32 src, UINT32 cnt, UINT32 dst, UINT32 idx, UINT32 rld Arguments Device handle. See EDMA_Open() and EDMA_AllocT- hEdma able(). Options Source address Transfer count Destination address...
Page 104 EDMA Example EDMA_ConfigB(hEdma, 0x41200000, /* opt */ 0x80000000, /* src */ 0x00000040, /* cnt */ 0x80010000, /* dst */ 0x00000004 /* idx */ 0x00000000 /* rld */ 4.7.8 EDMA_DisableChannel Disables an EDMA channel Function void EDMA_DisableChannel( EDMA_HANDLE hEdma Arguments Device handle, see EDMA_Open(). hEdma Return Value none...
Page 105 EDMA 4.7.10 EDMA_FreeTable Frees up a PRAM table previously allocated Function void EDMA_FreeTable( EDMA_HANDLE hEdma Arguments Device handle. See EDMA_AllocTable(). hEdma Return Value none Description This function frees up a PRAM table previously allocated via EDMA_Al- locTable(). This function accepts the following device handles: From EDMA_AllocTable() Example EDMA_FreeTable(hEdmaTable);...
Page 106 EDMA 4.7.12 EDMA_GetPriQStatus Returns the value of the priority queue status register (PQSR) Function UINT32 EDMA_GetPriQStatus(); Arguments none Return Value Returns status of the priority queue Status Description Returns the value of the priority queue status register (PQSR). May be the logical OR of any of the following: 0x00000001 –...
Page 107 You have a choice of using integer constants, integer variables, or the symbolic constants for arguments. All field values are right justified. Refer to the TMS320C6000 Peripherals Reference Guide (literature number SPRU190) for descriptions of the arguments. CSL API Reference...
Page 108 You have a choice of using integer constants, integer variables, or the symbolic constants for arguments. All field values are right justified. Refer to the TMS320C6000 Peripherals Reference Guide (literature number SPRU190) for descriptions of the arguments. Example UINT32 Dst;...
Page 109 You have a choice of using integer constants, integer variables, or the symbolic constants for arguments. All field values are right justified. Refer to the TMS320C6000 Peripherals Reference Guide (literature number SPRU190) for descriptions of the arguments. Example UINT32 Idx;...
Page 110 EDMA 4.7.19 EDMA_MK_OPT Makes a value suitable for the EDMA OPT parameter Macro EDMA_MK_OPT( link, tcc, tcint, dum, d2d, sum, s2d, esize, Arguments Frame sync: EDMA_OPT_FS_NO EDMA_OPT_FS_YES Link flag: link EDMA_OPT_LINK_NO EDMA_OPT_LINK_YES Transfer complete code: EDMA_OPT_TCC_OF(x) Transfer complete interrupt: tcint EDMA_OPT_TCINT_NO EDMA_OPT_TCINT_YES Destination address update mode:...
Page 111 You have a choice of using integer constants, integer variables, or the symbolic constants for arguments. All field values are right justified. Refer to the TMS320C6000 Peripherals Reference Guide (literature number SPRU190) for descriptions of the arguments. CSL API Reference...
Page 112 You have a choice of using integer constants, integer variables, or the symbolic constants for arguments. All field values are right justified. Refer to the TMS320C6000 Peripherals Reference Guide (literature number SPRU190) for descriptions of the arguments. 4-64...
Page 113 You have a choice of using integer constants, integer variables, or the symbolic constants for arguments. All field values are right justified. Refer to the TMS320C6000 Peripherals Reference Guide (literature number SPRU190) for descriptions of the arguments. Example UINT32 Src;...
Page 114 EDMA 4.7.22 EDMA_Open Opens an EDMA channel Function EDMA_HANDLE EDMA_Open( int ChaNum, UINT32 Flags Arguments EDMA channel to open: ChaNum EDMA_CHA_ANY EDMA_CHA_DSPINT EDMA_CHA_TINT0 EDMA_CHA_TINT1 EDMA_CHA_SDINT EDMA_CHA_EXTINT4 EDMA_CHA_EXTINT5 EDMA_CHA_EXTINT6 EDMA_CHA_EXTINT7 EDMA_CHA_TCC8 EDMA_CHA_TCC9 EDMA_CHA_TCC10 EDMA_CHA_TCC11 EDMA_CHA_XEVT0 EDMA_CHA_REVT0 EDMA_CHA_XEVT1 EDMA_CHA_REVT1 Open flags, logical OR of any of the following: Flags EDMA_OPEN_RESET EDMA_OPEN_ENABLE...
Page 115 If the EDMA_OPEN_ENABLE flag is specified, the channel will be enabled. If the channel cannot be opened, EDMA_HINV is returned. Refer to the TMS320C6000 Peripherals Reference Guide (literature number SPRU190) for details regarding the EDMA channels. EDMA_HQDMA Example EDMA_HANDLE hEdma;...
Page 116 EDMA 4.7.24 EDMA_SetChannel Triggers an EDMA channel by writing to appropriate bit in the event set register (ESR) Function void EDMA_SetChannel( EDMA_HANDLE hEdma Arguments Device handle obtained by EDMA_Open(). hEdma Return Value none Description Software triggers an EDMA channel by writing to the appropriate bit in the EDMA event set register (ESR).
Page 117: Emif
EMIF 4.8 EMIF 4.8.1 EMIF_CONFIG Structure used to set up the EMIF peripheral Structure EMIF_CONFIG Members EMIF global control register value UINT32 gblctl CE0 space control register value UINT32 ce0ctl CE1 space control register value UINT32 ce1ctl CE2 space control register value UINT32 ce2ctl CE3 space control register value UINT32 ce3ctl...
Page 118 EMIF Description Sets up the EMIF using the configuration structure. The values of the structure are written to the EMIF registers. See also EMIF_ConfigB() and EMIF_CONFIG. Example EMIF_CONFIG MyConfig = { 0x00003060, /* gblctl */ 0x00000040, /* ce0ctl */ 0x404F0323, /* ce1ctl */ 0x00000030, /* ce2ctl */ 0x00000030, /* ce3ctl */ 0x72270000, /* sdctl...
Page 119 EMIF Description Sets up the EMIF using the register value arguments. The arguments are written to the EMIF registers. See also EMIF_ConfigA(). Example EMIF_ConfigB( 0x00003060, /* gblctl */ 0x00000040, /* ce0ctl */ 0x404F0323, /* ce1ctl */ 0x00000030, /* ce2ctl */ 0x00000030, /* ce3ctl */ 0x72270000, /* sdctl 0x00000410, /* sdtim...
Page 120 You have a choice of using integer constants, integer variables, or the symbolic constants for arguments. All field values are right justified. Refer to the TMS320C6000 Peripherals Reference Guide (literature number SPRU190) for descriptions of the arguments. Example UINT32 CeCtl;...
Page 121 EMIF 4.8.5 EMIF_MK_GBLCTL Makes a value suitable for the EMIF global control register Macro EMIF_MK_GBLCTL( rbtr8, sscrt, clk2en, clk1en, sscen, sdcen, nohold Arguments Requester arbitration mode: rbtr8 EMIF_GBLCTL_RBTR8_NA EMIF_GBLCTL_RBTR8_HPRI EMIF_GBLCTL_RBTR8_8ACC SBSRAM clock rate select: sscrt EMIF_GBLCTL_SSCRT_NA EMIF_GBLCTL_SSCRT_CPUOVR2 EMIF_GBLCTL_SSCRT_CPU CLKOUT2 enable: clk2en EMIF_GBLCTL_CLK2EN_NA EMIF_GBLCTL_CLK2EN_DISABLE...
Page 122 You have a choice of using integer constants, integer variables, or the symbolic constants for arguments. All field values are right justified. Refer to the TMS320C6000 Peripherals Reference Guide (literature number SPRU190) for descriptions of the arguments. Example UINT32 GblCtl;...
Page 123 EMIF 4.8.6 EMIF_MK_SDCTL Makes a value suitable for the EMIF SDRAM control register Macro EMIF_MK_SDCTL( trc, trp, trcd, init, rfen, sdwid, sdcsz, sdrsz, sdbsz Arguments SDRAM Trc value: EMIF_SDCTL_TRC_OF(x) SDRAM Trp value: EMIF_SDCTL_TRP_OF(x) SDRAM Trcd value: trcd EMIF_SDCTL_TRCD_OF(x) Forces initialization of all SDRAM: init EMIF_SDCTL_INIT_NO EMIF_SDCTL_INIT_YES...
Page 124 You have a choice of using integer constants, integer variables, or the symbolic constants for arguments. All field values are right justified. Refer to the TMS320C6000 Peripherals Reference Guide (literature number SPRU190) for descriptions of the arguments. Example UINT32 SdCtl;...
Page 125 EMIF 4.8.7 EMIF_MK_SDEXT Makes a value suitable for the EMIF SDRAM extension register Macro EMIF_MK_SDEXT( tcl, tras, trrd, twr, thzp, rd2rd, rd2deac, rd2wr, r2wdqm, wr2wr, wr2deac, wr2rd Arguments SDRAM CAS latency: EMIF_SDEXT_TCL_OF(x) SDRAM Tras value: tras EMIF_SDEXT_TRAS_OF(x) SDRAM Trrd value: trrd EMIF_SDEXT_TRRD_OF(x) SDRAM Twr value:...
Page 126 You have a choice of using integer constants, integer variables, or the symbolic constants for arguments. All field values are right justified. Refer to the TMS320C6000 Peripherals Reference Guide (literature number SPRU190) for descriptions of the arguments. Example UINT32 SdExt;...
Page 127 You have a choice of using integer constants, integer variables, or the symbolic constants for arguments. All field values are right justified. Refer to the TMS320C6000 Peripherals Reference Guide (literature number SPRU190) for descriptions of the arguments. Example UINT32 SdTim;...
Page 128 EMIF 4.8.9 EMIF_SUPPORT A compile time constant that has a value of 1 if the device supports the EMIF module Constant EDMA_SUPPORT Description Compile time constant that has a value of 1 if the device supports the EMIF module and 0 otherwise. You are not required to use this constant.
Page 129: Hpi
4.9 HPI 4.9.1 HPI_GetDspint Reads the DSPINT bit from HPIC register Function UINT32 HPI_GetDspint(); Arguments none Return Value Returns the value of the DSPINT bit, 0 or 1 DSPINT Description This function reads the DSPINT bit from the HPIC register. Example if (HPI_GetDspint()) { 4.9.2...
Page 130 4.9.5 HPI_GetHrdy Returns the value of the HRDY bit of the HPIC register Function UINT32 HPI_GetHrdy(); Arguments none Return Value Returns the value of the HRDY HRDY bit, 0 or 1 Description This function returns the value of the HRDY bit of the HPIC register.
Page 131 Description This function writes the value to the HINT file of the HPIC register Example HPI_SetHint(0); HPI_SetHint(1); 4.9.9 HPI_SUPPORT A compile time constant whose value is 1 if the device supports the HPI module Constant HPI_SUPPORT Description Compile time constant that has a value of 1 if the device supports the HPI module and 0 otherwise.
Page 132: Irq
4.10 IRQ 4.10.1 IRQ_Clear Clears the event flag from the IFR register Function void IRQ_Clear( UINT32 EventId Arguments Event ID. See IRQ_EVT_NNNN for a complete list of EventId events. Return Value none Description Clears the event flag from the IFR register Example IRQ_Clear(IRQ_EVT_TINT0);...
Page 133 IRQ_EVT_XINT0 IRQ_EVT_RINT0 IRQ_EVT_XINT1 IRQ_EVT_RINT1 IRQ_EVT_XINT2 IRQ_EVT_RINT2 These are the IRQ events. Refer to the TMS320C6000 Peripherals Ref- Description erence Guide (literature number SPRU190) for more details regarding the events. 4.10.5 IRQ_Map Maps an event to a physical interrupt number by...
Page 134 4.10.6 IRQ_Set Sets the specified event by writing to the appropriate ISR register Function void IRQ_Set( UINT32 EventId Arguments Event ID. See IRQ_EVT_NNNN for a complete list of EventId events. Return Value none Description Sets the specified event by writing to the appropriate ISR register. This basically allows software triggering of events.
Page 135: Mcbsp
MCBSP 4.11 MCBSP 4.11.1 MCBSP_Close loses a MCBSP port previously opened via MCBSP_Open() Function void MCBSP_Close( MCBSP_HANDLE hMcbsp Arguments Handle to MCBSP port, see MCBSP_Open() hMcbsp Return Value none Description This function closes a MCBSP port previously opened via MCBSP_Open(). The registers for the MCBSP port are set to their pow- er-on defaults.
Page 136 MCBSP Example MCBSP_CONFIG MyConfig = { 0x00012001, /* spcr */ 0x00010140, /* rcr 0x00010140, /* xcr 0x00000000, /* srgr */ 0x00000000, /* mcr 0x00000000, /* rcer */ 0x00000000, /* xcer */ 0x00000000 /* pcr MCBSP_ConfigA(hMcbsp,&MyConfig); 4.11.3 MCBSP_ConfigA Sets up the MCBSP port using the configuration structure Function void MCBSP_ConfigA(...
Page 137 MCBSP 4.11.4 MCBSP_ConfigB Sets up the MCBSP port using the register values passed in Function void MCBSP_ConfigB( MCBSP_HANDLE hMcbsp, UINT32 spcr, UINT32 rcr, UINT32 xcr, UINT32 srgr, UINT32 mcr, UINT32 rcer, UINT32 xcer, UINT32 pcr Arguments Handle to MCBSP port. See MCBSP_Open() hMcbsp Serial port control register value spcr...
Page 138 MCBSP 4.11.5 MCBSP_EnableFsync nables the frame sync generator for the given port Function void MCBSP_EnableFsync( MCBSP_HANDLE hMcbsp Arguments Handle to MCBSP port. See MCBSP_Open() hMcbsp Return Value none Description Use this function to enable the frame sync generator for the given port. Example MCBSP_EnableFsync(hMcbsp);...
Page 139 MCBSP 4.11.8 MCBSP_EnableXmt nables the transmitter for the given port Function void MCBSP_EnableXmt( MCBSP_HANDLE hMcbsp Arguments Handle to MCBSP port. See hMcbsp MCBSP_Open() Return Value none Description Use this function to enable the transmitter for the given port. Example MCBSP_EnableXmt(hMcbsp); 4.11.9 MCBSP_GetPins Reads the values of the port pins when configured as...
Page 140 MCBSP 4.11.10 MCBSP_GetRcvAddr Returns the address of the data receive register (DRR) Function UINT32 MCBSP_GetRcvAddr( MCBSP_HANDLE hMcbsp Arguments Handle to MCBSP port. See MCBSP_Open() hMcbsp Return Value DRR register address Receive Address Description Returns the address of the data receive register, DRR. This value is needed when setting up DMA transfers to read from the serial port.
Page 141 MCBSP 4.11.13 MCBSP_GetXmtEventId Retrieves the transmit event ID for the given port Function UINT32 MCBSP_GetXmtEventId( MCBSP_HANDLE hMcbsp Arguments Handle to MCBSP port. See hMcbsp MCBSP_Open() Return Value Event ID of transmitter Transmit Event ID Description Retrieves the transmit event ID for the given port. Example UINT32 XmtEventId;...
Page 142 You have a choice of using integer constants, integer variables, or the symbolic constants for arguments. All field values are right justified. Refer to the TMS320C6000 Peripherals Reference Guide (literature number SPRU190) for descriptions of the arguments. 4-94...
Page 143 MCBSP Example UINT32 Mcr; /* you can do this / Mcr = MCBSP_MK_MCR(0,0,0,0,0,0); / or to be more readable, you can do this */ Mcr = MCBSP_MK_MCR( MCBSP_MCR_RMCM_CHENABLE, MCBSP_MCR_RPABLK_SF0, MCBSP_MCR_RPBBLK_SF1, MCBSP_MCR_XMCM_ENNOMASK, MCBSP_MCR_XPABLK_SF0, MCBSP_MCR_XPBBLK_SF1 4.11.15 MCBSP_MK_PCR Makes a value suitable for the pin control register Macro MCBSP_MK_PCR( clkrp,...
Page 144 MCBSP Transmit frame sync polarity: fsxp MCBSP_PCR_FSXP_ACTIVEHIGH MCBSP_PCR_FSXP_ACTIVELOW DX pin status: dxstat MCBSP_PCR_DXSTAT_0 MCBSP_PCR_DXSTAT_1 CLKS pin status: clksstat MCBSP_PCR_CLKSSTAT_0 MCBSP_PCR_CLKSSTAT_1 Receiver clock mode: clkrm MCBSP_PCR_CLKRM_INPUT MCBSP_PCR_CLKRM_OUTPUT Transmitter clock mode: clkxm MCBSP_PCR_CLKXM_INPUT MCBSP_PCR_CLKXM_OUTPUT Receive frame sync mode: fsrm MCBSP_PCR_FSRM_EXTERNAL MCBSP_PCR_FSRM_INTERNAL Transmit frame sync mode: fsxm MCBSP_PCR_FSXM_EXTERNAL MCBSP_PCR_FSXM_INTERNAL...
Page 145 You have a choice of using integer constants, integer variables, or the symbolic constants for arguments. All field values are right justified. Refer to the TMS320C6000 Peripherals Reference Guide (literature number SPRU190) for descriptions of the arguments. Example UINT32 Pcr;...
Page 146 You have a choice of using integer constants, integer variables, or the symbolic constants for arguments. All field values are right justified. Refer to the TMS320C6000 Peripherals Reference Guide (literature number SPRU190) for descriptions of the arguments. Example UINT32 Rcer;...
Page 147 MCBSP Receive element length in phase 1: rwdlen1 MCBSP_RCR_RWDLEN1_8BIT MCBSP_RCR_RWDLEN1_12BIT MCBSP_RCR_RWDLEN1_16BIT MCBSP_RCR_RWDLEN1_20BIT MCBSP_RCR_RWDLEN1_24BIT MCBSP_RCR_RWDLEN1_32BIT Receive frame length in phase 1: rfrlen1 MCBSP_RCR_RFRLEN1_OF(x) Receive phase 2: rphase2 MCBSP_RCR_RPHASE2_NA MCBSP_RCR_RPHASE2_NORMAL MCBSP_RCR_RPHASE2_OPPOSITE Receive data delay: rdatdly MCBSP_RCR_RDATDLY_0BIT MCBSP_RCR_RDATDLY_1BIT MCBSP_RCR_RDATDLY_2BIT Receive frame ignore: rfig MCBSP_RCR_RFIG_YES MCBSP_RCR_RFIG_NO Receive companding mode:...
Page 148 You have a choice of using integer constants, integer variables, or the symbolic constants for arguments. All field values are right justified. Refer to the TMS320C6000 Peripherals Reference Guide (literature number SPRU190) for descriptions of the arguments. Example UINT32 Rcr;...
Page 149 MCBSP 4.11.18 MCBSP_MK_SPCR Makes a value suitable for the serial port control register Macro MCBSP_MK_SPCR( rrst, rintm, dxena, clkstp, rjust, dlb, xrst, xintm, grst, frst Arguments Receiver reset: rrst MCBSP_SPCR_RRST_YES MCBSP_SPCR_RRST_NO Receiver interrupt mode: rintm MCBSP_SPCR_RINTM_RRDY MCBSP_SPCR_RINTM_EOS MCBSP_SPCR_RINTM_FRM MCBSP_SPCR_RINTM_RSYNCERR DX enabler: dxena MCBSP_SPCR_DXENA_NA MCBSP_SPCR_DXENA_OFF...
Page 150 You have a choice of using integer constants, integer variables, or the symbolic constants for arguments. All field values are right justified. Refer to the TMS320C6000 Peripherals Reference Guide (literature number SPRU190) for descriptions of the arguments. 4-102...
Page 151 MCBSP Example UINT32 Spcr; /* you can do this / Spcr = MCBSP_MK_SPCR(0,0,0,0,0,0,0,0,0,0); / or to be more readable, you can do this */ Spcr = MCBSP_MK_SPCR( MCBSP_SPCR_RRST_YES, MCBSP_SPCR_RINTM_RRDY, MCBSP_SPCR_DXENA_NA, MCBSP_SPCR_CLKSTP_DISABLE, MCBSP_SPCR_RJUST_RZF, MCBSP_SPCR_DLB_OFF, MCBSP_SPCR_XRST_YES, MCBSP_SPCR_XINTM_XRDY, MCBSP_SPCR_GRST_YES, MCBSP_SPCR_FRST_YES 4.11.19 MCBSP_MK_SRGR Makes a value suitable for the sample rate generator register Macro MCBSP_MK_SRGR(...
Page 152 You have a choice of using integer constants, integer variables, or the symbolic constants for arguments. All field values are right justified. Refer to the TMS320C6000 Peripherals Reference Guide (literature number SPRU190) for descriptions of the arguments. Example UINT32 Srgr;...
Page 153 You have a choice of using integer constants, integer variables, or the symbolic constants for arguments. All field values are right justified. Refer to the TMS320C6000 Peripherals Reference Guide (literature number SPRU190) for descriptions of the arguments. Example UINT32 Xcer;...
Page 154 MCBSP 4.11.21 MCBSP_MK_XCR Makes a value suitable for the transmit control register Macro MCBSP_MK_XCR( xwdrevrs, xwdlen1, xfrlen1, xphase2, xdatdly, xfig, xcompand, xwdlen2, xfrlen2, xphase Arguments Transmit 32-bit reversal: xwdrevrs MCBSP_XCR_XWDREVRS_NA MCBSP_XCR_XWDREVRS_DISABLE MCBSP_XCR_XWDREVRS_ENABLE Transmit element length in phase 1: xwdlen1 MCBSP_XCR_XWDLEN1_8BIT MCBSP_XCR_XWDLEN1_12BIT MCBSP_XCR_XWDLEN1_16BIT MCBSP_XCR_XWDLEN1_20BIT...
Page 155 You have a choice of using integer constants, integer variables, or the symbolic constants for arguments. All field values are right justified. Refer to the TMS320C6000 Peripherals Reference Guide (literature number SPRU190) for descriptions of the arguments. CSL API Reference...
Page 156 MCBSP Example UINT32 Xcr; /* you can do this / Xcr = MCBSP_MK_XCR(0,0,0,0,0,0,0,0,0,0); / or to be more readable, you can do this */ Xcr = MCBSP_MK_XCR( MCBSP_XCR_XWDREVRS_NA, MCBSP_XCR_XWDLEN1_8BIT, MCBSP_XCR_XFRLEN1_OF(0), MCBSP_XCR_XPHASE2_NA, MCBSP_XCR_XDATDLY_0BIT, MCBSP_XCR_XFIG_YES, MCBSP_XCR_XCOMPAND_MSB, MCBSP_XCR_XWDLEN2_8BIT, MCBSP_XCR_XFRLEN2_OF(0), MCBSP_XCR_XPHASE_SINGLE 4.11.22 MCBSP_Open Opens a McBSP port for use Function MCBSP_HANDLE MCBSP_Open( int DevNum,...
Page 157 MCBSP Example MCBSP_HANDLE hMcbsp; hMcbsp = MCBSP_Open(MCBSP_DEV0,MCBSP_OPEN_RESET); 4.11.23 MCBSP_PORT_CNT Compile time constant that holds the number of serial ports present on the current device Constant MCBSP_PORT_CNT Description Compile time constant that holds the number of serial ports present on the current device. Example #if (MCBSP_PORT_CNT==3) #endif...
Page 158 MCBSP Description Resets the given serial port. If you use INV for hMcbsp, all serial ports are reset. Actions Taken: All serial port registers are set to their power-on defaults. All associated interrupts are disabled and cleared Example MCBSP_Reset(hMcbsp); MCBSP_Reset(INV); 4.11.26 MCBSP_Rfull eads the RFULL bit of the serial port control register...
Page 159 MCBSP 4.11.28 MCBSP_RsyncErr Reads the RSYNCERR status bit of the SPCR register Function BOOL MCBSP_RsyncErr( MCBSP_HANDLE hMcbsp Arguments Handle to MCBSP port. See MCBSP_Open() hMcbsp Return Value Returns RSYNCERR bit of the SPCR register; 0 or 1 RSYNCERR Description Reads the RSYNCERR status bit of the SPCR register. A 1 indicates a receiver frame sync error.
Page 160 MCBSP 4.11.30 MCBSP_SUPPORT A compile time constant whose value is 1 if the device supports the MCBSP module Constant MCBSP_SUPPORT Description Compile time constant that has a value of 1 if the device supports the MCBSP module and 0 otherwise. You are not required to use this constant.
Page 161 MCBSP 4.11.33 MCBSP_Xrdy Reads the XRDY status bit of the SPCR register Function BOOL MCBSP_Xrdy( MCBSP_HANDLE hMcbsp Arguments Handle to MCBSP port. See MCBSP_Open() hMcbsp Return Value Returns XRDY status bit of SPCR; 0 or 1 XRDY Description Reads the XRDY status bit of the SPCR register. A 1 indicates the transmitter is ready to be written to.
Page 162: Pwr
4.12 PWR 4.12.1 PWR_ConfigB Sets up the power-down logic using the register value passed in Function void PWR_ConfigB( UINT32 pdctl Arguments Power-down control register value pdctl Return Value none Description Sets up the power-down logic using the register value passed in. You may use literal values for the argument or for readability.
Page 163 You have a choice of using integer constants, integer variables, or the symbolic constants for arguments. All field values are right justified. Refer to the TMS320C6000 Peripherals Reference Guide (literature number SPRU190) for descriptions of the arguments. Example UINT32 PdCtl;...
Page 164 Return Value none Description Calling this function forces the DSP to enter a power-down state. Refer to the TMS320C6000 Peripherals Reference Guide (literature number SPRU190) for a description of the power-down modes. Example PWR_PowerDown(PWR_PD2); 4.12.4 PWR_SUPPORT A compile time constant whose value is 1 if the device...
Page 165: Stdinc
STDINC 4.13 STDINC 4.13.1 BOOL Typedef BOOL Description typedef unsigned int BOOL; 4.13.2 FALSE Constant FALSE Description #ifndef FALSE #define FALSE ((BOOL)(0)) #endif 4.13.3 INT16 Typedef INT16 Description typedef short UINT16; 4.13.4 INT32 Typedef INT32 Description typedef int INT32; 4.13.5 INT40 Typedef INT40...
Page 166 STDINC 4.13.8 Constant Description #define NO ((BOOL)(0)) 4.13.9 TRUE Constant TRUE Description #ifndef TRUE #define TRUE ((BOOL)(1)) #endif 4.13.10 UINT16 Typedef UINT16 Description typedef unsigned short UINT16; 4.13.11 UINT32 Typedef UINT32 Description typedef unsigned int UINT32; 4.13.12 UINT40 Typedef UINT40 Description typedef unsigned long UINT40;...
Page 167: Timer
TIMER 4.14 TIMER 4.14.1 TIMER_Close Closes a previously opened timer device Function void TIMER_Close( TIMER_HANDLE hTimer Arguments Device handle. See TIMER_Open(). hTimer Return Value none Description Closes a previously opened timer device. See TIMER_Open(). The Following Tasks are Performed: The timer event is disabled and cleared The timer registers are set to their default values Example TIMER_Close(hTimer);...
Page 168 TIMER 4.14.3 TIMER_ConfigA Configure timer using configuration structure Function void TIMER_ConfigA( TIMER_HANDLE hTimer, TIMER_CONFIG *Config Arguments Device handle. See TIM- hTimer ER_Open(). Config Return Value none Description Sets up the timer device using the configuration structure. The values of the structure are written to the DMA regis- ters.
Page 169 TIMER Description Sets up the timer using the register values passed in. The register val- ues are written to the timer registers. The timer control register ( ctl ) is written last. See also TIMER_ConfigA(). You may use literal values for the arguments or for readability. You may use the TIMER_MK macros to create the register values based on field values.
Page 170 TIMER 4.14.8 TIMER_GetEventId Obtains the event ID for the timer device Function UINT32 TIMER_GetEventId( TIMER_HANDLE hTimer Arguments Device handle. See TIMER_Open(). hTimer Return Value IRQ Event ID for the timer device Event ID Description Use this function to obtain the event ID for the timer device. Example TimerEventId = TIMER_GetEventId(hTimer);...
Page 171 TIMER 4.14.11 TIMER_MK_CTL Makes a value suitable for the timer control register Macro TIMER_MK_CTL( func, invout, datout, pwid, hld, clksrc, invinp Arguments Function of TOUT pin: func TIMER_CTL_FUNC_GPIO TIMER_CTL_FUNC_TOUT TOUT inverter control: invout TIMER_CTL_INVOUT_NO TIMER_CTL_INVOUT_YES Data output: datout TIMER_CTL_DATOUT_0 TIMER_CTL_DATOUT_1 Pulse width: pwid TIMER_CTL_PWID_ONE...
Page 172 You have a choice of using integer constants, integer variables, or the symbolic constants for arguments. All field values are right justified. Refer to the TMS320C6000 Peripherals Reference Guide (literature number SPRU190) for descriptions of the arguments. Example UINT32 Ctl;...
Page 173 TIMER 4.14.12 TIMER_Open Opens a TIMER device for use Function TIMER_HANDLE TIMER_Open( int DevNum, UINT32 Flags Arguments Device Number: DevNum TIMER_DEVANY TIMER_DEV0 TIMER_DEV1 Open flags, logical OR of any of the follow- Flags ing: TIMER_OPEN_RESET Return Value Device handle Device Handle Description Before a TIMER device can be used, it must first be opened by this function.
Page 174 TIMER 4.14.14 TIMER_Reset Resets the timer device Function void TIMER_Reset( TIMER_HANDLE hTimer Arguments Device handle. See hTimer TIMER_Open(). Return Value none Description Resets the timer device. Disables and clears the interrupt event and sets the timer registers to default values. If INV is specified, all timer devices are reset.
Page 175 TIMER 4.14.17 TIMER_SetDataout Sets the data output value Function void TIMER_SetDatout( TIMER_HANDLE hTimer, int Val Arguments Device handle. See TIMER_Open(). hTimer 0 or 1 Return Value none Description Sets the data output value. Example TIMER_SetDatout(hTimer,0); 4.14.18 TIMER_SetPeriod Sets the timer period Function void TIMER_SetPeriod( TIMER_HANDLE hTimer,...
Page 176 TIMER 4.14.20 TIMER_SUPPORT A compile time constant whose value is 1 if the device supports the TIMER module Constant TIMER_SUPPORT Description Compile time constant that has a value of 1 if the device supports the TIMER module and 0 otherwise. You are not required to use this constant.
Page 177: Hal Reference
HAL because this could have an adverse effect on the service layer func- tionality. However, if you decide not to use the service layer, the HAL is avail- able for exclusive use. It is a good idea to have the TMS320C6000 Peripherals Reference Guide (literature number SPRU190) readily available when view- ing the HAL reference.
Page 178: Hal Reference Introduction
HAL Reference Introduction 5.1 HAL Reference Introduction The HAL offers a consistent orthogonal set of constants and macros used for manipulating peripheral registers symbolically. For every register and every field of every register, there are access identifiers as shown below. Memory Mapped Register Constants HPER_REG_ADDR Memory Mapped Register Macros...
Page 179 For example, if a field becomes larger in a future device, the MASK/SHIFT macros will be adjusted accordingly and hence, the GET/SET macros still work. It is a good idea to have the TMS320C6000 Peripherals Reference Guide handy when viewing the HAL reference. HAL Reference...
Page 180: Hcache
HCACHE 5.2 HCACHE 5.2.1 HCACHE_CCFG cache configuration register (RW) HCACHE_CCFG* Fields L2 operation mode (RW) HCACHE_CCFG_L2MODE invalidate L1D (RW) HCACHE_CCFG_ID invalidate L1P (RW) HCACHE_CCFG_IP L2 requestor priority (RW) HCACHE_CCFG_P *Only supported on devices with L2 cache 5.2.2 HCACHE_L2FBAR L2 cache flush base address register (RW) HCACHE_L2FBAR* Fields L2 flush base address...
Page 181 HCACHE 5.2.6 HCACHE_L1PFBAR L1 program cache flush base address register (RW) HCACHE_L1PFBAR* Fields L1P flush base address (RW) HCACHE_L1PFBAR_L1PFBAR *Only supported on devices with L2 cache 5.2.7 HCACHE_L1PFWC L1 program cache flush word count register (RW) HCACHE_L1PFWC* Fields L1P flush word count (RW) HCACHE_L1PFWC_L1PFWC *Only supported on devices with L2 cache 5.2.8...
Page 182 HCACHE 5.2.12 HCACHE_MAR Memory attribute registers 0–15 (RW) HCACHE_MAR0* (RW) HCACHE_MAR1* (RW) HCACHE_MAR2* (RW) HCACHE_MAR3* (RW) HCACHE_MAR4* (RW) HCACHE_MAR5* (RW) HCACHE_MAR6* (RW) HCACHE_MAR7* (RW) HCACHE_MAR8* (RW) HCACHE_MAR9* (RW) HCACHE_MAR10* (RW) HCACHE_MAR11* (RW) HCACHE_MAR12* (RW) HCACHE_MAR13* (RW) HCACHE_MAR14* (RW) HCACHE_MAR15* Fields cacheability enable (RW) HCACHE_MAR_CE *Only supported on devices with L2 cache...
Page 183: Hchip
HCHIP 5.3 HCHIP 5.3.1 NULL register HCHIP_NULL (RW) HCHIP_NULL Fields none When a register exists on one device but not on another, the NULL register is used on the non-supporting device. This allows the HAL to still implement the GET/SET macros. 5.3.2 HCHIP_CSR Control status register...
Page 184 HCHIP 5.3.3 HCHIP_IFR Interrupt flag register (R) HCHIP_IFR (R) IFR Fields non-maskable interrupt flag HCHIP_IFR_NMIF interrupt 4 flag HCHIP_IFR_IF4 interrupt 5 flag HCHIP_IFR_IF5 interrupt 6 flag HCHIP_IFR_IF6 interrupt 7 flag HCHIP_IFR_IF7 interrupt 8 flag HCHIP_IFR_IF8 interrupt 9 flag HCHIP_IFR_IF9 interrupt 10 flag HCHIP_IFR_IF10 interrupt 11 flag HCHIP_IFR_IF11...
Page 185 HCHIP 5.3.5 HCHIP_ICR Interrupt clear register (W) HCHIP_ICR (W) ICR Fields interrupt 4 clear HCHIP_ICR_IC4 interrupt 5 clear HCHIP_ICR_IC5 interrupt 6 clear HCHIP_ICR_IC6 interrupt 7 clear HCHIP_ICR_IC7 interrupt 8 clear HCHIP_ICR_IC8 interrupt 9 clear HCHIP_ICR_IC9 interrupt 10 clear HCHIP_ICR_IC10 interrupt 11 clear HCHIP_ICR_IC11 interrupt 12 clear HCHIP_ICR_IC12...
Page 186 HCHIP 5.3.7 HCHIP_ISTP Interrupt service table pointer register (RW) HCHIP_ISTP (RW) ISTP Fields highest priority enabled interrupt HCHIP_ISTP_HPEINT interrupt service table base address (RW) HCHIP_ISTP_ISTB 5.3.8 Interrupt return pointer register HCHIP_IRP (RW) HCHIP_IRP (RW) IRP Fields interrupt return pointer (RW) HCHIP_IRP_IRP 5.3.9 HCHIP_NRP Non-maskable interrupt return pointer register...
Page 187 HCHIP 5.3.11 HCHIP_FADCR Floating-point adder configuration register (RW) HCHIP_FADCR* (RW) FADCR* Fields NAN1.L1 (RW) HCHIP_FADCR_L1NAN1 NAN2.L1 (RW) HCHIP_FADCR_L1NAN2 DEN1.L1 (RW) HCHIP_FADCR_L1DEN1 DEN2.L1 (RW) HCHIP_FADCR_L1DEN2 INVAL.L1 (RW) HCHIP_FADCR_L1INVAL INFO.L1 (RW) HCHIP_FADCR_L1INFO OVER.L1 (RW) HCHIP_FADCR_L1OVER INEX.L1 (RW) HCHIP_FADCR_L1INEX UNDER.L1 (RW) HCHIP_FADCR_L1UNDER Rmode.L1 (RW) HCHIP_FADCR_L1RMODE NAN1.L2 (RW) HCHIP_FADCR_L2NAN1...
Page 188 HCHIP 5.3.12 HCHIP_FAUCR Floating-point auxiliary configuration register (RW) HCHIP_FAUCR* (RW) FAUCR* Fields NAN1.S1 (RW) HCHIP_FAUCR_S1NAN1 NAN2.S1 (RW) HCHIP_FAUCR_S1NAN2 DEN1.S1 (RW) HCHIP_FAUCR_S1DEN1 DEN2.S1 (RW) HCHIP_FAUCR_S1DEN2 INVAL.S1 (RW) HCHIP_FAUCR_S1INVAL INFO.S1 (RW) HCHIP_FAUCR_S1INFO OVER.S1 (RW) HCHIP_FAUCR_S1OVER INEX.S1 (RW) HCHIP_FAUCR_S1INEX UNDER.S1 (RW) HCHIP_FAUCR_S1UNDER UNORD.S1 (RW) HCHIP_FAUCR_S1UNORD DIV0.S1 (RW) HCHIP_FAUCR_S1DIV0...
Page 189 HCHIP 5.3.13 HCHIP_FMCR Floating-point multiplier configuration register (RW) HCHIP_FMCR* (RW) FMCR* Fields NAN1.M1 (RW) HCHIP_FMCR_M1NAN1 NAN2.M1 (RW) HCHIP_FMCR_M1NAN2 DEN1.M1 (RW) HCHIP_FMCR_M1DEN1 DEN2.M1 (RW) HCHIP_FMCR_M1DEN2 INVAL.M1 (RW) HCHIP_FMCR_M1INVAL INFO.M1 (RW) HCHIP_FMCR_M1INFO OVER.M1 (RW) HCHIP_FMCR_M1OVER INEX.M1 (RW) HCHIP_FMCR_M1INEX UNDER.M1 (RW) HCHIP_FMCR_M1UNDER Rmode.M1 (RW) HCHIP_FMCR_M1RMODE NAN1.M2 (RW) HCHIP_FMCR_M2NAN1...
Page 190: Hdma
HDMA 5.4 HDMA 5.4.1 DMA auxiliary control register HDMA_AUXCTL (RW) HDMA_AUXCTL* Fields DMA channel priority (RW) HDMA_AUXCTL_CHPRI auxiliary channel priority mode (RW) HDMA_AUXCTL_AUXPRI * only supported on devices with DMA 5.4.2 HDMA_PRICTL DMA primary control register (RW) HDMA_PRICTL0* (RW) HDMA_PRICTL1* (RW) HDMA_PRICTL2* (RW) HDMA_PRICTL3* Fields...
Page 191 HDMA 5.4.3 HDMA_SECCTL DMA secondary control register (RW) HDMA_SECCTL0* (RW) HDMA_SECCTL1* (RW) HDMA_SECCTL2* (RW) HDMA_SECCTL3* Fields split transfer overrun receive condition (RW) HDMA_SECCTL_SXCOND split transfer overrun receive interrupt en- (RW) HDMA_SECCTL_SXIE able (RW) HDMA_SECCTL_FRAMECOND frame complete condition frame complete interrupt enable (RW) HDMA_SECCTL_FRAMEIE last frame condition (RW) HDMA_SECCTL_LASTCOND...
Page 192 HDMA 5.4.5 HDMA_DST DMA destination address register (RW) HDMA_DST0* (RW) HDMA_DST1* (RW) HDMA_DST2* (RW) HDMA_DST3* Fields destination address (RW) HDMA_DST_DST * only supported on devices with DMA 5.4.6 HDMA_XFRCNT DMA transfer count register (RW) HDMA_XFRCNT0* (RW) HDMA_XFRCNT1* (RW) HDMA_XFRCNT2* (RW) HDMA_XFRCNT3* Fields element count (RW) HDMA_XFRCNT_ELECNT...
Page 193: Hedma
HEDMA 5.5 HEDMA 5.5.1 quick EDMA options register HEDMA_OPT quick EDMA options pseudo register EDMA channel 0 options EDMA channel 1 options EDMA channel 2 options EDMA channel 3 options EDMA channel 4 options EDMA channel 5 options EDMA channel 6 options EDMA channel 7 options EDMA channel 8 options EDMA channel 9 options...
Page 194 HEDMA Table Continued 2-dimensional source (RW) HEDMA_OPT_2DS element size (RW) HEDMA_OPT_ESIZE priority level (RW) HEDMA_OPT_PRI * only supported on devices with EDMA + all of the macros apply for the options member of a PRAM table for both read and write ++ this field ignored for quick DMA registers 5-18...
Page 195 HEDMA 5.5.2 HEDMA_SRC quick EDMA source address register quick EDMA source address pseudo register EDMA channel 0 source address EDMA channel 1 source address EDMA channel 2 source address EDMA channel 3 source address EDMA channel 4 source address EDMA channel 5 source address EDMA channel 6 source address EDMA channel 7 source address EDMA channel 8 source address...
Page 196 HEDMA 5.5.3 HEDMA_CNT quick EDMA transfer count register quick EDMA transfer count pseudo register EDMA channel 0 transfer count EDMA channel 1 transfer count EDMA channel 2 transfer count EDMA channel 3 transfer count EDMA channel 4 transfer count EDMA channel 5 transfer count EDMA channel 6 transfer count EDMA channel 7 transfer count EDMA channel 8 transfer count...
Page 197 HEDMA 5.5.4 HEDMA_DST quick EDMA destination address register quick EDMA destination address pseudo register EDMA channel 0 destination address EDMA channel 1 destination address EDMA channel 2 destination address EDMA channel 3 destination address EDMA channel 4 destination address EDMA channel 5 destination address EDMA channel 6 destination address EDMA channel 7 destination address EDMA channel 8 destination address...
Page 198 HEDMA 5.5.5 HEDMA_IDX quick EDMA index register quick EDMA index pseudo register EDMA channel 0 index EDMA channel 1 index EDMA channel 2 index EDMA channel 3 index EDMA channel 4 index EDMA channel 5 index EDMA channel 6 index EDMA channel 7 index EDMA channel 8 index EDMA channel 9 index...
Page 199 HEDMA 5.5.6 HEDMA_RLD EDMA channel 0 element reload & link EDMA channel 1 element reload & link EDMA channel 2 element reload & link EDMA channel 3 element reload & link EDMA channel 4 element reload & link EDMA channel 5 element reload & link EDMA channel 6 element reload &...
Page 200 HEDMA 5.5.8 HEDMA_CIPR Channel interrupt pending register (RW) HEDMA_CIPR* Fields interrupt 0 pending (RW) HEDMA_CIPR_CIP0 interrupt 1 pending (RW) HEDMA_CIPR_CIP1 interrupt 2 pending (RW) HEDMA_CIPR_CIP2 interrupt 3 pending (RW) HEDMA_CIPR_CIP3 interrupt 4 pending (RW) HEDMA_CIPR_CIP4 interrupt 5 pending (RW) HEDMA_CIPR_CIP5 interrupt 6 pending (RW) HEDMA_CIPR_CIP6 interrupt 7 pending...
Page 201 HEDMA 5.5.9 HEDMA_CIER Channel interrupt enable register (RW) HEDMA_CIER* Fields interrupt 0 enable (RW) HEDMA_CIER_CIE0 interrupt 1 enable (RW) HEDMA_CIER_CIE1 interrupt 2 enable (RW) HEDMA_CIER_CIE2 interrupt 3 enable (RW) HEDMA_CIER_CIE3 interrupt 4 enable (RW) HEDMA_CIER_CIE4 interrupt 5 enable (RW) HEDMA_CIER_CIE5 interrupt 6 enable (RW) HEDMA_CIER_CIE6 interrupt 7 enable...
Page 202 HEDMA 5.5.11 HEDMA_ER EDMA event flag register (R) HEDMA_ER* Fields event 0 flag (R) HEDMA_ER_EVT0 event 1 flag (R) HEDMA_ER_EVT1 event 2 flag (R) HEDMA_ER_EVT2 event 3 flag (R) HEDMA_ER_EVT3 event 4 flag (R) HEDMA_ER_EVT4 event 5 flag (R) HEDMA_ER_EVT5 event 6 flag (R) HEDMA_ER_EVT6 event 7 flag...
Page 203 HEDMA 5.5.12 HEDMA_EER EDMA event enable register (RW) HEDMA_EER* Fields event 0 enable (RW) HEDMA_EER_EE0 event 1 enable (RW) HEDMA_EER_EE1 event 2 enable (RW) HEDMA_EER_EE2 event 3 enable (RW) HEDMA_EER_EE3 event 4 enable (RW) HEDMA_EER_EE4 event 5 enable (RW) HEDMA_EER_EE5 event 6 enable (RW) HEDMA_EER_EE6 event 7 enable...
Page 204 HEDMA 5.5.13 HEDMA_ECR EDMA event clear register (RW) HEDMA_ECR* Fields event 0 clear (RW) HEDMA_ECR_EC0 event 1 clear (RW) HEDMA_ECR_EC1 event 2 clear (RW) HEDMA_ECR_EC2 event 3 clear (RW) HEDMA_ECR_EC3 event 4 clear (RW) HEDMA_ECR_EC4 event 5 clear (RW) HEDMA_ECR_EC5 event 6 clear (RW) HEDMA_ECR_EC6 event 7 clear...
Page 205 HEDMA 5.5.14 HEDMA_ESR EDMA event set register (RW) HEDMA_ESR* Fields event 0 set (RW) HEDMA_ESR_ES0 event 1 set (RW) HEDMA_ESR_ES1 event 2 set (RW) HEDMA_ESR_ES2 event 3 set (RW) HEDMA_ESR_ES3 event 4 set (RW) HEDMA_ESR_ES4 event 5 set (RW) HEDMA_ESR_ES5 event 6 set (RW) HEDMA_ESR_ES6 event 7 set...
Page 206: Hemif
HEMIF 5.6 HEMIF 5.6.1 global control register HEMIF_GBLCTL (RW) HEMIF_GBLCTL Fields map mode HEMIF_GBLCTL_MAP requester arbitration mode (RW) HEMIF_GBLCTL_RBTR8 SBSRAM clock rate select (RW) HEMIF_GBLCTL_SSCRT CLKOUT2 enable (RW) HEMIF_GBLCTL_CLK2EN CLKOUT1 enable (RW) HEMIF_GBLCTL_CLK1EN SSCLK enable (RW) HEMIF_GBLCTL_SSCEN SDCLK enable (RW) HEMIF_GBLCTL_SDCEN external hold disable (RW) HEMIF_GBLCTL_NOHOLD HOLDA output control...
Page 207 HEMIF 5.6.3 HEMIF_SDCTL SDRAM control register (RW) HEMIF_SDCTL Fields Trc value (RW) HEMIF_SDCTL_TRC Trp value (RW) HEMIF_SDCTL_TRP Trcd value (RW) HEMIF_SDCTL_TRCD SDRAM initialization HEMIF_SDCTL_INIT refresh enable (RW) HEMIF_SDCTL_RFEN SDRAM width select (RW) HEMIF_SDCTL_SDWID SDRAM column size (RW) HEMIF_SDCTL_SDCSZ SDRAM row size (RW) HEMIF_SDCTL_SDRSZ SDRAM bank size (RW) HEMIF_SDCTL_SDBSZ...
Page 208: Hhpi
HHPI 5.7 HHPI 5.7.1 HPI control register HHPI_HPIC (RW) HHPI_HPIC* Fields halfword ordering bit HHPI_HPIC_HWOB host to CPU interrupt (RW) HHPI_HPIC_DSPINT DSP to host interrupt (RW) HHPI_HPIC_HINT ready signal to host HHPI_HPIC_HRDY host fetch request HHPI_HPIC_FETCH * only supported on devices with an HPI 5-32...
Page 209: Hirq
HIRQ 5.8 HIRQ 5.8.1 interrupt multiplexer low register HIRQ_MUXL (RW) HIRQ_MUXL Fields interrupt select 4 (RW) HIRQ_MUXL_INTSEL4 interrupt select 5 (RW) HIRQ_MUXL_INTSEL5 interrupt select 6 (RW) HIRQ_MUXL_INTSEL6 interrupt select 7 (RW) HIRQ_MUXL_INTSEL7 interrupt select 8 (RW) HIRQ_MUXL_INTSEL8 interrupt select 9 (RW) HIRQ_MUXL_INTSEL9 5.8.2 HIRQ_MUXH...
Page 210: Hmcbsp
HMCBSP 5.9 HMCBSP 5.9.1 HMCBSP_DRR data receive register (R) HMCBSP_DRR0 (R) HMCBSP_DRR1 (R) HMCBSP_DRR2* Fields data (R) HMCBSP_DRR_DRR * only on devices with three or more serial ports 5.9.2 HMCBSP_DXR data transmit register (W) HMCBSP_DXR0 (W) HMCBSP_DXR1 (W) HMCBSP_DXR2* Fields data (W) HMCBSP_DXR_DXR * only on devices with three or more serial ports...
Page 211 HMCBSP Table Continued sample rate generator reset (RW) HMCBSP_SPCR_GRST frame sync generator reset (RW) HMCBSP_SPCR_FRST * only on devices with three or more serial ports 5.9.4 HMCBSP_RCR receive control register (RW) HMCBSP_RCR0 (RW) HMCBSP_RCR1 (RW) HMCBSP_RCR2* Fields 32-bit reversal feature (RW) HMCBSP_RCR_RWDREVRS element length in phase 1 (RW) HMCBSP_RCR_RWDLEN1...
Page 212 HMCBSP 5.9.5 HMCBSP_XCR transmit control register (RW) HMCBSP_XCR0 (RW) HMCBSP_XCR1 (RW) HMCBSP_XCR2* Fields 32-bit reversal feature (RW) HMCBSP_XCR_XWDREVRS element length in phase 1 (RW) HMCBSP_XCR_XWDLEN1 frame length in phase 1 (RW) HMCBSP_XCR_XFRLEN1 phase 2 (RW) HMCBSP_XCR_XPHASE2 data delay (RW) HMCBSP_XCR_XDATDLY frame ignore (RW) HMCBSP_XCR_XFIG companding mode...
Page 213 HMCBSP 5.9.7 HMCBSP_MCR multichannel control register (RW) HMCBSP_MCR0 (RW) HMCBSP_MCR1 (RW) HMCBSP_MCR2* Fields receive multichannel selection enable (RW) HMCBSP_MCR_RMCM receive current subframe HMCBSP_MCR_RCBLK receive partition A subframe (RW) HMCBSP_MCR_RPABLK receive partition B subframe (RW) HMCBSP_MCR_RPBBLK transmit multichannel selection enable (RW) HMCBSP_MCR_XMCM transmit current subframe HMCBSP_MCR_XCBLK transmit partition A subframe...
Page 214 HMCBSP Table Continued enable element 2 in partition B (RW) HMCBSP_RCER_RCEB2 enable element 3 in partition B (RW) HMCBSP_RCER_RCEB3 enable element 4 in partition B (RW) HMCBSP_RCER_RCEB4 enable element 5 in partition B (RW) HMCBSP_RCER_RCEB5 enable element 6 in partition B (RW) HMCBSP_RCER_RCEB6 enable element 7 in partition B (RW) HMCBSP_RCER_RCEB7...
Page 215 HMCBSP Table Continued enable element 15 in partition A (RW) HMCBSP_XCER_XCEA15 enable element 0 in partition B (RW) HMCBSP_XCER_XCEB0 enable element 1 in partition B (RW) HMCBSP_XCER_XCEB1 enable element 2 in partition B (RW) HMCBSP_XCER_XCEB2 enable element 3 in partition B (RW) HMCBSP_XCER_XCEB3 enable element 4 in partition B (RW) HMCBSP_XCER_XCEB4...
Page 216 HMCBSP Table Continued receiver general purpose IO mode (RW) HMCBSP_PCR_RIOEN transmitter general purpose IO mode (RW) HMCBSP_PCR_XIOEN * only on devices with three or more serial ports 5-40...
Page 217: Hpwr
HPWR 5.10 HPWR 5.10.1 peripheral power-down control register HPWR_PDCTL (RW) HPWR_PDCTL* Fields DMA clock enable (RW) HPWR_PDCTL_DMA EMIF clock enable (RW) HPWR_PDCTL_EMIF MCBSP0 clock enable (RW) HPWR_PDCTL_MCBSP0 MCBSP1 clock enable (RW) HPWR_PDCTL_MCBSP1 MCBSP2 clock enable (RW) HPWR_PDCTL_MCBSP2 * only on 6202 and 6203 devices HAL Reference 5-41...
Page 218: Htimer
HTIMER 5.11 HTIMER 5.11.1 timer control register HTIMER_CTL (RW) HTIMER_CTL0 (RW) HTIMER_CTL1 Fields function of TOUT pin (RW) HTIMER_CTL_FUNC TOUT inverter control (RW) HTIMER_CTL_INVOUT data output (RW) HTIMER_CTL_DATOUT data in (RW) HTIMER_CTL_DATIN pulse width (RW) HTIMER_CTL_PWID GO bit (RW) HTIMER_CTL_GO hold (RW) HTIMER_CTL_HLD clock/pulse mode...
Page 219: A Glossary
Appendix A Appendix A Glossary address: The location of program code or data stored; an individually accessible memory location. A-law companding: See compress and expand (compand) . API: See application programming interface. API module: A set of API functions designed for a specific purpose. application programming interface (API): Used for proprietary applica- tion programs to interact with communications software or to conform to protocols from another vendor’s product.
Page 220 Glossary board support library (BSL): The BSL is a set of application programming interfaces (APIs) consisting of target side DSP code used to configure and control board level peripherals. boot: The process of loading a program into program memory. boot mode: The method of loading a program into program memory. The ’C6x DSP supports booting from external ROM or the host port interface (HPI).
Page 221 Glossary code: A set of instructions written to perform a task; a computer program or part of a program. coder-decoder or compression/decompression (codec): A device that codes in one direction of transmission and decodes in another direction of transmission. compiler: A computer program that translates programs in a high-level lan- guage into their assembly-language equivalents.
Page 222 Glossary DMA module: DMA is an API module that currently has two architectures used on ’C6x devices: DMA and EDMA (enhanced DMA). Devices such as the ’6201 have the DMA peripheral, whereas the ’6211 has the EDMA peripheral. DMA source: The module where the DMA data originates. DMA data is read from the DMA source.
Page 223 Glossary global interrupt enable bit (GIE): A bit in the control status register (CSR) that is used to enable or disable maskable interrupts. HAL: Hardware abstraction layer of the CSL. The HAL underlies the service layer and provides it a set of macros and constants for manipulating the peripheral registers at the lowest level.
Page 224 Glossary interrupt: A signal sent by hardware or software to a processor requesting attention. An interrupt tells the processor to suspend its current opera- tion, save the current task status, and perform a particular set of instruc- tions. Interrupts communicate with the operating system and prioritize tasks to be performed.
Page 225 Glossary µ-law companding: See compress and expand (compand) . maskable interrupt: A hardware interrupt that can be enabled or disabled through software. MCBSP: See multichannel buffered serial port; see also MCBSP module . MCBSP module: MCBSP is an API module that contains a set of functions for configuring the McBSP registers.
Page 226 Glossary peripheral: A device connected to and usually controlled by a host device. program cache: A fast memory cache for storing program instructions al- lowing for quick execution. program memory: Memory accessed through the ‘C6x’s program fetch in- terface. PWR: Power; see PWR module . PWR module: PWR is an API module that is used to configure the power- down control registers, if applicable, and to invoke various power-down modes.
Page 227 Glossary STDINC module: STDINC is an API module that defines some identifiers which are globally useful to everyone and are used throughout the CSL source code. synchronous-burst static random-access memory (SBSRAM): RAM whose contents does not have to be refreshed periodically. Transfer of data is at a fixed rate relative to the clock speed of the device, but the speed is increased.
Page 228 CACHE architectures 2-6 API module, defined A-1 CHIP 2-10 API module support CSL 2-7 DMA_AllocGlobalReg 4-22 DAT 2-8 TMS320C6000 devices, table 4-2 DAT routines 2-8 devices with DMA 2-9 API reference devices with EDMA 2-9 BOOL 4-117 DMA 2-11 CACHE 4-3...
Page 229 Index DAT_Support 4-18 EDMA_MK_DST 4-60 DAT_Wait 4-18 EDMA_MK_IDX 4-61 DMA 4-22 EDMA_MK_OPT 4-62 DMA_AutoStart 4-23 EDMA_MK_RLD 4-64 DMA_CHA_CNT 4-23 EDMA_MK_SRC 4-65 DMA_ClearCondition 4-24 EDMA_Open 4-66 DMA_Close 4-24 EDMA_Reset 4-67 DMA_CONFIG 4-25 EDMA_SetChannel 4-68 DMA_ConfigA 4-25 EDMA_SUPPORT 4-68 DMA_ConfigB 4-26 EDMA_TABLE_CNT 4-68 DMA_FreeGlobalReg 4-27 EMIF 4-69 DMA_GET_CONDITION 4-28...
Page 230 Index MCBSP_EnableFsync 4-90 TIMER_Pause 4-125 MCBSP_EnableRcv 4-90 TIMER_Reset 4-126 MCBSP_CEnableSrgr 4-90 TIMER_Resume 4-126 TIMER_SetCount 4-126 MCBSP_EnableXmt 4-91 TIMER_SetDataout 4-127 MCBSP_GetPins 4-91 TIMER_SetPeriod 4-127 MCBSP_GetRcvAddr 4-92 TIMER_Start 4-127 MCBSP_CGetRcvEventId 4-92 TIMER_SUPPORT 4-128 MCBSP_GetXmtAddr 4-92 TRUE 4-118 MCBSP_GetXmtEventId 4-93 UINT16 4-118 MCBSP_MK_MCR 4-93 UINT32 4-118 MCBSP_MK_PCR 4-95 UINT40 4-118...
Page 231 Index CACHE_SetPccMode, API reference 4-9 CSL module, defined A-3 CSL_Init, API_reference 4-10 CACHE_SUPPORT, API reference 4-9 CCS, defined A-2 central processing unit (CPU), defined A-2 CHIP API function table 3-3 API function table 3-3 API reference 4-19 API reference 4-11 defined A-2 defined A-3 module introduction 2-10...
Page 232 Index DMA_MK_AUXCTL, API reference 4-30 EDMA_MK_DST, API reference 4-60 EDMA_MK_IDX, API reference 4-61 DMA_MK_DST, API reference 4-32 EDMA_MK_RLD, API reference 4-64 DMA_MK_GBLADDR, API reference 4-33 EDMA_MK_SRC, API reference 4-65 DMA_MK_GBLCNT, API reference 4-34 EDMA_Open, API reference 4-66 DMA_MK_GBLIDX, API reference 4-35 EDMA_Reset, API reference 4-67 DMA_MK_PRICTL, API reference 4-36 EDMA_SetChannel, API reference 4-68...
Page 233 Index HCACHE 5-4 HEMIF_CECTL 5-30 HEMIF_GBLCTL 5-30 HAL (hardware abstraction layer) , reference HEMIF_SDCTL 5-31 HCACHE_CCFG 5-4 HEMIF_SDEXT 5-31 HCACHE_L1DFBAR 5-5 HEMIF_SDTIM 5-31 HCACHE_L1DFWC 5-5 HHPI_HPIC 5-32 HCACHE_L1PFBAR 5-5 HIRQ_EXTPOL 5-33 HCACHE_L1PFWC 5-5 HIRQ_MUXH 5-33 HCACHE_L2CBAR 5-4 HIRQ_MUXL 5-33 HCACHE_L2CLEAN 5-5 HMCBSP_DRR 5-34 HCACHE_L2CWC 5-4 HMCBSP_DXR 5-34...
Page 234 Index HCHIP_IER, HAL reference 5-9 HMCBSP_PDCTL, HAL reference 5-41 HMCBSP_RCER, HAL reference 5-37 HCHIP_IFR, HAL reference 5-8 HMCBSP_RCR, HAL reference 5-35 HCHIP_IRP, HAL reference 5-10 HMCBSP_SPCR, HAL reference 5-34 HCHIP_ISR, HAL reference 5-8 HMCBSP_SRGR, HAL reference 5-36 HCHIP_ISTP, HAL reference 5-10 HMCBSP_XCER, HAL reference 5-38 HCHIP_NRP, HAL reference 5-10 HMCBSP_XCR, HAL reference 5-36...
Page 235 Index MCBSP_GetXmtAddr, API reference 4-92 API function table 3-8 MCBSP_GetXmtEventId, API reference 4-93 API reference 4-84 MCBSP_MK_MCR, API reference 4-93 defined A-6 MCBSP_MK_PCR, API reference 4-95 module introduction 2-17 MCBSP_MK_RCER, API reference 4-97 IRQ module, defined A-6 MCBSP_MK_RCR, API reference 4-98 IRQ_Clear, API reference 4-84 MCBSP_MK_SPCR, API reference 4-101 IRQ_Disable, API reference 4-84...
Page 236 Index program cache, defined A-8 API reference 4-119 module introduction 2-22 program memory, defined A-8 using a TIMER device 2-22 using a TIMER device 2-22 API function table 3-10 timer, defined A-9 API reference 4-114 defined A-8 TIMER module, defined A-9 module introduction 2-20 TIMER_Close, API reference 4-119 PWR module, defined A-8...

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